Synchronization over packet-switching networks: theory and applications

Raffaele Noro PhD exam Lausanne, May 12 th 2000

Institute for computer Communications and Applications (ICA) Swiss Federal Institute of Technology, Lausanne (EPFL)

Outline



Synchronization over packet-switching networks:

 Needs and problems in packet-switching networks 

Theory:

 Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks  Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements 

Applications:

   Circuit Emulation over IP Networks Synchronous ATM Adaptation Layer (AAL) Digital TV over packet-switching networks 

Conclusions

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

2

Synchronization over packet-switching networks

• Voice • Digital TV • … • Voice • Digital TV • …

Synchronous application Synchronous application Application-specific synchronization Synchronous application Circuit-switching network Synchronous application Packet-switching network Synchronous

 Time Division Multiplexing  Periodic, fixed-size frames

Asynchronous

 Statistical Multiplexing  Bursty traffic, variable delay 

Global

,

static

synchronization 

Point-2-point

,

dynamic

synchronization

Requirement of point-to-point synchronization:

 Synchronize the terminal clocks (fast, efficiently) even in the presence of (higher) transmission jitter

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

3

Generation

The problem of synchronization in packet-switching networks - part I

Variable delay [

D

min …

D

max

] Constant delay Packet-switching network Playout de-jittering buffer

 Network jitter    Removed through the

de-jittering buffer

Controlled playout of data Optimal size:

B= (

D

max -

D

min )· C

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

4

The problem of synchronization in packet-switching networks - part II

Variable delay [

D

min …

D

max

] Constant delay Generation Packet-switching network Playout de-jittering buffer

 Physically dispersed clocks  Clock drift D

f /f

:

speed of writing



The Network Time Protocol (NTP, [Mills ’92]) provides only poor clock synchronization guarantees (millisecond accuracy at best)

speed of reading

(on average)  Overflow (or underflow) of the de-jittering buffer  Time-to-overflow (or underflow) depends on buffer size, bitrate, and drift

T



B C

 D

f

/

f

Example:

B

= 10 kbits,

C

= 1 Mbps, D

f /f

= 10 -4 (10 ms of jitter absorption in the buffer)

T= 100 seconds !!

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

5

Generation

The problem of synchronization in packet-switching networks

Variable delay [

D

min …

D

max

] Constant delay Packet-switching network Playout de-jittering buffer

 Objective

Control and reduce to zero the clock drift within a convergence time shorter than the time-to-overflow:

D

f /f



0 within t < T

T



B C

 D

f

/

f

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

6

Outline



Synchronization over packet-switching networks:

 Needs and problems in packet-switching networks 

Theory:

 Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks  Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements 

Applications:

   Circuit Emulation over IP Networks Synchronous ATM Adaptation Layer (AAL) Digital TV over packet-switching networks 

Conclusions

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

7

Synchronization of dispersed clocks

Generation Packet-switching network Playout Clock of transmitter Timestamps Synch algorithm Clock of receiver (free-running) Synchonized clock Timing of transm.

data

 

c Tx (t) Timing of receiv.+ jitter data c Rx (t)

Timestamping of data flow 1.

2.

Information about the timing of data Information about the transmitter clock Processing of timestamps   Jitter limits the ability of the algorithm to reduce D

f /f

to zero A convergence time is needed (… still not exceeding

T

)

c Tx (t) Timing of transm.

(original) Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

8

State of the art: Phase-Locked Loops (PLLs)

PLL synchronization algorithm

Jitter Reference clock signal x i

PLL

Phase comparator + Error signal Control signal

Loop filter

Local clock VCO (pulse generator) Periodic pulses Synchronized clock signal Pulse counter c Rx PLL (t)   Linear filtering of network jitter    Proportional-Integrative (PI) loop filter Controlled frequency of the local oscillator (VCO) Feedback used to trigger an error signal Characteristics of linear filtering   For better accuracy  narrower bandwidth With narrower bandwidth  longer response time

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

9

State of the art: Phase-Locked Loops (PLLs)

PLL synchronization algorithm

Jitter Reference clock signal x i

PLL

Phase comparator + Error signal Control signal

Loop filter

Local clock VCO (pulse generator) Periodic pulses Synchronized clock signal Pulse counter c Rx PLL (t)

Relative frequency drift,

K p

= 0.0015,

K i

= 0.000005

0.02

0.01

0 -0.01

-0.02

Network jitter Residual jitter Convergence time

2000 4000 6000 Time (s) 8000 10000

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

 

Accuracy

d

0 

network residual jitter jitter

Performance budget

 

d transient

0

time

  20    0 .

005 

The performance budget of PLLs (here: 0.005) results below the expected performance budget for packet-switching (ex: 0.2)



Introduction



Theory



Applications



Conclusions

10

Outline



Synchronization over packet-switching networks:

 Needs and problems in packet-switching networks 

Theory:

 Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks  Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements 

Applications:

   Circuit Emulation over IP Networks Synchronous ATM Adaptation Layer (AAL) Digital TV over packet-switching networks 

Conclusions

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

11

Least-square Linear Regression (LLR): statistical filtering of network jitter

Clock model: c Tx (t)= a c Rx (t)+ b [Mills, ’93; Cristian ‘89] y(t)= C Tx (t)

x N , y N x 1 , y 1

x(t)= C Rx (t)

Estimation of (a, b) with the a LLR N last collected (x, y)  N N   x i y i 2 y i     y i   2  y i b LLR   N y i   x i x i y i y i       y i y i 2

Each cycle is triggered by the reception of one timestamp Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

Recovered clock: c Tx LLR (t)= a LLR c Rx (t)+ b LLR 

Introduction



Theory



Applications



Conclusions

12

LLR circuitry and performance budget

0.02

0.01

y i

^ 2 x Mem.

Mem.

Mem.

Mem.

+ + + +

S y i S y i 2 S x i y i S x i

^ 2

x

N Slope computation +

 a LLR x

(1-

a

) Low-pass filter +

x a x

N + + x -

x i

Relative frequency drift,

N

= 1000,

a

= 0.98

c Rx (t)

+ x Timekeeping Network jitter



Accuracy

d 0



20

0 -0.01

-0.02

Residual jitter

2000 4000 6000 Time (s) 8000 10000

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

â LLR c Tx LLR (t) 

Performance budget

 

0.2

The performance budget of LLR (here: 0.2) is 1.

Better than for PLLs (10 to 100 times)

2.

Supports the needs of packet-switching applications



Introduction



Theory



Applications



Conclusions

13

10

Comparative perfomance of LLR and PLL

Accuracy (jitter resilience capability)

0% 90% 99% 99.9% Region of interest for packet-switching networks 100 1000

LLR: Accuracy/ Conv.time  0.25 / t ( t = 0.1 s for this example)

10000

PLL: Accuracy/ Conv.time  0.05

(nearly independent of t ) Convergence time (s)   Choose the parameters of LLR (

N,

a ), and of PLL (

K p , K i

) 

trade-off between accuracy and rapidity

The trade-off is much better with the LLR

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

14

Outline



Synchronization over packet-switching networks:

 Needs and problems in packet-switching networks 

Theory:

 Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks  Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements 

Applications:

   Circuit Emulation over IP Networks Synchronous ATM Adaptation Layer (AAL) Digital TV over packet-switching networks 

Conclusions

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

15

Applications and synchronization (I): Circuit Emulation over IP networks

Objective  Support of circuit-switched leased-lines (e.g., T1) with high-speed IP backbones (e.g., optical IP) [ TDM-over IP Forum, Geneva ‘99] Relevance    Seamless migration to IP backbones without interruption of legacy services Transparent to the end-user Can be simpler than VoIP solutions Contributions    Definition of the functions Design of the protocol Performance assessment

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications — Application I: Circuit Emulation



Conclusions

16

Applications and synchronization (I): Circuit Emulation over IP – definition of the functions

 Emulation functions are allocated in a

Circuit Emulation adapter

User (e.g., T1/T3 leased lines)

TDM traffic

- Isochronous - Periodic

Circuit Emulation Adapter

• Jitter Removal • Clock recovery • Data structure handling IP Network operator

IP packets

- Asynchronous - Aperiodic IP backbone TDM LT IP

Circuit Emulation

LT IP f

Circuit Emulation Adapter Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications — Application I: Circuit Emulation



Conclusions

17

Applications and synchronization (I): Circuit Emulation over IP – design of the protocol

    Real-Time Protocol has been developed for real-time applications, including VoIP applications [Schulzrinne, ’96] Native features include timestamping and sequencing Includes a control protocol – RTCP Extended features can be added

Timestamping & Sequencing

RTP

RTP-H Payload

UDP

UDP-H RTP-H Payload

IP

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000 IP-H UDP-H RTP-H Payload



Introduction



Theory



Applications — Application I: Circuit Emulation



Conclusions

18

Applications and synchronization (I): Circuit Emulation over IP – design of the protocol

RTP packet V PX M CC PT sequence number timestamp synchronization source (SSRC) id.

Fixed header contributing source (CSRC) id. #1 ...

profile length source clock indication (optional) Payload of Consecutive Data Units RTCP message Other fields d_max structure … number x spacing unused SR extension or APP data Extension header Payload

    Data timing, jitter removal 

timestamp

Clock recovery  Data handling 

source clock indication structure and spacing

Session information  RTCP messages

4 bytes Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications — Application I: Circuit Emulation



Conclusions

19

Applications and synchronization (I): Circuit Emulation over IP – design of the adapter

Circuit Emulation adapter non-idle idle Transmitter part payload Packing Leased line Structure Spacing Timestamps + Source clock indications Master clock Scheduling Timestamp RTP packets Circuit Emulation adapter Receiver part RTP packets Source clock indications Timestamp Scheduling Slave clock (LLR/PLL) Structure Spacing Timestamp Leased line Receiver part payload Transmitter part Packing Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications — Application I: Circuit Emulation



Conclusions

20

Applications and synchronization (I): Circuit Emulation over IP – performance assessment

End-to-end delay and loss rate for:   Best-effort service class Expedited forwarding service class  Guaranteed service Network jitter model: [Bolot, ‘93]

Same nominal convergence time, more stable end-to-end delay with LLR (and more stable bitrate) End-to-end delay for a LLR with N= 1200 and

a

= 0.992

220 Best Effort 200 180 160 140 120 100 80 60 0 Convergence time= 100 s

End-to-end delay for a PLL with K p = 0.05 and K i = .0005

220 200 180 160 140 Convergence time= 100 s 50 Time (s) 100 Exp. Forwarding Guar. Service

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

150 120 100 80 60 0 50 Time (s) 

Introduction



Theory



Applications — Application I: Circuit Emulation



Conclusions

100 Best Effort Exp. Forwarding Guar. Service 150 21

Applications and synchronization (I): Circuit Emulation over IP – performance assessment

Loss rate (log scale) for a LLR with N= 1200 and

a

= 0.992

10 0

Loss rate (log scale) for a PLL with K p = 0.05 and K i = .0005

10 0 10 -1 Guar. Service 10 -1 Guar. Service 10 -2 10 -3 10 -4 0 Exp. Forwarding Best Effort 50 Time (s) 100 150 10 -2 10 -3 10 -4 0 Exp. Forwarding Best Effort 50 Time (s) 100 150

Same nominal convergence time, lower losses with LLR Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications — Application I: Circuit Emulation



Conclusions

22

Outline



Synchronization over packet-switching networks:

 Needs and problems in packet-switching networks 

Theory:

 Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks  Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements 

Applications:

   Circuit Emulation over IP Networks Synchronous ATM Adaptation Layer (AAL) Digital TV over packet-switching networks 

Conclusions

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

23

Applications and synchronization (II) Synchronous AAL

Objective  Tranport of statistically multiplexed Variable Bitrate (VBR) traffic in ATM networks with constant end-to-end delay [AAL-1; AAL-2; AAL-3/4; AAL-5] Relevance  Multimedia applications (Voice over ATM, video distribution) Contributions   Design of the protocol Performance assessment

Application Synch AAL ATM layer

Constant delay Variable delay

Application Synch AAL ATM layer

ATM switch

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

ATM switch 

Introduction



Theory



Applications — Application II: Synchronous AAL



Conclusions

24

Applications and synchronization (II) Synchronous AAL – design of the protocol

Application layer SSCS Synchronous AAL CPCS (AAL-5) Synchronous AAL SDU (AAL-5) CPCS SDU (AAL-5) CPCS PDU TS 4-byte timestamp added by the synchronous AAL (in units of microseconds) Reserved CRC TS Padding Length SAR (AAL-5) ATM layer

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications — Application II: Synchronous AAL



Conclusions

25

Applications and synchronization (II) Synchronous AAL – design of the protocol

Synchronous AAL (transmitter) AAL SDU Synchronous AAL (receiver) AAL SDU Scheduling Transmitter clock Timestamp SSCS AAL-5 CPCS SDU AAL-5 CPCS trailer CPCS SAR ATM cells payload To the ATM network Self-synch LLR/PLL SSCS CPCS SAR Timestamp AAL-5 CPCS SDU From the ATM network Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications — Application II: Synchronous AAL



Conclusions AAL SDU AAL-5 CPCS trailer ATM cells payload

26

10 -1

Applications and synchronization (II) Synchronous AAL – performance assessment

Loss rate and rate discrepancy for:   376-byte AAL SDU 1 Mbps average rate  Erlang jitter distribution Network jitter model:[Parekh, ’93; Singh, ’94; …]

Loss rate (log scale) for a LLR with N= 10000 and

a

= 0.9992

10 -1

Same nominal convergence time, lower loss with LLR during the convergence time Loss rate (log scale) for a PLL with Kp= 0.05 and Ki= 0.00025

Convergence time= 100 s Convergence time= 100 s 10 -2 10 -2 10 -3 10 -3 10 -4 0 50 100 Time (s) 150 200

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

250 10 -4 0 50 100 Time (s) 

Introduction



Theory



Applications — Application II: Synchronous AAL



Conclusions

150 200 27 250

20 15 10 5 0 -5 -10 -15 -20 0

Applications and synchronization (II) Synchronous AAL – performance assessment

Difference between output and input rate per each second of the session (LLR)

Average rate= 1 Mbps Convergence time= 100 s 50 100 Time (s) 150 200 250 20 15 10 5 0 -5 -10 -15 -20 0

Difference between output and input rate per each second of the session (PLL)

50 Average rate= 1 Mbps Convergence time= 100 s 100 Time (s) 150 200 250

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000 Same nominal convergence time, more stable rate with LLR during the convergence time



Introduction



Theory



Applications — Application II: Synchronous AAL



Conclusions

28

Outline



Synchronization over packet-switching networks:

 Needs and problems in packet-switching networks 

Theory:

 Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks  Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements 

Applications:

   Circuit Emulation over IP Networks Synchronous ATM Adaptation Layer (AAL) Digital TV over packet-switching networks 

Conclusions

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

29

Applications and synchronization (III) Digital TV services

Objective  Synchronization of MPEG-2 systems over IP and ATM channels [MPEG 2, ’94; Tryfonas ’99; …] Relevance   Penetration of Digital TV services Network-independence of MPEG codecs The electron beam of TV must be

in-sync

with the video camera Contribution  Performance assessment Stored material (films) Residential user Return channel Receiver/ decoder #1 Live material (TV) Video server  DVB: Video broadcast (cable, terrestrial and sat)  VoD: Video-on-demand (interactive TV)  PPV: Pay-per-view (pre-scheduled TV programs)

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

DVD Distribution network Receiver/ decoder #N 

Introduction



Theory



Applications — Application III: Digital TV services



Conclusions

The decoder must synchronize to the server: - generation of TV signal - audio and video sync 30

Applications and synchronization (III) Digital TV services – standardized protocol

Timestamping for:   Intra- and inter-flow synchronization (DTS or PTS) Clock recovery and synchronization (PCR) Audio Video

Compression

Audio and video part contain Presentation TS referred to a common timebase PTS/DTS Video PTS/DTS Audio

Decompression

PES packetizer

Program clock Mux

Transmitter

Program clock

PCR

Synch LLR/PLL Demux

PES depacketizer Receiver PCR Transport network

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

PCR 

Introduction



Theory



Applications — Application III: Digital TV services



Conclusions

The PC Reference is used to reconstruct the common timebase 31

Applications and synchronization (III) Digital TV services – performance assessment

Frequency reconstruction error of the System Clock   50 ms of network jitter PCRs inserted each 100 ms  20 parts-per-million (tolerance dictated by MPEG-2) Network jitter model: [Andreotti, ’95; Noro, ’99; …]

Same nominal accuracy, faster convergence with LLR

1000

Frequency error (log scale) of the recovered clock with

N

=4000 and

a

=0.99

Convergence time= 70 s 100 10 1 0.1

1000

Frequency error (log scale) of the recovered clock with Kp= 0.002, Ki= 0.000001

Convergence time= 2000 s 100 10 1 0.1

0.01

0.01

4000 1000 2000 Time (s) 3000 4000

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

5000 1000 2000 

Introduction



Theory



Applications — Application III: Digital TV services



Conclusions

3000 Time (s) 5000 32

Conclusions

Addressed problem



How to synchronize fast and efficiently dispersed clocks in the presence of network jitter – satisfy new needs of packet-switching

Contributions



A solution based on LLR – overcomes limitations of conventional PLLs

  

Circuit Emulation over IP – support to legacy TDM leased-lines Synchronous AAL – transport of ATM traffic with constant delay Digital TV over packet-switching – distribution of MPEG-2 streams

Future work



Standardization of Circuit Emulation in the Internet community (RFCs)

 

Synchronization for mobile services Global synchronization for IP networks

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000



Introduction



Theory



Applications



Conclusions

33

Most relevant publications

Patents

1.

''Real-time remote inspection of high resolution images'', European Patent n.EP946919A1, Issued Oct. 1999 2.

R. Noro, J.P. Hubaux and M. Hamdi, ``Clock Synchronization over Data Transmission Networks'', US Patent Application, filed July 1998, in progress 3.

M. Hamdi, R. Noro and J.P. Hubaux, ``Fresh Packet First Scheduling for Voice Traffic in Congested Networks'', US Patent Application, filed July 1998, in progress

Articles

1.

2.

''Circuit Emulation over IP Networks'', Proc. of the IFIP 6th International Workshop on Protocols for High-Speed Networks

, Salem- MA, USA, Aug. 1999

''

Clock Synchronization of MPEG-2 Services over Packet Networks'',

Telecommunication Systems Journal

, Baltzer Science Publisher, Vol. 11, Nos. 1- 2, Mar. 1999,

3.

Seminars

1.

Design of a Circuit Emulation Protocol based on extended functionalities of RTP

, at the TDM over IP Forum, Geneva, Switzerland, Oct. 1999

2.

''Improving Clock Synchronization for MPEG-2 Services over ATM Networks'', Proc. of the 4th Int. Workshop on Interactive Distributed Multimedia Systems

, Darmstadt, Germany, Sep. 1997, pp. 176- 188

Synchronization of Networks and Applications: a Survey

, EPFL-SSC Seminars Series, Lausanne, Switzerland, July 1999

Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12 th 2000

34