Transcript Electrical instability in high-k gate stacks: as

Reliability assessment for new
materials: Generation and activation of
electrical defects in high-k gate stacks
Gennadi Bersuker
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Dielectric degradation: multilayer gate stack
- Defect location: in high-k or IL?
- Defect origin: intrinsic or
process-related?
- Defect generation mechanism:
stress condition-dependent or
‘universal’?
•
Defects in interfacial SiO2
Process-related  High-k-induced:
O-vacancies & Hf impurities
•
Defects in high-k
As-grown: O-vacancies
Stress generated – at high stress biases
Polarons
•
Characterization
Combining electrical and physical
techniques, and modeling
SILC evolution for monitoring breakdown
Gate Current [nA]
Gate Current [A]
20
10
9.4
-7
10
101
SBD
10
500 nA
10-3
9.6
9.8
10.0
-5
-7
10
10-9
65 nA
10.2
3
10-11
TiN/3nm HfO /2.1 nm IL
10
10
2
10
100nA; 500 nA
1 A; 100  A
TiN/3nm HfO2/ 2.1 nm IL
-8
-15
10
-8
1
65 nA
500  A
10-13
2
TiN/
3nm
-8 HfO
2
2/2.1nm SiO2
nFET 1x10 cm
CVS
4.6V
CVS 4.6
V
0
1 mA
10
Time [10 sec]
10
10 mA
-1
Ig [A]
-6
10
100
90
80
70
60
50
40
30
3
10
4
10
0.0
0.5
Gate Voltage [V]
Time [sec]
Stress-induced leakage current reflects on the formation
of percolation path
G.B., IRPS 2007
2
nMOSFET 1x10 cm
1.0
1.5
2.0
Probing SiO2 traps
SILC
Charge Pumping
1.E+03
D Jg/Jg0 @ Vg = 2V
1.E+02
/ tIL ; Vstress
1.E+02
t0.9
TiN/HfO2/IL/p-Si
nMOSFET W/L = 1 / 0.2 m
7nm / 1nm; 4.6V
5 nm / 1nm 4.2V
3nm / 1nm; 4.1V
1.0
1.E+01
0.4
1.E+00
TiN/HfO2/IL/p-Si
nMOSFET W/L = 1 / 0.2 m
-8
A: 2x10
-8
t1.0
2
cm
1.E+01
0.9
1.E+00
tH-K / tIL ; Vstress
7nm/1nm;4.6V
5nm/1nm;4.2V
3nm/1nm;4.1V
0.5
2
A: 2x10 cm
1.E-01
1.E+00
D Nit / Nit0 @ CP frq. 1 KHz
tH-K
1.E-01
1.E+01
1.E+02
Stress time (sec)
1.E+03
1.E+04
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
Stress time (sec)
Since CP probes IL, similar CP and SILC growth rates
for each dielectric stack points to the same
contributing defects in IL
Effect of stress voltage on reliability
assessments
SILC voltage: 4
Vg=0.6V
0.67nm
14
3.5
Vg=1.0V
3
0.84nm
12
1.0nm
2.5
10
1.1nm SiO2/ 3nm HfO2
8
2
Vstress = 2.4 V
1.5
6
4
1
2
0.5
0
0
0
1st1 300s
2nd2
300s
3rd3 300s
4
1.1nm SiO2/3nm HfO2
4KHz
DNit/Nit0
18 N probing distance
it
16 from Si:
High voltage
SILC growth rate RSILC
Nit growth rate Rit X1010 /cm2
Low voltage
2
1MHz
Vstress = 4.1 V
0
0
100 200 300 400 500 600 700
Stress time (s)
4
Stress periods (sec)
• Low voltage: activation of precursor defects in IL
• High voltage: defect generation in IL
High-k–induced O vacancies in SiO2 IL: EELS
40000
35000
Si L2,3-edge EELS
Solid – as-deposited
Dashed – after 1000C
anneal
Si
Si
Y Axis Title
30000
Si/SiO2
25000
SiO2
20000
SiO2
HfO2
15000
10000
SiO2/HfO2
5000
100
110
120
K. van Benthem, Pennycook
Energy-loss [eV]
Higher O deficiency higher density of precursor defects (Si-Si)
 converted by stress into electron traps SiG.B., JAP 2006
Metal/high-k-induced O defects in SiO2: ESR
3nm HfO2/1nm SiO2/TiN+ 1000C PDA
3nm HfO2/1nm SiO2 +1000C PDA
3nm HfO2/1nm SiO2
J. Ryan et al., APL 2007
Metal/high-k process significantly enhances E’
center density in interfacial SiO2 layer
Metal/high-k-induced O defects in SiO2: ESR
SiO2 (20Å) + HfO2 (30Å)/TiN
+ 1000ºC/10s
ESR Amplitude (Arb. Units)
g = 2.0035
g = 2.0005
b
g = 2.0025
a
SiO2 (10Å) +HfO2 (30Å)/TiN
+ 1000ºC/10s
3461
3463
3465
3467
3469
J. Ryan et al.
Magnetic Field (Gauss)
High-k-induced (process-related) generation of E’ centers
is much more effective in thinner SiO2 layers
12
Fast interface trap generation: DCIV
DCIV measurements
High-k
1600
5000
Eo @ 3.4 MV/cm
DDit
2000
1000
DVt
t = 10 s
5s
2s
1s
0s
-0.5
-0.4
-0.3
VG(V)
-0.2
-0.1
800
3.3 nm SiO2
400
0
-0.6
t = 10 s
5s
2s
1s
0s
1200
DIB (pA)
DIB (pA)
4000
3000
[email protected] V
3 nm HfO2
EOT @ 1.2 nm
125 oC, VG = -1.8 V
[email protected] V
SiO2
0
0
-0.1
125 C, VG = -3.2 V
Eo @ 9.7 MV/cm
o
0
0.1
0.2
0.3
VG (V)
Neugroschel, IEDM 2006
High-k devices show strong initial increase of both
trapped charges and interface traps
0.4
0.5
Hf defects in IL: spin dependent recombination
HfO2/SiO2
12
g = 2.0060 ± 0.0003
g = 2.0033 ± 0.0003
Possible E' Center
SDR Amplitude (Arb Scale)
SDR Intensity (Arb. Units)
SiO2
9
6
g = 1.9998
3
0
3430
3440
3450
3460
Magnetic Field (G)
Magnetic Field (G)
3470
3480 3360
3375
3390
3405
Magnetic Field (G)
Magnetic Field (G)
Lenahan, IRW 2006
Fast transient defect generation might be
associated with Hf atoms in interfacial SiO2 layer
3420
3435
Fast degradation: Hf in SiO2 IL
Si
Si
SiO2
Amorphous
layers
HfO2
SiO2
“Regular”
structure
Hf
G.B., JAP 2006
Hf can diffuse through voids in SiO2
S. Rashkeev, INFOS 2005
Long-term instability: defects in SiO2
Threshold voltage
Interface states
1.E+11
11
10
2
DDIT (1/cm -eV)
HF-last + 3 nm HfO2
28 oC, -1.6 V
n @ 0.16
SiO2
High-k
10
1.E+10
10
103
1000
High-k
DDIT - DDIT(1s)
4
10000
10
Stress Time (s)
5
100000
10
Neugroschel, IEDM 2006
Similar degradation rates in high-k stack and control SiO2
 same mechanism
Defect generation in high-k film
Low Vg:
mostly reversible
High Vg:
w/ continues degradation
1.1nm SiO2/ 3 nm HfO2
200 Vstress= 2.4 V
D Vt (V)
DVt (mV)
180
160
140
120
100
80
60
40
20
0
-0.5
1.0
after
afterdischarge
discharge
0.5
1.5
2.5
3.5
4.5
Stress
Stresstime
timex1000
x1000(sec)
(sec)
5.5
0.1
101
after detrapping
before detrapping
Vstress = 5 V
1.1nm SiO2/3nm HfO2
102
103
Stress time (sec)
• Low stress voltage: reversible filling of pre-existing traps
• High voltage: trap generation
Defect generation in high-k:
pulse measurements
Gate
High
-k
V STRESS = 3.5 V
1.1nm SiO2/3nm HfO2
DVth (mV)
Drain Current
100
0.0
10
2
Breakdown
0.5
1.0
1.5
2.0
Gate Voltage [V]
3
10
Stress Time (sec)
Defect generation rate (mV/s)
o
T = 25 C
Pulse time = 300 ns
0.4
0.3
0.2
0.1
0.0
0
500
1000
1500
Stress Time (s)
Defect generation at as-grown defect precursors
2000
Trapping in amorphous high-k
J. Gavartin, ECS 2006
Injected electron can trap via self-localization (polaron
formation)  No defects needed to charge high-k film
Summary
• Interfacial SiO2 layer:
- Low bias stress: trap generation at asprocessed precursor defects (O vacancies/Hf atoms)
induced by high-k dielectric
- High bias stress: new “conventional” defects
• High-k film:
- Low bias stress: instability due to reversible
electron trapping on as-processed defects (Ovacancies) or polaron formation(?)
- High bias stress: defect generation at asprocessed precursors: Defect nature? Mechanism?
Specifics of metal electrode/high-k dielectric
gate stacks
–
–
–
Multi-layer dielectric stacks
Interfacial SiO2, high-k dielectric, metal/high-k interface
Ultra-short characteristic times
Transient charging/discharging (relaxation) effects
High density of pre-existing defects
O vacancies, under-coordinated metal and Si atoms
Question applicability of SiO2 test methodologies
New Materials Reliability Issues
•
Reversible parameter instability – sensitive to
measurement times; can be partially addressed by design
•
Stress-dependent degradation mechanisms test close to use conditions
•
Strong process-dependent characteristics –
reliability assessment requires extensive set of gate stacks of
variety of compositions/processing