Transcript LCLS Timing
LCLS Timing Outline Scope The order of things Introducing the PNET VME receiver Status of the PNET VME receiver System diagram Looking at timing pulse to pulse LCLS MPG EVG Conclusions April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] Scope LCLS timing system is used to transmit a fiducial 360 Hz signal to all triggered devices in LCLS System requirements (speed and content) are known: receive 128 bit PNET data at 360 Hz; append add’l info; operate at 120 Hz The component parts are known: PNET VME receiver, EVG-200 and EVR-200 The interfaces are being defined April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] The order of things The one and only SLC Master Pattern Generator (MPG) Takes as input: 360 Hz fiducial from SLC PDU is the signal to create a new PNET buffer Performs tasks: creates PNET buffers responds to faults Outputs PNET buffers to all micros and PNET VME receiver on the next 1/360 s fiducial April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] Introducing the PNET VME receiver N April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] Status of the VME PNET receiver Hardware prototype is finished (1 instance) Board is 3 slots wide to accommodate on board cable modem interface to PNET Engineering Design Specification doc written Driver and device support (bi, mbbiDirect to access each variable in PNETbuffer) written. Compiled only for Synergy PPC running RTEMS 4.6.2 April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] System Diagram Needs to be added so that LCLS vacuum leak detection shuts off klystron LCLS beam loss monitor (new) PEP beam loss monitor (existing) LCLS power supplies (new) LCLS vacuum (new) Orbit tolerances Laser Turn off/clear Laser status LCLS MPS (new) Kicker Turn on (to drive beam to dump)/clear Kicker status Arrives within 8.3 ms (1-120 Hz beam pulse) Mode of running (eg rate limit) LCLS MPG C P U MPG Arrives within 24.9 ms (3-120 Hz beam pulses) SCP P N E T SLC-AWARE IOC Gated data acquisition application (eg. BPM) SLC-AWARE IOC Gated data acquisition application (eg. BPM) C P U E V G E V R B P M h w C P U E V R PNET Bit pattern of instructions for current beam pulse + fault indicators MKSU MPS Slow control (eg setup commands) Within 1/360 s RF 119 MHz clock with 360 Hz fiducial (existing) LINAC vacuum interlock (existing) April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] B P M h w Looking at timing pulse to pulse Time in milliseconds (the 360 Hz fiducial) 120 Hz signal 0.00 BGRP= PEPII 4 "one second"s worth of PNET buffers is kept in 4 separate arrays PBx = PNETbuffer 'x' is 16 bytes (128 bits); EBx = EVG buffer 'x' is ~24 bytes (192 bits) SLC PDU MPG ISR sends intr3 to MPG - receives intr 3 - reads fault bits from camac - if BCS fault bit asserted, ISR sets BCSFAULT modifier bit in PB2 (created last intr) - sends (modified) PB2 - finds which BGRP to execute - based on fault bits and BGRP var (from operator), find MGRP - execute MGRP which creates PB3 2.78 sends intr4 to MPG - receives intr 4 - updates PB3 if new faults - sends PB3 -creates PB4 BGRP= CRYO 5.56 April 27-29, 2005 EPICS Collaboration Meeting at SLAC Each micro VME PNET receiver LCLS MPG 128 µs + several µs for speed of light travel - is interrupted by the arrival of PB2 - xlate 5-bit base beamcode + modifier bits in PB2 into 8 bit beamcode and set up camac FC F19A10 so that “2/360s early” cmds in PB2 will happen next fiducial - set up camac FC F19A9 so that “1/ 360s early” cmds from PB1 will happen next fiducial - set up camac FC F19A8 so that “on time” cmds from PB0 will execute next fiducial - looks for YY=243. If found, mark current full sec buffer not to be overwritten OR if full, mark next -saves PB2 to current full sec buffer - receives PB2 - does checksum(s) and - if error, appends flag - appends epicsTimeStamp - sets flag that data2 ready receives flag that data2 ready adds additional cmds for new apps ext to SCP appends faults that occurred since PB2 created sets flag that EB2 ready - is interrupted by the arrival of PB3 - xlate 5-bit base beamcode + modifier bits in PB3 into 8 bit beamcode and set up camac FC F19A10 so that “2/360s early” cmds in PB3 will happen next fiducial - set up camac FC F19A9 so that “1/ 360s early” cmds from PB2 will happen next fiducial - set up camac FC F19A8 so that “on time” cmds from PB1 will execute next fiducial - looks for YY=243. If found, mark current full sec buffer not to be overwritten OR if full, mark next -saves PB3 to current full sec buffer - receives PB3 - does checksum(s) and - if error, appends flag - appends epicsTimeStamp - sets flag that data3 ready receives flag that data2 ready adds additional cmds for new apps ext to SCP appends faults that occurred since PB2 created sets flag that EB2 ready Dayle Kotturi [email protected] Looking at timing pulse to pulse Time in milliseconds (the 360 Hz fiducial) 120 Hz signal SLC PDU 5.56 sends intr5 to MPG BGRP= LCLS 8.33 Each micro MPG ISR - receives intr 5 - updates PB4 if new faults - sends PB4 -creates PB5 - is interrupted by the arrival of PB4 - xlate 5-bit base beamcode + modifier bits in PB4 into 8 bit beamcode and set up camac FC F19A10 so that “2/360s early” cmds in PB4 will happen next fiducial - set up camac FC F19A9 so that “1/ 360s early” cmds from PB3 will happen next fiducial - set up camac FC F19A8 so that “on time” cmds from PB2 will execute next fiducial - looks for YY=243. If found, mark current full sec buffer not to be overwritten OR if full, mark next -saves PB4 to current full sec buffer sends intr6 to MPG BGRP= PEPII VME PNET receiver LCLS MPG - receives PB4 - does checksum(s) and - if error, appends flag - appends epicsTimeStamp - sets flag that data4 ready receives flag that data4 ready adds additional cmds for new apps ext to SCP appends faults that occurred since PB4 created sets flag that EB4 ready Pattern repeats ... 11.11 sends intr7 to MPG BGRP= CRYO 13.89 BGRP= LCLS sends intr8 to MPG April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] Looking at timing pulse to pulse Time in milliseconds (the 360 Hz fiducial) 120 Hz signal SLC PDU MPG ISR VME PNET receiver EVG LCLS MPG Each EVR SLCaware IOC 0.00 sends intr3 to MPG - receives intr 3 - reads fault bits from camac - if BCS fault bit asserted, ISR sets BCSFAULT modifier bit in PB2 (created last intr) - sends (modified) PB2 - finds which BGRP to execute - based on fault bits and BGRP var (from operator), find MGRP - execute MGRP which creates PB3 128 µs + several µs for speed of light travel - receives PB2 - does checksum(s) and - if error, appends flag - appends epicsTimeStamp - sets flag that data2 ready receives flag that data2 ready adds additional cmds for new apps ext to SCP appends faults that occurred since PB2 created sets flag that EB2 ready Sees flag that EB2 ready Sends EB2 at 125MHz ... 2.78 Receives EB2 < 1 μs later (50 ns/2 B)*24B + overhead + fiber length travel time Pattern repeats 5.56 8.33 11.11 April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] LCLS MPG Takes the PNETbuffer with appended epicsTimeStamp and checksum fault indicators Adds on LCLS application commands Adds on any newly detected faults Informs EVG that data is ready April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] EVG On board FPGA packages/chunks 24 byte LCLS MPG data and sends to EVR at 125 MHz Data arrives in EVR in 0.6 microseconds + fiber travel time (which depends on distance) April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected] Conclusions LCLS MPG needs to be designed LCLS MPG/EVG interface needs defining EVR/SLC-aware IOC interface needs defining Performance and reliability from PNET through to EVG must be measured But I guess there has been some progress… April 27-29, 2005 EPICS Collaboration Meeting at SLAC Dayle Kotturi [email protected]