Transcript front end electronics for ILC calorimeters (CALICE)

Front-End electronics for
Future Linear Collider
calorimeters
C. de La Taille
IN2P3/LAL Orsay
On behalf of the CALICE collaboration
http::/www.lal.in2p3.fr/technique/se/flc
« Imaging calorimetry » at ILC
©J.C Brient (LLR)
F. Sefkow (DESY)
 Particle flow algorithm
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Reconstruct each particle individually
Bring jet resolution down to 30%/√E
Measure charged particles in tracker
Measure photons in ECAL
Measure hadrons in ECAL and HCAL
Minimize confusion term
 Calorimeter design
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High granularity : typ < 1 cm2
High segmentation : ~30 layers
Moderate energy resolution (10%/√E)
ECAL : Silicon-Tungsten
HCAL : analog vs digital
 CALICE collaboration
« a high granularity calorimeter
optimized for particle flow algorithm
 190 phys./eng., 9 countries, 3 regions
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20 may 2006
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front-end electronics for ILC calorimeters FEE2006 Perugia
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ILC Challenges for electronics
 Requirements for electronics
Large dynamic range (15 bits)
 Auto-trigger on ½ MIP
 On chip zero suppress
 Front-end embedded in detector
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Si pads
Ultra-low power : ( « 100µW/ch
)
Ultra-low
108 channels
 Compactness
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ASIC
 « Tracker electronics with
performance »
ILC : 100µW/ch
20 may 2006
POWER
W layer
is the
KEY issue
calorimetric
FLC_PHY3 18ch 10*10mm 5mW/ch
C. de La Taille
ATLAS LAr FEB 128ch 400*500mm 1 W/ch
front-end electronics for ILC calorimeters FEE2006 Perugia
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CALICE physics prototype(s)
 1 m3 prototype for physics tests
Goal : study particle flow algorithm
 Check modelization of hadronic showers
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 3 calorimeters to go to testbeam
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ECAL : W-Si 24X0 20x20 cm2
AHCAL : Tiles + fibers + SiPMs
DHCAL : RPCs or GEMS
Already 104 to 4 105 channels !
Run at DESY (05), CERN (06), FNAL (07)
20 may 2006
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front-end electronics for ILC calorimeters FEE2006 Perugia
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ECAL W-Si prototype
 ECAL prototype
1 cm2 Si PADS, 550 µm
 1 MIP = 40 000 e 216 channels/slab
 10 000 channels total
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 Readout electronics
FLC_PHY3 ASIC [LAL]
 Calibration ASIC [LAL]
 CRC DAQ boards [UK]
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14 layers, 2.1 mm thick
70 boards made in Korea
20 may 2006
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FLCPHY3 front-end ASIC
 Chip architecture
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©J. Fleury (LAL)
1 channel
18 Channels/chip
Low noise charge preamp optimized for
Cd=70pF. Variable gain (Cf = 0.2 -> 3 pF)
ENC = 1000e- + 40 e-/pF @ tp=200ns
series noise : en = 1.6nV/√Hz @ 600 µA
poor 1/f noise : 25 e-/pF
Dual gain shaper (G1-G10) tp = 200 ns
splits 15bit dynamic range in 2 x 12 bits
Differential shaper and Track&Hold =>
better pedestal stability and dispersion :
pedestal dispersion : 5 mV rms
Multiplexed output : 5 MHz
Amp
OPA
G10
OPA
G1
Synoptic of 1 channel of FLCPHY3
Power dissipation : 6mW/channel
 Technology : AMS 0.8µm BiCMOS
 2000 chips produced in 2003, yield : 86%
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front-end electronics for ILC calorimeters FEE2006 Perugia
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FLC_PHY3 : performance
 Measured on all preamp gains
Cf = 0.2, 0.4, 0.8, 1.6, 3 pF
 Well within ± 0.2 %
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 Dynamic range (G1, Cf=1.6pF)
Max output : 3 V
 linear (0.1%) range : 2.5V
= 500 MIPS @ Cf = 1.6 pF
 Noise :
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• 200 µV (Cd = 0)
• 410 µV (Cd = 68pF)
• = 0.1 MIP @ Cd = 68 pF
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Dynamic range : > 12 bits
• 13 000 (14 bits) @ Cd = 0
• 6500 (12 bits) @ Cd = 68 pF
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Can be extended to 13-14 bits
by using the bi-gain outputs
20 may 2006
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Results with detector
©G. Gayken (LLR)
 Testbeam at DESY (jan 05)
Calorimeter partially equipped
(7 X0, 3000 channels)
 MIP/noise = 8 => clean cut at ½ MIP
 Calibration done with cosmics
 Just now completed to 24X0 !
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2 adjacent 2 GeV electrons
Noise, MIP
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front-end electronics for ILC calorimeters FEE2006 Perugia
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©F. Sefkow (DESY)
AHCAL testbeam prototype
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•
1 cubic metre,
38 layers, 2cm steel plates
8000 tiles with SiPMs
Electronics based on ECAL design
Mechanics and front end boards: DESY
Front end ASICs: LAL
20 may 2006
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front-end electronics for ILC calorimeters
FEE2006 Perugia
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SiPMs for calorimetry
• Multipixel Geiger Mode APDs
ITEP
– Gain 106, bias ~ 50 V, size 1 mm2
– Insensitive to magnetic fields
Auto-calibrating
but non-linear
1156 pixels with
individual quenching
resistor on common
substrate
20 may 2006
3x3 cm scintillator tile
with WLS fibre
MEPHI / PULSAR
C. de La Taille
New era for scintillator–
based detectors:
High granularity at
relatively low cost
front-end electronics for ILC calorimeters
FEE2006 Perugia
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SiPM readout ASIC
©L. Raux (LAL)
 Readout AHCAL (DESY)
One pixel signal © E. Popova
SiPM detector (MEPHI )
 >3000 channels : first large scale use
 G ~ 106 e ~10% HV ~ 50 V
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A, mV
0,0
 FLC_SiPM readout ASIC
18 channel variable gain preamp and shaper
 Dynamic range : 13 bits (2 gains)
 8 bit DAC for SiPM gain adjustment
 1000 chips produced in 2004
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-0,4
-0,8
-1,2
0
20
40
60
80
100
time, ns
Single photoelectron spectrum © E. Popova
8bit DAC
i
n
o
u
t
Variable Gain Charge
Preamplifier
20 may 2006
Variable Shaper CRRC²
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front-end electronics for ILC calorimeters FEE2006 Perugia
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Digital HCAL physics prototype
 GEM based DHCAL
©A. White (U. Arlington)
J. Repond (ANL)
 RPC based DHCAL
Mylar sheet
Resistive paint
1.2mm gas gap
Signal Pad
1.1mm Glass sheet
1.1mm Glass sheet
Resistive paint
Mylar sheet
GND
-HV
Aluminum foil
Charged particles
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DHCAL front-end electronics
©J. Hoff, A. Mekaoui (FNAL)
 DCAL chip
64 inputs with gain choice GEM/RPC
 Triggerless or triggered operation
 Output hit pattern & time stamp
 Prototyped in 0.25µm in march 2005
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front-end electronics for ILC calorimeters FEE2006 Perugia
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DCAL chip performance
 DCAL chip performance
All digital functions operationnal
 Excellent efficiency curves
 Threshold adjustable between 2-8 fC
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 DCAL2 chip
Submission foreseen july 06
 Reduced preamp gain
 Threshold RPC ~ 100 fC
 Threshold GEMS ~10 fC
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Technological prototype : “EUDET module”
 Front-end ASICs embedded in detector
Very high level of integration
 Ultra-low power with pulsed mode
 FLC_TECH1 ASIC prototype in 0.35 µm SiGe
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 All communications via edge
4,000 ch/slab, minimal room, access, power
 small data volume (~ few 100 kbyte/s/slab)
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 « Stitchable motherboards »
Elementary motherboard ‘stitchable’
24*24 cm ~500 ch. ~8 FE ASICS
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front-end electronics for ILC calorimeters FEE2006 Perugia
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EUDET module FEE : main issues
 Mixed signal issues
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Digital activity with sensistive
analog front-end
 Pulsed power issues
Electronics stability
 Thermal effects
 To be tested in beam a.s.a.p.
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 No external components
Reduce PCB thickness to < 800µm
 Internal supplies decoupling
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PCB (600µm)
20 may 2006
C. de La Taille
Tungsten (1 mm)
FE chip (1mm)
Wafer (400µm)
front-end electronics for ILC calorimeters FEE2006 Perugia
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ECAL Front-End ASIC
 Readout integration is the key element of compact detector
Keep small Moliere radius for good shower separation
 Many features have never been used before e.g. power cycling (ON 2ms OFF 200 ms)
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Power
Cycling
Auto-trigger
on ½ MIP
Internal
ADC
20 may 2006
C. de La Taille
front-end electronics for ILC calorimeters FEE2006 Perugia
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Present status on noise & power cycling
 FLC_TECH1 : moving into SiGe 0.35µ
30 µW in pulsed mode
 ENC = 1000 e- @ Cd=27pF (MIP=40 000e-)  NOISE WELL BELOW MIP
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First demonstration of power cycling : Target power of 100 µW/channel appears
within reach : to be validated in testbeam in 2006 with FLC PHY4 ASIC
POWER CYCLING MEASUREMENT
NOISE MEASUREMENT
Detector capacitance
R FC F
signal
ON
20 µs
Ready for pulse
Autotrigger
20 may 2006
C. de La Taille
front-end electronics for ILC calorimeters FEE2006 Perugia
FLC shaping
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EUDET ECAL ASIC
 72 channels
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Scales with the 4 factor reduction in pad size and is compatible with physics
prototype
 Detector DC coupling
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Prepares the case the on-detector MMIC HV capacitance is not affordable
Provides leakage current monitoring, up to 1 µA/Ch
 Auto-trigger
If one channel is hit during a bunch crossing, then the whole chip is recorded
with a time tag (BCID)
 The auto trigger activates the T&H
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 Analogue pipeline, ADC & digital registers
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8-depth analog pipeline to store « in bunch » events
Wilkinson 12 bit 100MHz ADC
On chip storage, inter-bunch data outputting
 Digital data output
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Daisy chained with redundancy : one output for 40 ASICs
Common architecture for ECAL and HCAL
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Front-end
 Derived from existing FLC_PHY4 chip
SW0
Cf0
SW1
Cf1
SW2
Cf2
SW3
Cf3
INPUT
SCA
Vref_ss
op. amp.
+
Gain 1
Vref_ss
T rack&Hold
op. amp.
+
Gain 10
T rack&Hold
T o Gain 1 MUX
Amplifier
SCA
Rf
T o Gain 10 MUX
CALIBRAT ION
Bipolar Fast shaper
Vref_fs
To ADC – leakage
current meas.
Trigger
Timewalk-free
Threshold
Monostable
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front-end electronics for ILC calorimeters FEE2006 Perugia
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ADC
©G. Bohner (LPCC)
 Wilkinson architecture, developped by Clermont group
 100 MHz clock frequency : 4 µs digitization time for 12 bits
Channel 0
Register 0
Channel 1
Channel 71
Register 71
Ramp
generator
20 may 2006
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Gray
counter
front-end electronics for ILC calorimeters FEE2006 Perugia
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Digital part
 Store all channels and BCID for every hit. Depth ~8 bits
 Event size : 8(depth)*[16bit*72ch+16bit(bcid)] = 9344 bits
 Sequential readout : 9344*10ns = 100 µs : LVDS level
OR
Discri
CH 0
Register 16bits
Discri
CH 71
Register 16bits
16 bit counter
BCID
20 may 2006
C. de La Taille
Register 16*16 bit
BCID
front-end electronics for ILC calorimeters FEE2006 Perugia
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EUDET ECAL ASIC
 Will be submitted in AMS 0.35µm SiGe in sept 06
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Area : 3 x 7 mm
Control signals and power supplies
36
inputs
36
Analog
Channels
+ ADC
Digital
memory
and
controls
36
Analog
Channels
+ ADC
36
inputs
Control signals and power supplies
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C. de La Taille
front-end electronics for ILC calorimeters FEE2006 Perugia
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EUDET DHCAL RPC ASIC
 Move towards ILC specs
Power pulsing
 Data internally saved during bunch train
 Data transferred to DAQ during inter-bunch
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 Chip based on MAROC will be submitted in sep 06
T hreshold 0
Channel 1
T hreshold 1
Channel 2
T hreshold 2
Channel 3
T hreshold 3
Channel 62
T hreshold 62
Channel 63
T hreshold 63
Bunch crossing ID
20 may 2006
C. de La Taille
front-end electronics for ILC calorimeters FEE2006 Perugia
Digital memory
[64bits (data) + 12 bits (BCID)]*depht
Channel 0
memory write
>
analogue front-end
Data out
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MAROC : 64 ch MAPMT chip for ATLAS lumi
©N. Seguin (LAL)
 Characteristics
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Hold signal
64 PMT channels input (50-100 Ω)
Variable gain current conveyor (0-2)
Multiplexed
Variable
S&H
charge output
6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16
Slow
Shaper
64 discriminator outputs (GTL)
64 PM
Variab
inputs
100% sensitivity to 1/3 photoelectron
le
Bipolar
Gain
(50fC). Counting rate up to 2 MHz
Fast Shaper
Pream
p.
Common threshold loaded by internal
64Trigger
outputs
10 bit DAC
10bit DAC
1 multiplexed charge output with variable
discriminator
Gain correction
shaping 20-200ns and Track & Hold.
threshold
6 bits/channel
10 bits DAC
Dynamic range : 11 bits (2fC - 5 pC)
Crosstalk < 1%
Synoptic diagramm of MAROC1
 Technology : AMS SiGe 0.35µm
Submitted 13 june 05 Area 12 mm2
 Dissipation 130 mW @ VDD=3.5V
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 Can be accomodated to DHCAL
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Adding power pulsing and digital readout
20 may 2006
C. de La Taille
front-end electronics for ILC calorimeters FEE2006 Perugia
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« super common base » Preamplifier
 Current conveyor
« Super common-base » configuration
 Low input impedance : 50 – 100 Ω
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• Rin = 1/gm1gm2RC=VT2/IC1IC2RC + 50 Ω protection
• Can be varied by adjusting IC1
• Low “Inductive term”(50 nH) with careful dimensioning
Large output impedance : ~500 kΩ
 Unity current gain
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Iout
Rc
Q2
Iin
20 may 2006
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front-end electronics for ILC calorimeters FEE2006 Perugia
Q1
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MAROC Efficiency curves
20 may 2006
C. de La Taille
front-end electronics for ILC calorimeters FEE2006 Perugia
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Prospective for A-HCAL SiPM Chip
 Similar developments for AHCAL
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Chip fully dedicated to SiPMs developped after ECAL chip
Internal DAC for SiPM gain adjustment (5V range)
Auto-trigger (fast shaper + Discriminator)
Internal TDC, 1 ns step
Internal 12 bit ADC
Power pulsing
T&H Analogue
Memory
8 bit DAC
(0-5V)
Charge
Ouput
…
Shaper tp~30-40ns
12-bit
ADC
x1
Auto-trigger
in
Variable gain
Preamplifier
Capacitance
for AC
coupling
20 may 2006
C. de La Taille
TDC
Fast Shaper
Threshold
Discri
12-bit DAC
front-end electronics for ILC calorimeters FEE2006 Perugia
Time
Ouput
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Conclusion
 Several large dynamic range ASICs
developped for CALICE physics prototypes
ECAL W-Si calorimeter : FLC_PHY3 = 104
channels in beam, dynamic range 0.1-600 MIPS
 AHCAL Tile-SiPM calorimeter : FLC_SiPM =
103 channels installed, beam in summer 06
 DHCAL GEM/RPC
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 ASICs for technological prototypes now in
development
Power pulsing
 Zero-suppress
 Auto-trigger
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 System aspects not to be forgotten
Power supplies !
 Mechanics
 Reliability…
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20 may 2006
C. de La Taille
front-end electronics for ILC calorimeters FEE2006 Perugia
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Backup slides
20 may 2006
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front-end electronics for ILC calorimeters FEE2006 Perugia
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SLAC-Oregon-UC Davis-BNL
Si-W ECal R&D
David Strom
Effective 4 x 4 mm2
20 may 2006
C. de La Taille
front-end electronics for ILC calorimeters FEE2006 Perugia
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SLAC-Oregon-UC Davis-BNL
Si-W ECal R&D
M.Breidenbach
Si-W Pixel Analog Section
1 of 1024 pixels
Low Gain
Wilkinson
scaler and
logic
Range Logic
Reset
KPix Cell 1 of 1024
Latch (4x)
Range Register
Reset
High Gain (default)
I
Source
Range Threshold
Track
Analog 1
Control Logic
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Pulses to Timing Latch,
Range Latch, and Event
Counter
Leakage Current Servo
Event Threshold
Reset
Analog 4
Track
Bunch Clock
Cal Dac
Cal Strobe
Metallization on detector from KPix
to cable
Simplified Timing:
Bump Bonds
There are ~ 3000 bunches separated by ~300 ns in a train, and trains are separated by ~200 ms.
Say a signal above event threshold happens at bunch n and time T0.
The Event discriminator triggers in ~100 ns and removes resets and strobes the Timing Latch (12 bit), range latch (1 bit) and Event Counter (5 bits).
The Range discriminator triggers in ~100 ns if the signal exceeds the Range Threshold.
When the glitch from the Range switch has had time to settle, Track connects the sample capacitor to the amplifier output. (~150 ns)
The Track signal opens the switch isolating the sample capacitor at T0 + 1 micro s. At this time, the amplitude of the signal at T0 is held on the Sample Capacitor .
Reset is asserted (synched to the bunch clock) . Note that the second capacitor is reset at startup and following an event, while the high gain (small) capacitor is reset each bunch crossing (except
while processing an event)
The system is ready for another signal in ~1.2 microsec.
After the bunch train, the capacitor charge is measured by a Wilkinson converter.
Tungsten
Thermal conduction adhesive
Kapton Data Cable
KPix
Si Detector
Kapton
Tungsten
20 may 2006
Heat
Flow
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front-end electronics for ILC calorimeters FEE2006 Perugia
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FLC_TECH1 : noise performance
 FLC_PHY3 : 0.8µm
 FLC_TECH1 : 0.35µm
Series : en = 1.6nV/√Hz
 CPA = 10pF + 15pF test board
 1/f noise : 25e-/pF
 Parallel : in = 40 fA/√Hz
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Series : en = 1.4 nV/√Hz
 CPA = 7 pF
 1/f noise : 12 e-/pF
 Parallel : in = 40 fA/√Hz
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 Target noise of ENC < MIP/10 =
4000 e- is (more than) achieved
Detector capacitance
ENC vs shaping time FLC_PHY3 0.8µ
20 may 2006
C. de La Taille
Autotrigger
FLC shaping
ENC
vs shaping
time
FLC_TECH1
front-end electronics for ILC
calorimeters
FEE2006
Perugia
0.35µ
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EUDET : ECAL emodule
 Electromagnetic calorimeter
Prototype of a (~ 1/6) module 0 :
one line & one column
 150 cm long, 12 cm wide 30 layers
 1800 + 10800 channels
 Test full scale mechanics + PCB
 Can go in test beam
 Test full integration + edge
communications
 Similar in #channels as physics
prototype

©M. Anduze (LLR)
Digital part
 Store all channels and BCID for every hit. Depth ~16 bits
 Data format : 16(depth)*[1bit*128ch+16bit(bcid)] = 2 kbits
 Sequential readout @ 100 MHz : 2000 * 10 ns = 20 µs
OR
Discri
CH 0
Register 16bits
Discri
CH 127
Register 16bits
16 bit counter
BCID
20 may 2006
C. de La Taille
More
probably
a RAM
Register 16*16 bit
BCID
front-end electronics for ILC calorimeters FEE2006 Perugia
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FLCPHY4
 Integrating 12 bit ADC [collab LPNHE Paris] and full power cycling
Ch.1
1
10
Ch.2
Power
Cycling
Multiplexing Gain 10
Submitted in july 05, to be validated in testbeam 06 at CERN
Multiplexing Gain 1

Ch.18
12 bit ADC ( AMS IP)
Digital Output
Idle
20 may 2006
Digital
Output
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HCAL architecture
To DAQ
Module data
concentrator
38 layers
80000 tiles
Typical layer
2m2
2000 tiles
Layer data
Concentrator
(control, clock
and read FEE)
FEE:
32 ASICs
(64-fold)
4 readout
lines / layer
EUDET: Mechanical structure,
electronics integration:
DESY and Hamburg U
20 may 2006
Instrument one tower (e.m. shower size)
+ 1 layer (few 1000 tiles)
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front-end electronics for ILC calorimeters
FEE2006 Perugia
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Towards module0 ASIC : FLC_TECH
 What is missing in FLC_PHY3 :
Dynamic range
<1000 MIPS
No Power
Cycling
1 channel
Amp
No Auto-trigger
on ½ MIP
20 may 2006
C. de La Taille
OPA
MUX out Gain=10
OPA
MUX out Gain=1
No Internal
ADC
front-end electronics for ILC calorimeters FEE2006 Perugia
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Signal uniformity (G1)
 Signal (Gain 1, Cf=1.6pF)

Amplitude = 696 mV/pC ± 18 mV
= 4.66 mV/ MIP ± 2.5% rms
Peaking time = 189 ns ± 2 ns rms
 Pedestals = -3.7 V ± 4.8 mV rms
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 Noise
Cd = 0 pF : Vn = 200 µV
 Cd = 68pF : Vn = 410 µV
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 Crosstalk : < 0.1%
Pedestal uniformity
20 may 2006
C. de La Taille
Gain 1 uniformity vs channel number
Peaking time uniformity
front-end electronics for ILC calorimeters FEE2006 Perugia
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Signal uniformity (G10)
 Signal (Gain 10, Cf=1.6pF)
Amplitude = 6294 mV/pC ± 188
 Peaking time = 174 ns ± 2 ns
 Pedestals = -3.74 V ± 8.3 mV rms
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 Noise
Cd = 0 pF : Vn = 500 µV
 Cd = 68pF : Vn = 1.6 mV
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 Crosstalk

Gain 10 uniformity vs channel number
< 0.2%
Pedestal uniformity
20 may 2006
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Peaking time uniformity
front-end electronics for ILC calorimeters FEE2006 Perugia
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More Results…
<T50> as function
of input charge
c) Linearity with injected charge
d) Tests of pipeline
e) Measurements of noise rate
f) Tests of time stamp counter
Error bars =
RMS of distributions
All successful!!!
2nd Iteration of ASIC Prototype
- Decrease of input sensitivity by x 100
Nice linear dependence!
Currently upper threshold corresponds to 7.6 fC
Smallest RPC signals ~ 100 fC
Noise from digital lines ~ 20 fC (preliminary)
- Decouple of output clock and chip clock
- Submission on July 22nd (highest priority of FNAL design group)
Redesign will start in late May
Will 2006
be used in slice test of Digital Hadron
with RPCs (January 2007 at MT6)
20-may
C. de LaCalorimeter
Taille front-end
electronics for ILC calorimeters
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