Modern Floorplanning Based on B*
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Transcript Modern Floorplanning Based on B*
© KLMH
Modern Floorplanning Based on B*-Tree
and Fast Simulated Annealing
Presented by: Jie Zou
University of Michigan
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
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Fall 2011
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Introduction
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Tung-Chieh Chen, Yao-Wen Chang, IEEE Transactions on computer-aided design of
integrated circuits and systems, Vol. 25, No. 4, April 2006
VLSI floorplanning incurs more sophisticated constraints with the die outline,
interconnect planning and block positions
Modern floorplanning is fixed-outline floorplanning
Two types of problems are studied
Fixed-outline floorplanning
Bus-driven floorplanning
Two types of methodology are used
Fixed-Outline
Bus-driven
B*-Tree to represent block positions
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
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Fast SA as the floorplanning algorithm
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
B*-Tree Representation
Ordered binary tree
Root represents the block on the left-bottom corner
Left child of the node ni represents the lowest unvisited block that belongs to
the set of blocks located on the right-hand side and adjacent to bi
xj = xi + wi
Right child of the node ni represents the lowest block located above and with its
x-coordinate equal to that of bi
xj = xi
n0
b2
b5
b3
b0
b1
VLSI Physical Design: From Graph Partitioning to Timing Closure
n2
n1
b7
n3
b4
n4
n5
n6
n7
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b6
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Fast SA
Motivation: To reduce the uphill moves in the beginning steps
Method: Resort to greedy algorithm to find the local optimal faster
Stages Decomposition
1. High-temperature random search stage
2. Pseudogreedy local-search stage
3. Hill-climbing search stage
Temperature updating function
n: number of iterations
∆avg: average uphill cost
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
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∆cost<1 since cost function is normalized
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Fast SA
Boltzmann acceptance criterion:
currsol : current solution
nextsol: new solution after perturbation
T: current temperature
r: random number between[0,1) from normal distr.
Cost Function:
A: current area
W: current wirelength
Anorm: average area
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
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Wnorm: average wirelength
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Fixed-Outline Floorplanning
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2
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0.79*1.26 = 0.9954
VLSI Physical Design: From Graph Partitioning to Timing Closure
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1.02*0.86=0.8772
Chapter 3: Chip Planning
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© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Pseudocode
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
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Input: A set of blocks and a fixed outline
Output: A floorplan within the outline
Mark all non-rotatable blocks and set their orientations;
Initialize a B*-tree with input blocks;
// Start the adaptive Fast-SA process;
T = T0
// initialization
do
Perturb the B*Tree;
Pack macro blocks;
Evaluate the B*-tree cost;
Decide if we should accept the new B*-tree;
Modify the weights in the cost function;
Update T;
until converged or cooling down;
return the best solution;
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Input: A set of blocks and a fixed outline
Output: A floorplan within the outline
Mark all non-rotatable blocks and set their orientations;
Initialize a B*-tree with input blocks;
// Start the adaptive Fast-SA process;
T = T0
// initialization
i=0
curr_sol = init_sol
curr_cost = COST(curr_sol)
while (T > Tmin)
while (stopping criterion is not met)
i=i+1
(ai,bi) = SELECT_PAIR(curr_sol)
// perturb the B*tree
trial_sol = TRY_MOVE(ai,bi)
// try small local change
trial_cost = COST(trial_sol)
cost = trial_cost – curr_cost
if (cost < 0)
// if there is improvement,
curr_cost = trial_cost
// update the cost and
curr_sol = MOVE(ai,bi)
// execute the move
else
r = RANDOM(0,1)
// random number [0,1]
if (r < e –Δcost/T)
// if it meets threshold,
curr_cost = trial_cost
// update the cost and
curr_sol = MOVE(ai,bi)
// execute the move
T = αDesign:
∙ T From
Update
T
// 0 < α <Chapter
1, T 3:reduction
VLSI Physical
Graph Partitioning
to Timing Closure
Chip Planning
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Bus-Driven Floorplanning
(BDF)
Problem statements
n rectangular macro blocks B = {bi|i = 1, . . . , n} & m buses U = {ui|i = 1, . . . , m}
each bus ui has a width ti and goes through a set of blocks Bi, Bi ⊆ B and |Bi| = ki
no overlap between any two blocks or between any two horizontal (vertical) buses
bus ui goes through all of its ki blocks
the chip area and the bus area are minimized
Characteristics of buses
assigned on the top two metal layers
connect multiple blocks
either vertically or horizontally oriented
alignment constraint
blocks don’t need to be adjacent when connected by buses
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© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Bus constraints – alignment
Dummy blocks to ensure feasibility of horizontal buses
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Bus-Driven Floorplanning
(BDF)
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
In a B*-tree, the nodes in the right-skewed subtree can guarantee
the feasibility of a vertical bus
Bus Overlapping
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Bus-Driven Floorplanning
(BDF)
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Fixed I/O ports define fixed orientation of buses connected to the ports
Twisted buses
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
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Bus-Driven Floorplanning
(BDF)
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
13
Lienig
Bus-Driven Floorplanning
(BDF)
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Pseudocode
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
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Input: A set of blocks and a set of bus constraints
Output: A floorplan satisfying bus constraints with minimized chip area and total bus
area
Initialize a B*-tree with input blocks;
// Perform the Fast-SA process;
T = T0
// initialization
do
Perturb the B*Tree;
Pack macro blocks without dummy blocks;
if there exists a “twisted-bus structure” in the B*-tree;
then restart the do-loop;
Adjust the heights of the dummy blocks to fix horizontal bus constraints and fix busoverlapping;
Pack macro blocks with dummy blocks;
Decide bus locations;
Evaluate the floorplan cost;
Decide if we should accept the new B*-tree;
Update T;
until converged or cooling down;
return the best solution;
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Application -- Parquet
Authors: Saurabh Adya, Hayward H. Chan, Igor Markov.
Latest version: PARQUET-4.5
Homepage: http://vlsicad.eecs.umich.edu/BK/parquet
Descriptions
free open-source software for fixed-outline floorplanning
based on Simulated Annealing
can also be applied to classical outline-free min-area block packing
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
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internal floorplan representation alternates between sequence pairs and B*-Trees
© KLMH
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing
Q&A
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3: Chip Planning
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Thank You !