Transcript Example: Traveling Salesman Problem (TSP)

Modern Floorplanning Based on
Fast Simulated Annealing
Tung-Chieh Chen* and Yao-Wen Chang*#
Graduate Institute of Electronics Engineering*
Department of Electrical Engineering#
National Taiwan University, Taipei, Taiwan
April 5, 2005
1
Outline
․Introduction
․Fast simulated annealing scheme
․Fixed-outline floorplanning
․Bus-driven floorplanning
․Conclusion
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Outline
․Introduction
․Fast simulated annealing scheme
․Fixed-outline floorplanning
․Bus-driven floorplanning
․Conclusion
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Introduction
․Popular modern floorplanning constraints


Fixed-die (fixed-outline) constraint
Block positions and interconnect constraints
․Two types of modern floorplanning problems


Fixed-outline floorplanning (FOF)
Bus-driven floorplanning (BDF)

Need to consider the interconnect and block positions
simultaneously.
․Our floorplanner is based on


the B*-tree floorplan representation and
a fast three-stage simulated annealing scheme,
called Fast-SA.
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Previous Work
․Fixed-outline floorplanning (FOF)

Adya et al. (ICCD 2001) -- Parquet


Lin et al. (ASPDAC 2004) -- GFA


Present new moves to guide local search.
Use evolutionary search.
However, both success rates are not high enough
when whitespace is small.
․Bus-driven floorplanning (BDF)

Rafiq et al. (ISPD 2002, ISCAS 2002)



The bus is composed of wires connecting only two blocks.
Not general for real bus designs.
Xiang et al. (ICCAD 2004)


General BDF allows a bus to connect multiple blocks.
Use the sequences pair (SP) representation.
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Our Contribution
․ Propose a fast three-stage simulated annealing
scheme (Fast-SA).
․ For the fixed-outline floorplanning (FOF)


Propose a new objective function and an adaptive
Fast-SA.
Obtain much higher success rates.
․ For the bus-driven floorplanning (BDF)


Explore the feasibility conditions of the B*-tree with
the bus constraints.
Reduce 20% (50%) dead space on average for the
floorplanning with hard (soft) blocks, compared
with the most recent work by Xiang et al.
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B*-Tree Floorplan Representation
․ Chang et al., “B*-tree: A new representation for nonslicing floorplans,” DAC-2k.



Given a B*-tree, the legal floorplan can be obtained in
amortized linear time.
Left child: the lowest, adjacent block on the right (xj = xi + wi).
Right child: the first block above, with the same x-coordinate
(xj = xi).
b5
b1
x1 = x0
b2
n0
b6
b3
b0
b4
b9
w0
n2
n9
b8
x7 = x0 + w0
A compacted floorplan
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n1
n8
b7
(x0, y0)
n7
n3
n5
n6
n4
The corresponding B*-tree
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Outline
․Introduction
․Fast simulated annealing scheme
․Fixed-outline floorplanning
․Bus-driven floorplanning
․Conclusion
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Simulated Annealing (SA) Using B*-trees
Start
․Non-zero probability for up-hill
climbing: p = min{1, e-ΔC/T}
․Perturbations
(neighboring solutions)




Initialize B*-tree
and Temperature
Perturb B*-tree
Op1: Rotate a block.
Op2: Move a node/block to
another place.
Op3: Swap two nodes/blocks.
Op4: Resize a soft block.
Better
solution?
Y
Keep new
B*-tree
․The cost function is based
on problem requirements.
(fixed-outline constraint,
bus constraint, etc.)
N
Should we
accept?
N
Y
Recover last
B*-tree
Update
Temperature
N
Cooling/Good
enough?
Y
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End
9
Simulated Annealing Schedule
․ Classical annealing schedule

Classical temperature updating function, λ is set to
a fixed value (0.85 as recommended by most
previous work)
Tnew = λTold,
0 < λ< 1
․ TimberWolf annealing schedule (Sechen and
Sangiovanni-Vincentelli, DAC-86)

Increase λ gradually from its lowest value (0.8) to
its highest value (approximately 0.95) and then
gradually decreases λ back to its lowest value.
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Fast Simulated Annealing (1/2)
․Reduce the number of “up-hill” moves in the beginning
․Consists of three stages
The high-temperature
random search stage
The pseudo-greedy local
search stage
The hill-climbing search
stage



Cost
S
local optima
global optimum
State (Solution space)
․Comparisons for the temperature vs. search time:
Classical SA
TimberWolf SA
Temperature
I
(b)
Probability for up-hill
climbing:
p = min{1, e-ΔC/T}
III
II
Time
Time
(a)
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Fast-SA
Time
(c)
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Fast Simulated Annealing (2/2)
․Temperature update
 avg
 ln P

T 
Tn   1 cost
 nc
 T1  cost
 n
n 1
Tn
avg
2nk
P
nk
cost
k,c
The temperature for nth iteration
Average uphill cost
Initial acceptance rate
Average cost change since the SA
started
User-specified constants
․If cost is large, the temperature decreases slowly.
․If cost is small, the temperature decreases quickly.
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Convergence and Stability for Fast-SA
27
Area
Classical SA
26
27
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
27
40
Area
26
25
24
23
80
120
Runtime (sec)
160
0
200
Fast-SA, k = 1
27
Fast SA
(no greedy
local search)
26
21
20
20
19
19
18
18
17
17
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160
160
200
200
․ Ran the circuit n100
for 10 times.
Fast-SA, k = 7
․ Fast-SA has better
Fast SA
convergence speed
than TimberWolf SA
and classical SA.
23
21
80
120
Runtime (sec)
Area
80
120
Runtime (sec)
TimberWolf SA
Fast-SA, k=1 (no
greedy local search)
Fast-SA, k=7
24
22
40
40
25
22
0
․ Classical SA
TimberWolf SA
25
24
0
TimberWolf SA
26
Classical SA
25
Area
0
40
80
120
Runtime (sec)
160
200
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Outline
․Introduction
․Fast simulated annealing scheme
․Fixed-outline floorplanning
․Bus-driven floorplanning
․Conclusion
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Fixed-Outline Constraints
․Two user-specified parameters:


Γ: maximum white-space fraction, and
R*: desired aspect ratio (height/width)
․The outline (height H* and width W*) is defined by:
H*  (1 ) AR*
W*  (1 ) A / R *
․Use the same formulation as Adya et al. (ICCD-2001).
H*
R*=1
R*=2 H*
Γ=0.15
Γ=0.50
W*
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W*
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Cost Function for Fixed-Outline Floorplanning
․Cost for a floorplan F
( F )  A  W  (1     )(R * R)2
Chip area
Wirelength
A

W

R*
R
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Aspect ratio penalty
Chip area
Area weight
Wirelength
Wirelength weight
Desired aspect ratio
Current floorplan aspect ratio
16
Adaptive Simulated Annealing
․Best aspect ratio of the floorplan in the fixed outline is
not the same as that of the outline.
․Shall decrease the weight of aspect ratio penalty to
concentrate on the floorplan wirelenth/area
optimization.


An adaptive method to control the weights in the cost
function is used according to n most recent floorplans
found.
The more feasible floorplans, the less aspect ratio penalty.
(a)
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Decrease aspect (b)
ratio penalty
17
Exp: Fixed-Outline Floorplanning (1/2)
․Success rate vs. aspect ratio on circuit n100
100
Success rate (%)
100
Success rate (%)
80
60
Parquet-2
40
Ours
Γ=15%
20
GFA
1.5
2
2.5
3
Aspect Ratio
Γ=10%
60
40
20
0
0
1
80
Parquet-2
Ours
GFA
3.5
4
1
1.5
2
2.5
3
Aspect Ratio
3.5
n100, Γ=10%
Parquet-2: SP
(TVLSI-2003)
GFA: NPE
(ASPDAC-2004)
Ours:
B*-tree
Avg. success rate
16.6%
30.3%
99.7%
Avg. dead space
7.32%
6.26%
5.79%
Avg. dead space ratio
1.26
1.08
1.00
Avg. runtime (sec)
40.2
44.5
27.6
Avg. runtime ratio
1.46
1.61
1.00
․On a Pentium 4 1.6GHz PC
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Exp: Fixed-Outline Floorplanning (2/2)
․Wirelength optimization under the fixed-outline constraint.
․Obtain 20% less wirelength on average, reduce 55%
runtime on average, compared to Parquet.
Circuit
Aspect
Ratio R*
1
2
ami33
3
4
Average
1
2
ami49
3
4
Average
Comparison
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․OnUniversity
a Pentium 4 1.6GHz PC
Parquet-2.1: SP
Ours: B*-tree
Wire (mm) Time (sec) Wire (mm) Time (sec)
64.6
23
46.3
16
65.9
24
48.9
11
80.9
23
67.7
15
72.7
24
61.4
14
71.0
24
56.1
14
753
25
752
17
792
25
739
18
964
25
858
18
989
25
787
20
875
25
784
18
1.20
1.55
1.00
1.00
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Fixed-Outline Floorplanning Results
Circuit: ami49
Circuit: n100
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Outline
․Introduction
․Fast simulated annealing scheme
․Fixed-outline floorplanning
․Bus-driven floorplanning (BDF)
․Conclusion
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BDF Problem Formulation
․Given n rectangular macro blocks B = { bi | i = 1, …, n }
and m buses U = { ui | i = 1, …, m }, each bus ui has a
width ti and goes through a set of blocks Bi.



Decide the positions of macro blocks and buses, and bus ui
goes through all of its blocks.
Minimize the chip/bus area.
No overlap between any two blocks or between any two
horizontal (vertical) buses.
• A feasible horizontal bus
u = < H, t, { A, B, C } >.
• ymax = yc + hc
• ymin = yb
• ymax - ymin ≥ t
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B*-trees Properties for Bus Constraints (1/4)
․ Left child

The lowest, adjacent block on the right (xj = xi + wi)
Property 1: In a B*-tree, the nodes in a left-skewed subtree may satisfy a horizontal bus constraint.
b5
b1
b2
n0
b6
b3
b0
b4
b9
n1
n8
n2
n9
b8
b7
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n7
n3
n5
n6
n4
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B*-trees Properties for Bus Constraints (2/4)
Property 2: Inserting dummy blocks of appropriate
heights, we can guarantee a horizontal bus with blocks
whose corresponding B*-tree nodes are in a leftskewed sub-tree
y
b3
b3
b1
b2
b1
b4
x
(a)
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b4
D4
b2
D2
dummy blocks x
(b)
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B*-trees Properties for Bus Constraints (3/4)
․ The height of the dummy block Di:
․ An example of inserting dummy blocks to satisfy a
horizontal bus.
n0
n1
y
n2
n3
n4
D5
D6
n5
n6
b2
b0
(a)
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b3
b5
b4
D5
b1
b6
D6
x
(b)
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B*-trees Properties for Bus Constraints (4/4)
․ Right child

The first block above, with the same x-coordinate (xj = xi).
Property 3: In a B*-tree, the nodes in a right-skewed
sub-tree can guarantee the feasibility of a vertical bus.
y
n0
b5
b4
n3
n1
b3
n4
n2
b2
n5
(a)
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b0
b1
x
(b)
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Infeasible Twisted-Bus Structure
․Consider two buses simultaneously, we cannot always
fix the horizontal bus constraint by inserting dummy
blocks.
․Should discard such a tree configuration.
y
n0
n1
n2
n5
n4
n3
n6
b4
b5
b0
(a)
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b6
b3
b2
b1
u1 = {b0, b3}
u2 = {b2, b6}
x
(b)
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Bus-Overlapping
․Use dummy blocks to avoid bus-overlapping while
considering multiple buses.
y
n0
n1
b3
n2
b4
n3
b0
n4
b2
b1
(a)
(b)
n0
y
n1
D2
b3
n3
n2
n4
(c)
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u1 = {b0, b4}
u2 = {b2, b3}
b0
b4
b1
(d)
b2
u1 = {b0, b4}
u2 = {b2, b3}
D2
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Our BDF Algorithm (1/2)
․Use simulated annealing to search for a desired
solution.
 Cost of a floorplan F, buses U:
( F ,U )  A  B  M
A
B
M
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chip area
bus area
number of unassigned buses
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Our BDF Algorithm (2/2)
Initialize floorplan
Perturb and pack
“Twisted-bus structure” exists?
no
Simulated
annealing
iterations
yes
Adjust heights of dummy blocks
Pack and decide bus location
Compute floorplan cost (quality)
Cooling down
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Report the best floorplan
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Soft Macro Block Adjustment
․Key: Line up with adjacent blocks
Each soft block has four candidates for the block
dimensions.
․Advantage: fast and reasonably effective
․Similar idea by Chi et al., Chung Yuan Journal, 2003.

y
y
T3
b5
b4
B3
R3
b3
b0
b1
(a)
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b5
b4
b0
b2
L3
b3
x
R3
b1
b2
x
(b)
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Exp: Bus-Driven Floorplanning
․ MCNC benchmark on Pentium 4 2.8GHz. Obtain 20% (55%) less
dead space on average for hard (soft) macro blocks.
Block type
Hard Macro Blocks
Soft Macro Blocks
SP: Xiang et al.
(ICCAD 2003)
B*-tree: Ours
SP: Xiang et al.
(ICCAD 2003)
B*-tree: Ours
Time
(sec)
Dead
space
Time
(sec)
Dead
space
Time
(sec)
Dead
space
Time
(sec)
Dead
space
Circuits
Block
#
Bus
#
apte
9
5
11
4.11%
8
1.59%
12
0.72%
3
0.02%
xerox
10
6
12
3.88%
5
3.85%
13
0.95%
6
0.10%
hp
11
14
28
5.02%
20
4.47%
28
0.62%
11
0.03%
ami33-1
33
8
61
6.02%
19
5.69%
62
0.94%
35
0.33%
ami33-2
33
18
81
6.10%
22
3.87%
86
1.27%
35
0.73%
ami49-1
49
9
98
5.42%
28
5.34%
101
0.85%
65
0.51%
ami49-2
49
12
278
6.09%
43
5.45%
281
0.84%
90
0.67%
ami49-3
49
15
265
7.40%
66
4.74%
268
1.09%
109
0.92%
104
5.51%
26
4.38%
106
0.91%
47
0.41%
Average
*SP: Hua Xiang, Xiaoping Tang, and Martin D.F. Wong, “Bus-driven floorplanning”, ICCAD 2003.
The platform of SP is Intel Xeon 2.4GHz.
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BDF Result
․ MCNC ami49-3
with soft block
adjustment.
․ It has 49 macro
blocks and 15
buses.
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Outline
․Introduction
․Fast simulated annealing scheme
․Fixed-outline floorplanning
․Bus-driven floorplanning
․Conclusion
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Conclusion
․ Have proposed algorithms for the modern
floorplanning problems with fixed-outline
constraints and bus-constraints based on the
new Fast-SA scheme.
․ Have shown Fast-SA leads to faster and stabler
convergence to desired floorplan solutions.
․ Have shown the efficiency and effectiveness of
our floorplanning algorithms for fixedoutline/bus-driven floorplanning.
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B*-tree 2005 will be available soon at
http://eda.ee.ntu.edu.tw/research.htm
B*-tree 1.0 (year 2000) + new perturbations + Fast-SA
Thank you for your attention!
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