Transcript Diapositive 1

MTVV 2009
--Automated tests generation
from SysML models
July 1st 2009
--Jonathan Lasalle
Outline
Test Designer
VETESS project
SysML/SysML4MBT
Test Generation Strategies
Conclusion and future works
17 juillet 2015
2
Test Designer
TEST MODEL
UML4ST
RSM
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PIVOT FILE
UML Java
Test
Designer™
Tests
3
Example : front lightings
Vehicle front lightings Management
(HighLights + HeadLights)
Actions :
• Turn on/off HighLights
• Turn on/off HeadLights
4 possible states :
•
•
•
•
All Lights OFF
HighLights Only
HeadLights Only
All Lights ON
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UML4ST (UML for Smartesting)
1 class diagram (static view)
1 object diagram (representation of the
initial state of the system)
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UML4ST (UML for Smartesting)
1 statemachine diagram (dynamic view)
Trigger : Operation Call
Guard : Boolean expression (OCL)
Action : OCL expression
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Outline
Test Designer
VETESS project
SysML/SysML4MBT
Test Generation Strategies
Conclusion and future works
17 juillet 2015
7
VETESS project
VETESS = Vérification de systèmes embarqués
VEhicule par génération automatique de TESts à partir
des Spécifications
Project labelized by the Competitiveness Cluster
«Véhicule du Futur» (2008/2010)
Project members :
•
•
•
•
•
Smartesting : editor of MBT’s software (Test Designer)
Clemessy : concepteur de bancs de validation
PSA : car manufacturer
LIFC : Model Based Testing experience (MBT)
MIPS : Model Driven Engineering experience (MDE)
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VETESS project
Specification of systems under test (SUT) with
SysML behavioral models
Automated tests generation from SysML models
with Test Designer (Smartesting)
Export and execution of tests on TestInView
platform (Clemessy)
Automation of this process with a tools
framework which contains those parts.
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Tools framework
TEST MODEL
UML4ST
RSM
PIVOT FILE
UML Java
Tests
+
TEST MODEL
UML4ST
PAPYRUS
UML4ST
MetaModel
Test
Designer
™
Adaptation layer
(TestInView Library)
+
ib d [block] PowerSubsystem [Alternative 1 - Combined Motor Generator]
epc:ElectricalPower
<>
Controller
ctrl
<>
i2:Electric
Current
emg:ElectricMotor
Generator
i1:Electric
Current
<>
I_IEPCCmd
<>
I_T RSMCmd
ctrl
trsm:T ransmission
c3
<>
I_T RSMData
I_EPCCmd
I_IEPCData
torquein:T orque
c2
rightHalfShaft
I_T RSMData
g1:T orque
torqueOut:T orque
<>
t1:Torque
epc trsm
ecu:PowerControlUnit
ice
rfw:ChassisSubsytem
.F rontWheel
spline
<>
I_IEPCData
t2:Torque
bp:BatteryPack
acl:accelerator
<>
I_T RSMCmd
dif:Differential
ice:InternalCombustionEngine
I_ICEData
<>
I_ICEData
ctrl
c1
4
fi:F uelInjector
leftHalfShaft
I_ICECmds
bp:BrakeSubsystem
.BrakePedal
fdist
<>
<>
<>
I_ICECmds
Port:ICEF uelF itting
ft:F uelT ankAssy
Port:F uelT ankF itting
fp:F uelPump
<>
fuelSupply:F uel
lfw:ChassisSubsytem
.F rontWheel
SysML4MBT
Metamodel
Embedded
Dedicated tests
fuelDelivery
fuelReturn:F uel
TEST MODEL
SysML4MBT
PAPYRUS
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Scientific challenge
To consider models with parallelism
Reactive systems (Transmission of
Signals)
To consider the system and his
environment
Test Generation strategies dedicated to
those problematics
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Outline
Test Designer
VETESS project
SysML/SysML4MBT
Test Generation Strategies
Conclusion and future works
17 juillet 2015
12
SysML
System Modeling Language
Modeling language for system
engineering
Subset of UML with extensions
OMG :
SysML 1.0 since September 2007
SysML = UML profile
Fit to modeling embedded system
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SysML diagrams
Diagrams in both :
•
•
•
•
Use-Case diagram
Sequence diagram
Activity diagram
State Machine
diagram
• Package diagram
Variation of UML :
• Class diagram
=> Block diagram
• Composite Structure
diagram
=> Internal Block
diagram
Only on SysML
• Parametric diagram : physics equations
• Requirement diagram
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SysML4MBT : block diagram
1 block diagram
=> static view
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SysML4MBT : block diagram
Flow ports :
• Controller
 outActionHead
 outActionHigh
• HeadLights
 inActionHead
• HighLights
 inActionHigh
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SysML4MBT : internal block diag.
1 internal block diagram
=> interconnections between blocks
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SysML4MBT : state machine diag.
1 or more statemachine diagram(s)
=> dynamic view of system parts
RECEIVE 2
SEND 3
SEND 2
SEND 4
SEND 1
RECEIVE 3
RECEIVE 1
SEND 1
SEND 4
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SEND 2
SEND 3
RECEIVE 4
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Scientific challenge
To consider models with parallelism
OK => Several state machine diagrams
Reactive systems (Transmission of
Signals)
OK => ports + signal
To consider the system and his
environment
OK => Several state machine diagrams
Test Generation strategies dedicated to
those problematics
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Outline
Test Designer
VETESS project
SysML/SysML4MBT
Test Generation Strategies
Conclusion and future works
17 juillet 2015
20
Test Generation Strategy : TD
Test Designer
• All behaviors
• For each behavior
=> 1 test case which passes through the
behavior
• Action of a transition:
IF (BOOL) THEN
TEST 1
Action A
(with BOOL = true)
Else
TEST 2
Action B
(with BOOL = false)
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Test Generation Strategy : DUvar
Uses state variables
For each variable Var
• For each behavior B1 which defines Var (Var = 5)
 For each behavior B2 which uses Var
(Var2 = Var)
– B1/B2 is a pair
Criteria :
• All_Uses : Coverage of each pair B1/B2 (1 path)
• All_Def_Use_Paths : Coverage of all paths for each
pair B1/B2
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Test Generation Strategy : ComCover
Uses connectors
For each connector Connect
• For each Behavior B1 which sends signal on
Connect
 For each Behavior B2 which receives signal sent
by B1
– B1/B2 is a pair
Criteria
• All_Receives : Coverage of each pair B1/B2 (1 path)
• All_Send_Receive_Paths : Coverage of all paths for
each pair B1/B2
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Test Generation Strategy : Scenario
Scenarios defined by the user
3 ideas:
• With valuated paths
 Ex : CallOp1(5), CallOp2(4), CallOp1(8)
• With not-valuated paths :
 Ex : CallOp1(?), CallOp2(?), CallOp1(5)
• With not-valuated not-complete paths :
 Ex : CallOp1(?), ?, CallOp2(6)
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Experimentations
FrontLightings
FrontWiper (manual)
Nb statemachine
3
6
Nb states
(4,2,2)
(1,1,1,1,14,2)
Nb transitions
(8,2,2)
(2,2,2,1,20,3)
Nb tests algo TD
12
30
Coverage Algo TD
All_transitions
Nb tests DUvar
0
15
Coverage All_Uses
None
None
Nb tests ComCover
8
13
Coverage All_Receives
DU-PATHS
None
Coverage
DUvar+ComCover
DU-PATHS
DU-PATHS
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Outline
Test Designer
VETESS project
SysML/SysML4MBT
Test Generation Strategies
Conclusion and future works
17 juillet 2015
26
Conclusion & Outlook
TEST MODEL
UML4ST
RSM
PIVOT FILE
UML Java
Tests
+
TEST MODEL
UML4ST
PAPYRUS
UML4ST
MetaModel
Test
Designer
™
Adaptation layer
(TestInView Library)
+
ib d [block] PowerSubsystem [Alternative 1 - Combined Motor Generator]
epc:ElectricalPower
<>
Controller
ctrl
<>
i2:Electric
Current
emg:ElectricMotor
Generator
i1:Electric
Current
I_IEPCCmd
<>
ctrl
trsm:T ransmission
<>
I_T RSMData
I_IEPCData
torquein:T orque
c2
rightHalfShaft
I_T RSMData
g1:T orque
torqueOut:T orque
<>
t1:Torque
epc trsm
ecu:PowerControlUnit
ice
rfw:ChassisSubsytem
.F rontWheel
spline
<>
I_T RSMCmd
c3
I_EPCCmd
<>
I_T RSMCmd
dif:Differential
ice:InternalCombustionEngine
I_ICEData
<>
I_ICEData
ctrl
c1
4
fi:F uelInjector
leftHalfShaft
I_ICECmds
bp:BrakeSubsystem
.BrakePedal
fdist
<>
<>
<>
I_ICECmds
Port:ICEF uelF itting
ft:F uelT ankAssy
Port:F uelT ankF itting
fp:F uelPump
DUvar
<>
I_IEPCData
t2:Torque
bp:BatteryPack
acl:accelerator
<>
fuelSupply:F uel
lfw:ChassisSubsytem
.F rontWheel
SysML4MBT
Metamodel
ComCover
Embedded
Dedicated tests
fuelDelivery
fuelReturn:F uel
TEST MODEL
SysML4MBT
PAPYRUS
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Scenario
27
The End
Questions?
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