ECE4430 Project Presentation

OPERATIONAL AMPLIFIER GROUP3 – DEBASHIS BANERJEE JASON PINTO ASHITA MATHEW

DESIGN SPECIFICATIONS

Technology Node –TSMC 0.18µm Required Design Specifications Technology node Supply (V) Max Power consumption (uW) Differential Gain (dB) CMRR (dB) ICMR (V) Output Swing (V) Bandwidth - 3dB (kHz) Loading (pF || kOhm) Slew Rate (V/us) TSMC 0.18

µm

2 150 100 100 0 - 2.5

0 - 2 10 10 || 100 20 2 ECE 4430 Project2 Presentation 4/27/2020

BMR & BIASING CIRCUIT

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OPERATIONAL AMPLIFIER -TOPOLOGY USED

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Transconductance stabilization circuit

5 Literature reference : M.M. Ahmadi, R. Lotfi, M. Sharif-Bakhtiar, “

A New Architecture for Rail-to-Rail Input Constant-gm, CMOS OperationaI Transconductance Amplifiers

” , ISLPED ‘03 ECE 4430 Project2 Presentation 4/27/2020

6

INITIAL DESIGN STEPS

         Redesigned BMR with 5uA reference current Designed short channel biasing circuit Total current budget = 75uA for a max power consumption of 150uW The transconductances of the PMOS NMOS pair of amplifying devices were made equal by sizing the PMOS to NMOS in the ratio kp n :kp p (5:1) Current combining stage is made low voltage headroom cascode with floating current sources for proper biasing.

The transconductance stage of diffamp was biased with 5uA each and the summing stage was designed for a current of 30uA For a rail to rail output swing, we designed a class AB push pull amplifier Using C C = 0.22C

L caused the bandwidth to be about 100Hz only.

Compensation capacitor was fine tuned iteratively to achieve a desired phase margin and maximum bandwidth possible.

ECE 4430 Project2 Presentation 4/27/2020

MAGNITUDE- PHASE PLOT

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ICMR : - 0.4 V to 2.23V

90.32dB, -0.41V

90.32dB, 2.23V

PHASE MARGIN OVER vcm

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56 degrees 50.09 degrees

4/27/2020

OUTPUT VOLTAGE SWING : 0 - 2V -0.25 V , 93dB 90.32dB, -0.41V

2.25V, 88dB 90.32dB, 2.23V

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SLEW RATE

10 Rise time = 175 ns Fall time = 171ns No ringing observed in output Positive slew rate = 9.224 V/ us Negative slew rate = -9.275 V/ us 4/27/2020

MINIMUM AND MAXIMUM SUPPLY VOLTAGE

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CMRR ACHIEVED = 140dB

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PSRR FOR VDD 108.8 dB PSRR FOR GND 108.8 dB

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MEASUREMENT OF PSRR

4/27/2020

INPUT REFERRED NOISE 35.57nV/sqrt(Hz)

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GAIN BANDWIDTHS

Unloaded BW = 434 Hz Loaded GBW = 17.36 MHz 15 ECE 4430 Project2 Presentation Unloaded GBW = 18.04 MHz 4/27/2020

INPUT OFFSET VOLTAGE = -2.01uV

MEASUREMENT OF INPUT OFFSET VOLTAGE NOMINAL OUTPUT VOLTAGE = 0.8 V

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POWER CONSUMPTION CURVES

17 with load ECE 4430 Project2 Presentation without load 4/27/2020

Op-Amp Final Specs and Simulation Results:

1 2 3 4 5 6

PARAMETER

Differential amplifier topology Reference topology Minumum Supply Voltage (V) Maximum Supply Voltage (V) Gain of differential amplifier (dB) CMRR (dB)

SPECS ACHEIVED

Folded cascode with modifications Drain regulated BMR 1.66 V 2.84V

95dB 140dB 18 13 14 10 11 7 Reference power consumption (uW) 8 OpAmp power consumption with zero input (uW) 9 OpAmp power consumption with no load (uW) 12 Total power consumption (uW) Positive Slew Rate (V/us) Negative Slew Rate (V/us) ICMR (Vmin ~ Vmax) Output Swing (Vmin ~ Vmax) ECE 4430 Project2 Presentation 162 uW 144uW 135uW 307.1uW

9.224V/us -9.275V/us -0.4V – 2.23V

0-2V 15 16 17 18 VDD PSRR (dB) GND PSRR (dB) Nominal output voltage (V) Input offset voltage (mV) 19 Unloaded Bandwidth (kHz) 20 Loaded Bandwidth (kHz) 21 Gain bandwidth product (MHz) 22 23 24 25 Compensation capacitor (pF) Phase margin (degrees) Rise time (ns) Fall time (ns) 26 Settling time (ns) Input referred noise (V/Hz^0.5) 108.8dB 108.8dB

0.8V

0.002mV

0.434 KHz 0.374KHz

17.36MHz

500pF 58.5 deg 175ns 171ns 0 35.57 nV/sqrt(Hz) 4/27/2020

DEVIATION FROM SPECS

1

Parameter

Max Power consumption (uW) 2 Differential Gain (dB)

Required Specifications

150 100

Specifications acheived

144 95

Percentage Error

-4% -5% 3 4 5 CMRR (dB) ICMR (V) Output Swing (V) 6 Bandwidth - 3dB (kHz) 100 0 - 2.5

0 - 2 19 7 Slew Rate (V/us) ECE 4430 Project2 Presentation 10 20 140 -0.4 – 2.23 0-2 0.374

9.22

+28.5% 0% -96% -53% 4/27/2020

CONCLUSION

     We observed that increasing the compensation capacitance improves the phase margin at the cost of bandwidth. For our case, the degradation in phase margin did not trade off for an appreciable increase in bandwidth.

Better common mode rejection was achieved by cascoding the tail current sources.

A gain of 95dB is not significantly deviated from 100dB because the OPAMP operates mainly as a feedback amplifier.

Since phase margin is high enough, no ringing is observed for a step response 20 ECE 4430 Project2 Presentation 4/27/2020

Thank you…

Questions??

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