Transcript Preface - 海南大学 | Hainan University | www.hainu.edu.cn

3.3 CMOS Logic
1. CMOS Logic Levels
Logic levels for typical CMOS Logic
circuits.
5.0V
Logic 1 (HIGH)
3.5V
1.5V
Logic 0 (LOW)
Undefined
Logic level
0.0V
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3.3 CMOS Logic
2. MOS Transistors
 A MOS transistor can be modeled as a 3terminal device that acts like a voltage
controlled resistance.
 In digital logic applications, a
MOS transistor is operated so
its resistance is always either V
IN
very high (and the transistor
is “off”) or very low (and the
transistor is “on”) .
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3.3 CMOS Logic

n-channel MOS (NMOS)
drain
gate
+
Vgs
-
• Vgs=0 → Rds 106 ()
source → I  10-6 (A)  0
drain
•Vgs  Vgs(th) → Rds  10
() << RL →VRds 0
gate
+
Vgs
Increase Vgs→decrease Rds
Normally, Vgs≥ 0
-
source
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3.3 CMOS Logic

p-channel MOS (PMOS)
Vgs
-
+
source Decrease Vgs→decrease Rds
Normally, Vgs 0
gate
drain
• Vgs=0 → Rds ≥ 106 ()
• Vgs  Vgs(th) → Rds  10 ()
Vgs source
-
+
Switch
Model
gate
drain
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3.3 CMOS Logic
3. Basic CMOS Inverter Circuit
VDD=+5.0V
Q2 (PMOS)
VOUT
VIN
VDD=+5.0V
VOUT=H
VIN=L
Q1 (NMOS)
VDD=+5.0V
VIN Q1 Q2 VOUT
0.0(L) off on 5.0(H)
VOUT=L
VIN=H
5.0(H) on off 0.0(L)
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3.3 CMOS Logic

CMOS inverter logical operation
On when
Vin is low.
Truth table for
VDD=+5.0V CMOS inverter
Q2 (PMOS)
Z
A
On when
Vin is high.
Q1 (NMOS)
A
0
1
Z
1
0
ZA
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3.3 CMOS Logic
4. CMOS NAND Gates
A
L
L
H
H
A
0
0
1
1
B
L
H
L
H
VDD
Q1
off
off
on
on
Q2 Q3 Q4 Z
on off on H
on on off H
off off on H
off on off L A
VDD
V
V
DD
DD
B Z
B
0 1
Z Z=H
A
B
Z=H
Z=H
Z=L
1
1
A=L
A=L
A=H
0 1 A
Z
B=L
B=H
B=L
B=H
1 0 B
Q2
Q4
Z
Q1
Q3
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3.3 CMOS Logic
5. CMOS NOR Gates
A
L
L
H
H
B
L
H
L
H
Q1
off
off
on
on
A
0
0
1
1
B
0
1
0
1
Z
1
0
0
0
Q2
on
on
off
off
Q3
off
on
off
on
Q4
on
off
on
off
Z
H
A
L
L B
L
VDD
Q2
Q4
Z
Z  AB
A
B
Q1
Q3
Z
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3.3 CMOS Logic
6. Fan-In
In principle,
you could design
a CMOS NAND or
Q6
Q4
NOR gate with a
Z
large number of
Why couldn't inputs. A 3-input
a CMOS gate CMOS NAND gate
has large
is showed in the
number of
figure.
inputs?
VDD
Q2
A
Q1
B
Q3
C
Q5
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3.3 CMOS Logic

Fan-In
TheA number
of transistor
inputs thathas
a gate
n-channel
low can
p-channel
have“on”
in aresistance
particular than
logic afamily
is called
transistor.
As fan-in.
a result, a k-input
the logic
family’s
NAND gate is generally faster
The
fan-in
of
CMOS
gates
is
typically
4
than a k-input NOR gate.
for NOR gates and 6 for NAND gates.
Why is the fan-in of CMOS gates for
NOR gates less than the ones for NAND
gates?
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3.3 CMOS Logic

Fan-In
As the number of inputs is increased,
designers of CMOS gate circuits may
compensate by increasing the size of the
series transistors to reduce their resistance
and the corresponding switching delay.
I1
I2
I3
I4
I5
I6
I7
I8
OUT
I1
I2
I3
I4
I5
I6
I7
I8
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OUT
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3.3 CMOS Logic
7. Noninverting Gates (P93)

AND Gate

OR Gate
8. CMOS AND-OR-INVERT Gate (P94)
9.CMOS OR-AND-INVERT Gate (P95)
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3.3 CMOS Logic
10. CMOS Steady-State Electrical Behavior
Typical input-output transfer
characteristic of a CMOS inverter
Vout
5.0
HIGH
3.5
undefined
1.5
LOW
1.5
3.5
5.0
LOW undefined HIGH
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Vin
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3.3 CMOS Logic
Logic Levels and Noise Margins

Vcc
HIGH
0.7Vcc
0.3Vcc
0
ABNORMAL
LOW
VOHmin High-state
VIHmin DC noise margin
VILmax Low-state
VOLmax DC noise margin
VOHmin: The minimum output voltage in
the HIGH state. VOHmin=VCC–0.1V

VOLmax: The maximum output voltage in
the LOW state. VOLmax=ground+0.1V

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3.3 CMOS Logic

VIHmin: The minimum input voltage
guaranteed to be recognized as a HIGH.
VIHmin=0.7VCC
VILmax: The maximum input voltage guaranteed
to be recognized as a LOW.
VILmax=0.3VCC
 DC noise margin: is a measure of how much
noise it takes to corrupt a worst-case output
voltage into a value that may not be recognized
properly by an input.
HIGH-state DC noise margin: VOHmin -VIHmin
LOW-state DC noise margin: VILmax -VOLmax

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3.3 CMOS Logic
IIH: The maximum current that flows into
the input in the HIGH state.
 IIL: The maximum current that flows into
the input in the LOW state.

Regardless of the voltage applied to the input
of a CMOS device, only the leakage current of
the transistors connected to input. This is in
sharp contrast to bipolar logic circuits like TTL
oe ECL, whose inputs consume significant
current (and power) in one or both states.
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3.3 CMOS Logic
Circuit Behavior with Resistive Loads
 Resistive Loads: (P102).
 IOLmax: The maximum current that the
output can sink in the LOW state while
still maintaining an output voltage no
greater than VOLmax.

IOHmax: The maximum current that the
output can sink in the HIGH state while
still maintaining an output voltage no
less than VOHmin.

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3.3 CMOS Logic
Fanout : The fanout of a logic gate is the
number of inputs that the gate can drive
without exceeding its worst-case loading
specifications.
 DC Fanout : the output in a constant state
(HIGH or LOW).

N OL
I OL (drive)

I IL (load)
N OH
I OH (drive)

I IH (load)
Overall Fanout : is the minimum of the
HIGH-state and LOW-state fanouts.

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3.3 CMOS Logic
11. CMOS Dynamic Electrical Behavior
 Transition Time : The amount of time that
output of a logic circuit takes to change from
one state to another.
(a) ideal case
tf
VIHmin
VILmax
tr
tr
tf
(b) approximation
(C) actual case
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3.3 CMOS Logic
Rise time(tr) : the amount of time an
output voltage takes to pass through the
“undefined” region from LOW to HIGH.

Fall time(tf) : the amount of time an
output voltage takes to pass through the
“undefined” region from HIGH to LOW.

The rise and fall times of a CMOS
output depend mainly on two factors,
the “on” transistor resistance and the
load capacitance.
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3.3 CMOS Logic

Propagation Delay : the amount of time that
it takes for a change in the input signal to
produce a change in the output signal.


tpHL
tpL
H
Propagation delays for a
CMOS inverter
ttpH
The time
time
L:: The
pLH
between
between an
an input
input
change
change and
and the
the
corresponding
corresponding
output
output change
change when
when
the
the output
output isis
changing
changing from
from HIGH
LOW
to
to LOW.
HIGH.
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3.3 CMOS Logic
Propagation delays for a CMOS inverter
measured at midpoints of transitions
50% VIH
50% VOH
tpHL

Power Consumption
tpL
H
Static power dissipation: The power
consumption of a CMOS circuit whose
output is not changing.

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3.3 CMOS Logic
Most CMOS circuits have very low quiescent
power dissipation. This is what makes them so
attractive for laptop computers and other lowpower application.
 Dynamic power
PT: The circuit’s internal
dissipation: The
power dissipation due to
power consumption output transitions.
of a CMOS circuit
CPD: The powerwhose output is
dissipation capacitance.
changing. It’s
f : The transition
significant.
frequency of the output
PT  CPD VCC2  f
signal.
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3.3 CMOS Logic
PL  CL V  f
2
CC
PL: the total amount of power dissipated by
charging and discharging CL.
CL: capacitive load on the output.
The total dynamic power dissipation PD of
a CMOS circuit is the sum of PT and PL.
PD  PT  PL  (CPD  CL ) V  f
2
CC
Based on this formula, dynamic power
dissipation is often called CV2f power.
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3.3 CMOS Logic
Notice
(1) The output voltage will move away from
the power-supply rail with nonideal inputs.
(2) A slightly overloaded circuit will fail.
Loading an output beyond its rated fanout will
make the output voltage(VOL) increase beyond
VOLmax in the LOW state, and the output
voltage(VOH) fall bellow VOHmin in the HIGH state,
and propagation delay to the output increase
beyond specification, and out rise and fall times
increase beyond specification, and the operating
temperature of the device increase.
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3.3 CMOS Logic
A
(3) An unused inputs
B
can be tied to another.
An unused AND or
NAND input can be
tied to logic 1.
A
B
+5V pull-up
1k resistor
F
C
F
C
An unused OR or
NOR input can be tied
to logic 0.
F
A
B
C
pull-down
1k
resistor
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3.3 CMOS Logic
A pull-up or pull-down resistor is usually
used. The resistor value is typically in the
range 1-10k. Such a single resistor can
serve multiple unused inputs. It is also
possible to tie unused inputs directly to
the appropriate power-supply rail.
Unused CMOS inputs should
never be left unconnected (or
floating). Why?
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3.3 CMOS Logic
(4) Systems that use CMOS circuits
require decoupling capacitors between
VCC and ground.
(5) ESD(Electro-Static Discharge)
may damage the insulation between an
input transistor’s gate and source and
drain, causing a short-circuit between
the device’s input and output.
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3.3 CMOS Logic
12. Transmission Gates
EN_L=0
EN_L
A
A
B
B
EN=1
EN
How can you create a
2-input multiplexer using
transmission gates?
(P123)
EN_L=1
A
B
EN=0
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3.3 CMOS Logic
13. Schmitt-Trigger Inputs
VOUT
5.0
VT- VT+
2.1 2.9
5.0
VIN
Voltage of hysteresis =VT+-VTReturn
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3.3 CMOS Logic
14. Three-State Outputs
VCC
VVCC
CC
C
EN
D
A
CC
EN
EN
OUT
D
D
A
A
OUT
OUT
B
EN
L
L
H
H
A
L
H
L
H
B
H
H
L
L
C
H
H
H
L
D
L
L
H
L
Q1
off
off
on
off
Q2 OUT
off Hi-Z
off Hi-Z
off
L
on H
EN
A
Return
OUT
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3.3 CMOS Logic
15. Open-Drain Outputs
VCC
Z
A
Q2
B
Q1
A
B
A
L
L
H
H
B
L
H
L
H
Q1
off
off
on
on
Q2
Z
off open
on open
off open
on
L
Pull-up
resistor
Z
A
B
VP
RP
RL
Return
Z
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3.3 CMOS Logic

Pull-up resistor calculation
RP
A
B
IOHmin
Rp max 
VP
ILH
RL
Z=VOHmin
Open-drain gates
can be useful in driving
A
light-emitting diodes
(LEDs) and other
B
devices; performing
wired logic; and driving
multisource buses.
R p min 
Vp  VOH min
I OH min  I LH
V p  VOL max
I OL max  I LL
RP
VP
IOLmax ILL
RL
Return
Z=VOHmin
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3.3 CMOS Logic
16. CMOS Logic Families
The first commercially successful CMOS
family was 4000-series CMOS.
74 FAM nn
prefix
Alphabetic
family
mnemonic
Numeric
function
designator
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3.3 CMOS Logic




HC: High-speed CMOS
HCT: High-speed CMOS, TTL compatible
VHC: Very High-speed CMOS
VHCT: Very High-speed CMOS, TTL compatible
Electrical characteristics of the
HC, HCT, VHC, and VHCT are
different. They are summarized on
page 137-144 in the text-book.
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