Transcript No Slide Title

14 Control Unit Synthesis
The control unit for the single-cycle design is memoryless
• Problematic when instructions vary greatly in complexity
• Multiple cycles needed when resources must be reused
Topics in This Chapter
14.1 A Multicycle Implementation
14.2 Choosing the Clock Cycle
14.3 The Control State Machine
14.4 Performance of the Multicycle Design
14.5 Microprogramming
14.6 Exception Handling
14.1 A Multicycle Implementation
Clock
Time
needed
Time
allotted
Instr 1
Instr 2
Instr 3
Instr 4
Clock
Time
needed
Time
allotted
Time
saved
3 cycles
5 cycles
3 cycles
4 cycles
Instr 1
Instr 2
Instr 3
Instr 4
Fig. 14.1
Single-cycle versus multicycle instruction execution.
A Multicycle Data Path
Inst Reg
x Reg
jta
Address
rs,rt,rd
(rs)
PC
imm
Cache
z Reg
Reg
file
ALU
(rt)
Data
Data Reg
op
y Reg
fn
Control
Fig. 14.2
Abstract view of a multicycle instruction execution unit for
MicroMIPS. For naming of instruction fields, see Fig. 13.1.
Multicycle Data Path with Control Signals Shown
26
/
30
/
4 MSBs
Inst Reg
rt
0
rd 1
31 2
Cache
Data Reg
InstData
PCWrite
(rs)
Reg
file
0
1
Data
MemWrite
MemRead
Fig. 14.3
op
IRWrite
(rt)
imm 16
/
fn
ALUZero
x Mux
ALUOvfl
0
Zero
z Reg
1
Ovfl
x Reg
rs
PC
0
1
SysCallAddr
jta
Address
32 y Reg
SE /
RegInSrc
RegDst
0
1
RegWrite
y Mux
4
0
1
2
4 3
ALUSrcX
ALUSrcY
30
4
ALU
0
1
2
3
Func
ALU out
ALUFunc
PCSrc
JumpAddr
Key elements of the multicycle MicroMIPS data path.
14.2 Clock Cycle and Control Signals
Table 14.1
Program
counter
Cache
Register
file
ALU
Control signal
0
1
JumpAddr
jta
SysCallAddr
PCSrc1, PCSrc0
Jump addr
x reg
PCWrite
Don’t write
Write
InstData
PC
z reg
MemRead
Don’t read
Read
MemWrite
Don’t write
Write
IRWrite
Don’t write
Write
RegWrite
Don’t write
Write
RegDst1, RegDst0
rt
rd
RegInSrc
Data reg
z reg
ALUSrcX
PC
x reg
ALUSrcY1, ALUSrcY0
4
y reg
AddSub
Add
Subtract
LogicFn1, LogicFn0
AND
FnClass1, FnClass0
lui
2
z reg
3
ALU out
$31
imm
4  imm
OR
XOR
NOR
Set less
Arithmetic
Logic
Execution
Cycles
Fetch &
PC incr
Decode &
reg read
Table 14.2
Instruction
Operations
Signal settings
Any
Read out the instruction and
write it into instruction register,
increment PC
Any
Read out rs & rt into x & y
registers, compute branch
address and save in z register
Perform ALU operation and save
the result in z register
Add base and offset values, save
in z register
If (x reg) =  < (y reg), set PC to
branch target address
InstData = 0, MemRead = 1
IRWrite = 1, ALUSrcX = 0
ALUSrcY = 0, ALUFunc = ‘+’
PCSrc = 3, PCWrite = 1
ALUSrcX = 0, ALUSrcY = 3
ALUFunc = ‘+’
1
2
Load
ALUSrcX = 1, ALUSrcY = 1 or 2
ALUFunc: Varies
ALUSrcX = 1, ALUSrcY = 2
ALUFunc = ‘+’
ALUSrcX = 1, ALUSrcY = 1
ALUFunc= ‘’, PCSrc = 2
PCWrite = ALUZero or
ALUZero or ALUOut31
Set PC to the target address jta, JumpAddr = 0 or 1,
SysCallAddr, or (rs)
PCSrc = 0 or 1, PCWrite = 1
Write back z reg into rd
RegDst = 1, RegInSrc = 1
RegWrite = 1
Read memory into data reg
InstData = 1, MemRead = 1
Store
Copy y reg into memory
InstData = 1, MemWrite = 1
Load
Copy data register into rt
RegDst = 0, RegInSrc = 0
RegWrite = 1
ALU type
Load/Store
ALU oper
& PC
update
3
Branch
Jump
ALU type
Reg write
or mem
access
Reg write
for lw
4
5
Execution cycles for multicycle MicroMIPS
14.3 The Control State Machine
Cycle 1
Cycle 2
Notes for State 5:
% 0 for j or jal, 1 for syscall,
don’t-care for other instr’s
@ 0 for j, jal, and syscall,
1 for jr, 2 for branches
# 1 for j, jr, jal, and syscall,
ALUZero () for beq (bne),
bit 31 of ALUout for bltz
For jal, RegDst = 2, RegInSrc = 1,
RegWrite = 1
State 0
InstData = 0
MemRead = 1
IRWrite = 1
ALUSrcX = 0
ALUSrcY = 0
ALUFunc = ‘+’
PCSrc = 3
PCWrite = 1
Jump/
Branch
State 1
ALUSrcX = 0
ALUSrcY = 3
ALUFunc = ‘+’
Fig. 14.4
Cycle 4
State 5
ALUSrcX = 1
ALUSrcY = 1
ALUFunc = ‘’
JumpAddr = %
PCSrc = @
PCWrite = #
State 6
Cycle 5
InstData = 1
MemWrite = 1
sw
lw/
sw
Start
Note for State 7:
ALUFunc is determined based
on the op and fn fields
Cycle 3
ALUtype
State 2
ALUSrcX = 1
ALUSrcY = 2
ALUFunc = ‘+’
lw
State 3
State 4
InstData = 1
MemRead = 1
RegDst = 0
RegInSrc = 0
RegWrite = 1
State 7
State 8
ALUSrcX = 1
ALUSrcY = 1 or 2
ALUFunc = Varies
RegDst = 0 or 1
RegInSrc = 1
RegWrite = 1
The control state machine for multicycle MicroMIPS.
State and Instruction Decoding
op
/4
5
6
7
8
9
10
11
12
13
14
15
ControlSt0
ControlSt1
ControlSt2
ControlSt3
ControlSt4
ControlSt5
ControlSt6
ControlSt7
ControlSt8
0
1
2
3
4
1
8
10
sltiInst
12
13
14
15
andiInst
oriInst
xoriInst
luiInst
35
lwInst
43
63
Fig. 14.5
/6
RtypeInst
bltzInst
jInst
jalInst
beqInst
bneInst
addiInst
andiInst
5
op Decoder
st Decoder
0
1
2
3
4
1
fn
/6
0
8
fn Decoder
st
jrInst
12
syscallInst
32
addInst
34
subInst
36
37
38
39
andInst
orInst
xorInst
norInst
42
sltInst
swInst
63
State and instruction decoders for multicycle MicroMIPS.
Control Signal Generation
Certain control signals depend only on the control state
ALUSrcX = ControlSt2  ControlSt5  ControlSt7
RegWrite = ControlSt4  ControlSt8
Auxiliary signals identifying instruction classes
addsubInst = addInst  subInst  addiInst
logicInst = andInst  orInst  xorInst  norInst  andiInst  oriInst  xoriInst
Logic expressions for ALU control signals
AddSub = ControlSt5  (ControlSt7  subInst)
FnClass1 = ControlSt7  addsubInst  logicInst
FnClass0 = ControlSt7  (logicInst  sltInst  sltiInst)
LogicFn1 = ControlSt7  (xorInst  xoriInst  norInst)
LogicFn0 = ControlSt7  (orInst  oriInst  norInst)
14.4 Performance of the Multicycle Design
R-type
Load
Store
Branch
Jump
44%
24%
12%
18%
2%
4 cycles
5 cycles
4 cycles
3 cycles
3 cycles
Contribution to CPI
R-type
0.444 = 1.76
Load
0.245 = 1.20
Store
0.124 = 0.48
Branch 0.183 = 0.54
Jump
0.023 = 0.06
ALU-type
P
C
Load
P
C
Store
P
C
Branch
P
C
(and jr)
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
_____________________________
Average CPI  4.04
Jump
(except
jr & jal)
P
C
Not
used
Fig. 13.6 The MicroMIPS data path unfolded (by depicting the register write
step as a separate block) so as to better visualize the critical-path latencies.
14.5 Microprogramming
PC
control
Cache
control
JumpAddr
PCSrc
PCWrite
InstData
MemRead
MemWrite
IRWrite
Fig. 14.6
Register
control
ALU
inputs
ALU Sequence
function control
FnType
LogicFn
AddSub
ALUSrcY
ALUSrcX
RegInSrc
RegDst
RegWrite
Possible 22-bit microinstruction format for MicroMIPS.
fetch: -------------
Control Unit for
Microprogramming
Dispatch
table 1
Dispatch
table 2
0
0
1
2
3
Multiway
branch
MicroPC
1
Address
andi: ---------
Microprogram
memory or PLA
Incr
Data
Microinstruction register
op (from
instruction
register)
Fig. 14.7
Control signals to data path
Microprogrammed control unit for MicroMIPS .
Sequence
control
fetch:
Microprogram for
MicroMIPS
Fig. 14.8
The complete
MicroMIPS
microprogram.
PCnext, CacheFetch, PC+4
PC + 4imm, mPCdisp1
lui1:
lui(imm)
rt  z, mPCfetch
add1:
x + y
rd  z, mPCfetch
sub1:
x - y
rd  z, mPCfetch
slt1:
x - y
rd  z, mPCfetch
addi1:
x + imm
rt  z, mPCfetch
slti1:
x - imm
rt  z, mPCfetch
and1:
x  y
rd  z, mPCfetch
or1:
x  y
rd  z, mPCfetch
xor1:
x  y
rd  z, mPCfetch
nor1:
x  y
rd  z, mPCfetch
andi1:
x  imm
rt  z, mPCfetch
ori1:
x  imm
rt  z, mPCfetch
xori:
x  imm
rt  z, mPCfetch
lwsw1:
x + imm, mPCdisp2
lw2:
CacheLoad
rt  Data, mPCfetch
sw2:
CacheStore, mPCfetch
j1:
PCjump, mPCfetch
jr1:
PCjreg, mPCfetch
branch1: PCbranch, mPCfetch
jal1:
PCjump, $31PC, mPCfetch
syscall1:PCsyscall, mPCfetch
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
0 (start)
1
7lui
8lui
7add
8add
7sub
8sub
7slt
8slt
7addi
8addi
7slti
8slti
7and
8and
7or
8or
7xor
8xor
7nor
8nor
7andi
8andi
7ori
8ori
7xori
8xori
2
3
4
6
5j
5jr
5branch
5jal
5syscall
14.6 Exception Handling
Exceptions and interrupts alter the normal program flow
Examples of exceptions (things that can go wrong):




ALU operation leads to overflow (incorrect result is obtained)
Opcode field holds a pattern not representing a legal operation
Cache error-code checker deems an accessed word invalid
Sensor signals a hazardous condition (e.g., overheating)
Exception handler is an OS program that takes care of the problem
 Derives correct result of overflowing computation, if possible
 Invalid operation may be a software-implemented instruction
Interrupts are similar, but usually have external causes (e.g., I/O)
Cycle 1
Exception
Control
States
Cycle 2
Jump/
Branch
Cycle 3
Cycle 4
State 5
ALUSrcX = 1
ALUSrcY = 1
ALUFunc = ‘’
JumpAddr = %
PCSrc = @
PCWrite = #
State 6
Cycle 5
InstData = 1
MemWrite = 1
sw
State 0
InstData = 0
MemRead = 1
IRWrite = 1
ALUSrcX = 0
ALUSrcY = 0
ALUFunc = ‘+’
PCSrc = 3
PCWrite = 1
State 1
ALUSrcX = 0
ALUSrcY = 3
ALUFunc = ‘+’
lw/
sw
Start
ALUtype
Illegal
operation
Fig. 14.10
State 2
ALUSrcX = 1
ALUSrcY = 2
ALUFunc = ‘+’
lw
State 3
State 4
InstData = 1
MemRead = 1
RegDst = 0
RegInSrc = 0
RegWrite = 1
State 7
State 8
ALUSrcX = 1
ALUSrcY = 1 or 2
ALUFunc = Varies
RegDst = 0 or 1
RegInSrc = 1
RegWrite = 1
State 10
IntCause = 0
CauseWrite = 1
ALUSrcX = 0
ALUSrcY = 0
ALUFunc = ‘’
EPCWrite = 1
JumpAddr = 1
PCSrc = 0
PCWrite = 1
Overflow
State 9
IntCause = 1
CauseWrite = 1
ALUSrcX = 0
ALUSrcY = 0
ALUFunc = ‘’
EPCWrite = 1
JumpAddr = 1
PCSrc = 0
PCWrite = 1
Exception states 9 and 10 added to the control state machine.