Adventures on the Sea of Interconnection Networks
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Transcript Adventures on the Sea of Interconnection Networks
Part IV
Data Path and Control
Computer Architecture, Data Path and Control
Slide 1
IV Data Path and Control
Topics in This Part
Chapter 13 Instruction Execution Steps
Chapter 14 Control Unit Synthesis
Computer Architecture, Data Path and Control
Slide 2
13 Instruction Execution Steps
Topics in This Chapter
13.1 A Small Set of Instructions
13.2 The Instruction Execution Unit
13.3 A Single-Cycle Data Path
13.4 Branching and Jumping
13.5 Deriving the Control Signals
13.6 Performance of the Single-Cycle Design
Computer Architecture, Data Path and Control
Slide 3
13.1 A Small Set of Instructions
31
R
I
op
25
rs
rt
20
15
rd
10
sh
fn
5
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
Opcode
Source 1
or base
Source 2
or dest’n
Destination
Unused
Opcode ext
imm
Operand / Offset, 16 bits
jta
J
Jump target address, 26 bits
inst
Instruction, 32 bits
Fig. 13.1
MicroMIPS instruction formats and naming of the various fields.
We will refer to this diagram later
Seven R-format ALU instructions (add, sub, slt, and, or, xor, nor)
Six I-format ALU instructions (lui, addi, slti, andi, ori, xori)
Two I-format memory access instructions (lw, sw)
Three I-format conditional branch instructions (bltz, beq, bne)
Four unconditional jump instructions (j, jr, jal, syscall)
Computer Architecture, Data Path and Control
Slide 4
0
The MicroMIPS
Instruction Set
Copy
Arithmetic
Logic
Memory access
Control transfer
Instruction
Usage
Load upper immediate
Add
Subtract
Set less than
Add immediate
Set less than immediate
AND
OR
XOR
NOR
AND immediate
OR immediate
XOR immediate
Load word
Store word
Jump
Jump register
Branch less than 0
Branch equal
Branch not equal
Jump and link
System call
lui
rt,imm
add
rd,rs,rt
sub
rd,rs,rt
slt
rd,rs,rt
addi rt,rs,imm
slti rd,rs,imm
and
rd,rs,rt
or
rd,rs,rt
xor
rd,rs,rt
nor
rd,rs,rt
andi rt,rs,imm
ori
rt,rs,imm
xori rt,rs,imm
lw
rt,imm(rs)
sw
rt,imm(rs)
j
L
jr
rs
bltz rs,L
beq
rs,rt,L
bne
rs,rt,L
jal
L
syscall
Computer Architecture, Data Path and Control
op fn
15
0
0
0
8
10
0
0
0
0
12
13
14
35
43
2
0
1
4
5
3
0
Slide 5
32
34
42
36
37
38
39
8
12
13.2 The Instruction Execution Unit
Next addr
jta
rs,rt,rd
PC
Instr
cache
(rs)
Reg
file
inst
ALU
Address
Data
Data
cache
(rt)
imm
op fn
Control
Fig. 13.2
Abstract view of the instruction execution unit for MicroMIPS.
For naming of instruction fields, see Fig. 13.1.
Computer Architecture, Data Path and Control
Slide 6
13.3 A Single-Cycle Data Path
Incr PC
Next addr
jta
Next PC
ALUOvfl
(PC)
PC
(rs)
rs
rt
Instr
cache
inst
rd
31
imm
op
Br&Jump
Fig. 13.3
0
1
2
Ovfl
Reg
file
ALU
(rt)
/
16
0
32
SE / 1
Func
ALU
out
Data
addr
Data
cache
Data
out
Data
in
0
1
2
Register input
fn
RegDst
RegWrite
ALUSrc
ALUFunc
DataRead
RegInSrc
DataWrite
Key elements of the single-cycle MicroMIPS data path.
Computer Architecture, Data Path and Control
Slide 7
ConstVar
Shift function
Constant
5
amount
0
Amount
5
1
5
Variable
amount
2
00
01
10
11
No shift
Logical left
Logical right
Arith right
Shifter
Function
class
32
5 LSBs
imm
Adder
y
32
k
/
c 31
xy
Shift
Set less
Arithmetic
Logic
0
0 or 1
c0
32
00
01
10
11
An ALU for
MicroMIPS
2
Shifted y
x
lui
s
MSB
32
2
32
Shorthand
symbol
for ALU
1
Control
c 32
3
x
Func
AddSub
s
ALU
Logic
unit
AND
OR
XOR
NOR
00
01
10
11
Ovfl
y
32input
NOR
Zero
2
Logic function
Zero
Ovfl
Fig. 10.19 A multifunction ALU with 8 control signals (2 for function class,
1 arithmetic, 3 shift, 2 logic) specifying the operation.
Computer Architecture, Data Path and Control
Slide 8
13.4 Branching and Jumping
Update
options
for PC
(PC)31:2 + 1
(PC)31:2 + 1 + imm
(PC)31:28 | jta
(rs)31:2
SysCallAddr
Default option
When instruction is branch and condition is met
When instruction is j or jal
When the instruction is jr
Start address of an operating system routine
BrTrue
/
30
IncrPC
/
30
Adder
c in
0
1
2
3
NextPC
/
30
/
30
/
30
/
30
/
30
1
(rt)
/
32
(rs)
/
30
(PC)31:2
/
26
jta
30
MSBs
SE
/
30
/
32
4
16
imm
MSBs
SysCallAddr
PCSrc
Fig. 13.4
/
30
Branch
condition
checker
BrType
Next-address logic for MicroMIPS (see top part of Fig. 13.3).
Computer Architecture, Data Path and Control
Slide 9
13.5 Deriving the Control Signals
Table 13.2 Control signals for the single-cycle MicroMIPS implementation.
Control signal
Reg
file
ALU
Data
cache
Next
addr
0
1
2
3
RegWrite
Don’t write
Write
RegDst1, RegDst0
rt
rd
$31
RegInSrc1, RegInSrc0
Data out
ALU out
IncrPC
ALUSrc
(rt )
imm
AddSub
Add
Subtract
LogicFn1, LogicFn0
AND
OR
XOR
NOR
FnClass1, FnClass0
lui
Set less
Arithmetic
Logic
DataRead
Don’t read
Read
DataWrite
Don’t write
Write
BrType1, BrType0
No branch
beq
bne
bltz
PCSrc1, PCSrc0
IncrPC
jta
(rs)
SysCallAddr
Computer Architecture, Data Path and Control
Slide 10
Computer Architecture, Data Path and Control
00
01
10
11
00
01
10
0
0
FnClass
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
PCSrc
0
1
1
0
1
00
10
10
01
10
01
11
11
11
11
11
11
11
10
10
BrType
10 10
1
0
0
0
1
1
0
0
0
0
1
1
1
1
1
LogicFn
01
01
01
01
01
01
01
01
01
01
01
01
01
00
Add’Sub
00
01
01
01
00
00
01
01
01
01
00
00
00
00
DataW rite
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
DataRead
001111
000000 100000
000000 100010
000000 101010
001000
001010
000000 100100
000000 100101
000000 100110
000000 100111
001100
001101
001110
100011
101011
000010
000000 001000
000001
000100
000101
000011
000000 001100
ALUSrc
fn
RegInS rc
Load upper immediate
Add
Subtract
Set less than
Add immediate
Set less than immediate
AND
OR
XOR
NOR
AND immediate
OR immediate
XOR immediate
Load word
Store word
Jump
Jump register
Branch on less than 0
Branch on equal
Branch on not equal
Jump and link
System call
op
RegDst
Table 13.3
Instruction
RegWrite
Control
Signal
Settings
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
10
00
00
00
01
11
11
01
10
00
Slide 11
0
3
4
5
bltzInst
jInst
jalInst
beqInst
bneInst
8
addiInst
1
2
10
sltiInst
12
13
14
15
andiInst
oriInst
xoriInst
luiInst
35
lwInst
43
63
Fig. 13.5
/6
RtypeInst
0
8
fn Decoder
1
fn
/6
op Decoder
Instruction
Decoding
op
jrInst
12
syscallInst
32
addInst
34
subInst
36
37
38
39
andInst
orInst
xorInst
norInst
42
sltInst
swInst
63
Instruction decoder for MicroMIPS built of two 6-to-64 decoders.
Computer Architecture, Data Path and Control
Slide 12
Control Signal Generation
Auxiliary signals identifying instruction classes
arithInst = addInst subInst sltInst addiInst sltiInst
logicInst = andInst orInst xorInst norInst andiInst oriInst xoriInst
immInst = luiInst addiInst sltiInst andiInst oriInst xoriInst
Example logic expressions for control signals
RegWrite = luiInst arithInst logicInst lwInst jalInst
ALUSrc = immInst lwInst swInst
AddSub = subInst sltInst sltiInst
DataRead = lwInst
PCSrc0 = jInst jalInst syscallInst
Computer Architecture, Data Path and Control
Slide 13
Putting It All Together
Fig. 10.19
ConstVar
Fig. 13.4
/
30
/
30
IncrPC
/
30
Adder
0
1
2
3
/
30
/
30
/
30
/
30
/
30
/
30
1
/
32
/
32
(rs)
4
16
imm
MSBs
Shift function
Constant
5
amount
0
Amount
5
1
5
Variable
amount
2
No shift
Logical left
Logical right
Arith right
Shifter
/
30
(PC)31:2
Function
class
/
26
jta
5 LSBs
y
0 or 1
c0
32
BrType
Shift
Set less
Arithmetic
Logic
0
x
SysCallAddr
00
01
10
11
2
Shifted y
Adder
PCSrc
00
01
10
11
32
30
MSBs
SE
c in
NextPC
Branch
condition
checker
BrTrue
(rt)
32
k
/
c
c 32 31
xy
s
32
2
32
Shortha
symb
for AL
1
MSB
Cont
3
x
Fun
AddSub
A
Incr PC
Next addr
jta
Next PC
rd
31
imm
op
0
1
2
00
01
10
11
Ovfl
Reg
file
ALU
(rt)
/
16
0
32
SE / 1
ALU
out
Data
addr
Data
in
Func
Data
cache
Data
out
Zero
Ovfl
addInst
subInst
jInst
0
1
2
Register input
fn
Zero
.
.
.
.
.
.
Control
sltInst
Br&Jump
RegDst
RegWrite
ALUSrc
ALUFunc
Computer Architecture, Data Path and Control
O
y
32input
NOR
2
Logic function
(rs)
rs
rt
inst
AND
OR
XOR
NOR
ALUOvfl
(PC)
PC
Instr
cache
Logic
unit
Fig. 13.3
DataRead
RegInSrc
DataWrite
Slide 14
13.6 Performance of the Single-Cycle Design
Instruction access
2 ns
Register read
1 ns
ALU operation
2 ns
Data cache access
2 ns
Register write
1 ns
Total
8 ns
Single-cycle clock = 125 MHz
R-type 44%
6 ns
Load
24%
8 ns
Store
12%
7 ns
Branch 18%
5 ns
Jump
2%
3 ns
Weighted mean 6.36 ns
ALU-type
P
C
Load
P
C
Store
P
C
Branch
P
C
(and jr)
Jump
(except
jr & jal)
P
C
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
Fig. 13.6 The MicroMIPS data path unfolded (by depicting the register write
step as a separate block) so as to better visualize the critical-path latencies.
Computer Architecture, Data Path and Control
Slide 15
14 Control Unit Synthesis
Topics in This Chapter
14.1 A Multicycle Implementation
14.2 Choosing the Clock Cycle
14.3 The Control State Machine
14.4 Performance of the Multicycle Design
14.5 Microprogramming
14.6 Exception Handling
Computer Architecture, Data Path and Control
Slide 16
14.1 A Multicycle Implementation
Clock
Time
needed
Time
allotted
Instr 1
Instr 2
Instr 3
Instr 4
Clock
Time
needed
Time
allotted
Time
saved
3 cycles
5 cycles
3 cycles
4 cycles
Instr 1
Instr 2
Instr 3
Instr 4
Fig. 14.1
Single-cycle versus multicycle instruction execution.
Computer Architecture, Data Path and Control
Slide 17
A Multicycle Data Path
Inst Reg
x Reg
jta
Address
rs,rt,rd
(rs)
PC
imm
Cache
z Reg
Reg
file
ALU
(rt)
Data
Data Reg
op
y Reg
fn
Control
Fig. 14.2
Abstract view of a multicycle instruction execution unit for
MicroMIPS. For naming of instruction fields, see Fig. 13.1.
Computer Architecture, Data Path and Control
Slide 18
Multicycle Data Path with Control Signals Shown
26
/
30
/
4 MSBs
Inst Reg
rt
0
rd 1
31 2
Cache
Data Reg
InstData
PCWrite
(rs)
Reg
file
0
1
Data
MemWrite
MemRead
Fig. 14.3
op
IRWrite
(rt)
imm 16
/
fn
ALUZero
x Mux
ALUOvfl
0
Zero
z Reg
1
Ovfl
x Reg
rs
PC
0
1
SysCallAddr
jta
Address
32 y Reg
SE /
RegInSrc
RegDst
0
1
RegWrite
y Mux
4
0
1
2
4 3
ALUSrcX
ALUSrcY
30
4
ALU
Func
ALU out
ALUFunc
PCSrc
JumpAddr
Key elements of the multicycle MicroMIPS data path.
Computer Architecture, Data Path and Control
0
1
2
3
Slide 19
14.2 Clock Cycle and Control Signals
Table 14.1
Program
counter
Cache
Register
file
ALU
Control signal
0
1
JumpAddr
jta
SysCallAddr
PCSrc1, PCSrc0
Jump addr
x reg
PCWrite
Don’t write
Write
InstData
PC
z reg
MemRead
Don’t read
Read
MemWrite
Don’t write
Write
IRWrite
Don’t write
Write
RegWrite
Don’t write
Write
RegDst1, RegDst0
rt
rd
RegInSrc
Data reg
z reg
ALUSrcX
PC
x reg
ALUSrcY1, ALUSrcY0
4
y reg
AddSub
Add
Subtract
LogicFn1, LogicFn0
AND
FnClass1, FnClass0
lui
Computer Architecture, Data Path and Control
2
z reg
3
ALU out
$31
imm
4 imm
OR
XOR
NOR
Set less
Arithmetic
Logic
Slide 20
Execution
Cycles
Fetch &
PC incr
Decode &
reg read
Table 14.2
Instruction Operations
Load
Store
Copy y reg into memory
InstData = 1, MemWrite = 1
Load
Copy data register into rt
RegDst = 0, RegInSrc = 0
RegWrite = 1
1
Any
2
Load/Store
3
Branch
Jump
ALU type
Reg write
or mem
access
Reg write
for lw
4
5
Signal settings
Read out the instruction and
InstData = 0, MemRead = 1
write it into instruction register, IRWrite = 1, ALUSrcX = 0
increment PC
ALUSrcY = 0, ALUFunc = ‘+’
PCSrc = 3, PCWrite = 1
Read out rs & rt into x & y
ALUSrcX = 0, ALUSrcY = 3
registers, compute branch
ALUFunc = ‘+’
address and save in z register
Perform ALU operation and
ALUSrcX = 1, ALUSrcY = 1 or 2
save the result in z register
ALUFunc: Varies
Add base and offset values,
ALUSrcX = 1, ALUSrcY = 2
save in z register
ALUFunc = ‘+’
If (x reg) = < (y reg), set PC ALUSrcX = 1, ALUSrcY = 1
to branch target address
ALUFunc= ‘’, PCSrc = 2
PCWrite = ALUZero or
ALUZero or ALUOut31
Set PC to the target address
JumpAddr = 0 or 1,
jta, SysCallAddr, or (rs)
PCSrc = 0 or 1, PCWrite = 1
Write back z reg into rd
RegDst = 1, RegInSrc = 1
RegWrite = 1
Read memory into data reg
InstData = 1, MemRead = 1
Any
ALU type
ALU oper
& PC
update
Execution cycles for multicycle MicroMIPS
Computer Architecture, Data Path and Control
Slide 21
14.3 The Control State Machine
Cycle 1
Cycle 2
Notes for State 5:
% 0 for j or jal, 1 for syscall,
don’t-care for other instr’s
@ 0 for j, jal, and syscall,
1 for jr, 2 for branches
# 1 for j, jr, jal, and syscall,
ALUZero () for beq (bne),
bit 31 of ALUout for bltz
For jal, RegDst = 2, RegInSrc = 1,
RegWrite = 1
State 0
InstData = 0
MemRead = 1
IRWrite = 1
ALUSrcX = 0
ALUSrcY = 0
ALUFunc = ‘+’
PCSrc = 3
PCWrite = 1
Jump/
Branch
State 1
ALUSrcX = 0
ALUSrcY = 3
ALUFunc = ‘+’
Fig. 14.4
Cycle 4
State 5
ALUSrcX = 1
ALUSrcY = 1
ALUFunc = ‘’
JumpAddr = %
PCSrc = @
PCWrite = #
State 6
Cycle 5
InstData = 1
MemWrite = 1
sw
lw/
sw
Start
Note for State 7:
ALUFunc is determined based
on the op and fn fields
Cycle 3
ALUtype
State 2
ALUSrcX = 1
ALUSrcY = 2
ALUFunc = ‘+’
lw
State 3
State 4
InstData = 1
MemRead = 1
RegDst = 0
RegInSrc = 0
RegWrite = 1
State 7
State 8
ALUSrcX = 1
ALUSrcY = 1 or 2
ALUFunc = Varies
RegDst = 0 or 1
RegInSrc = 1
RegWrite = 1
The control state machine for multicycle MicroMIPS.
Computer Architecture, Data Path and Control
Slide 22
State and Instruction Decoding
op
/4
5
6
7
8
9
10
11
12
ControlSt0
ControlSt1
ControlSt2
ControlSt3
ControlSt4
ControlSt5
ControlSt6
ControlSt7
ControlSt8
0
1
2
3
4
1
op Decoder
st Decoder
0
1
2
3
4
1
fn
/6
13
14
15
5
bltzInst
jInst
jalInst
beqInst
bneInst
8
addiInst
andiInst
10
sltiInst
12
13
14
15
andiInst
oriInst
xoriInst
luiInst
35
lwInst
43
63
Fig. 14.5
/6
RtypeInst
0
jrInst
8
fn Decoder
st
12
syscallInst
32
addInst
34
subInst
36
37
38
39
andInst
orInst
xorInst
norInst
42
sltInst
swInst
63
State and instruction decoders for multicycle MicroMIPS.
Computer Architecture, Data Path and Control
Slide 23
Control Signal Generation
Certain control signals depend only on the control state
ALUSrcX = ControlSt2 ControlSt5 ControlSt7
RegWrite = ControlSt4 ControlSt8
Auxiliary signals identifying instruction classes
addsubInst = addInst subInst addiInst
logicInst = andInst orInst xorInst norInst andiInst oriInst xoriInst
Logic expressions for ALU control signals
AddSub = ControlSt5 (ControlSt7 subInst)
FnClass1 = ControlSt7 addsubInst logicInst
FnClass0 = ControlSt7 (logicInst sltInst sltiInst)
LogicFn1 = ControlSt7 (xorInst xoriInst norInst)
LogicFn0 = ControlSt7 (orInst oriInst norInst)
Computer Architecture, Data Path and Control
Slide 24
14.4 Performance of the Multicycle Design
R-type
Load
Store
Branch
Jump
44%
24%
12%
18%
2%
4 cycles
5 cycles
4 cycles
3 cycles
3 cycles
Contribution to CPI
R-type
0.444 = 1.76
Load
0.245 = 1.20
Store
0.124 = 0.48
Branch 0.183 = 0.54
Jump
0.023 = 0.06
ALU-type
P
C
Load
P
C
Store
P
C
Branch
P
C
(and jr)
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
Not
used
_____________________________
Average CPI 4.04
Jump
(except
jr & jal)
P
C
Not
used
Fig. 13.6 The MicroMIPS data path unfolded (by depicting the register write
step as a separate block) so as to better visualize the critical-path latencies.
Computer Architecture, Data Path and Control
Slide 25
14.5 Microprogramming
PC
control
Cache
control
JumpAddr
PCSrc
PCWrite
InstData
MemRead
MemWrite
IRWrite
Fig. 14.6
Register
control
ALU
inputs
ALU Sequence
function control
FnType
LogicFn
AddSub
ALUSrcY
ALUSrcX
RegInSrc
RegDst
RegWrite
Possible 22-bit microinstruction format for MicroMIPS.
Computer Architecture, Data Path and Control
Slide 26
fetch: -------------
Control Unit for
Microprogramming
Dispatch
table 1
Dispatch
table 2
0
0
1
2
3
Multiway
branch
MicroPC
1
Address
andi: ---------
Microprogram
memory or PLA
Incr
Data
Microinstruction register
op (from
instruction
register)
Fig. 14.7
Control signals to data path
Sequence
control
Microprogrammed control unit for MicroMIPS .
Computer Architecture, Data Path and Control
Slide 27
Microinstruction symbolic names
Computer Architecture, Data Path and Control
Slide 28
fetch:
Microprogram
for MicroMIPS
Fig. 14.8
The complete
MicroMIPS
microprogram.
PCnext, CacheFetch, PC+4
PC + 4imm, mPCdisp1
lui1:
lui(imm)
rt z, mPCfetch
add1:
x + y
rd z, mPCfetch
sub1:
x - y
rd z, mPCfetch
slt1:
x - y
rd z, mPCfetch
addi1:
x + imm
rt z, mPCfetch
slti1:
x - imm
rt z, mPCfetch
and1:
x y
rd z, mPCfetch
or1:
x y
rd z, mPCfetch
xor1:
x y
rd z, mPCfetch
nor1:
x y
rd z, mPCfetch
andi1:
x imm
rt z, mPCfetch
ori1:
x imm
rt z, mPCfetch
xori:
x imm
rt z, mPCfetch
lwsw1:
x + imm, mPCdisp2
lw2:
CacheLoad
rt Data, mPCfetch
sw2:
CacheStore, mPCfetch
j1:
PCjump, mPCfetch
jr1:
PCjreg, mPCfetch
branch1: PCbranch, mPCfetch
jal1:
PCjump, $31PC, mPCfetch
syscall1:PCsyscall, mPCfetch
Computer Architecture, Data Path and Control
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State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
State
0 (start)
1
7lui
8lui
7add
8add
7sub
8sub
7slt
8slt
7addi
8addi
7slti
8slti
7and
8and
7or
8or
7xor
8xor
7nor
8nor
7andi
8andi
7ori
8ori
7xori
8xori
2
3
4
6
5j
5jr
5branch
5jal
5syscall
Slide 29
14.6 Exception Handling
Exceptions and interrupts alter the normal program flow
Examples of exceptions (things that can go wrong):
ALU operation leads to overflow (incorrect result is obtained)
Opcode field holds a pattern not representing a legal operation
Cache error-code checker deems an accessed word invalid
Sensor signals a hazardous condition (e.g., overheating)
Exception handler is an OS program that takes care of the problem
Derives correct result of overflowing computation, if possible
Invalid operation may be a software-implemented instruction
Interrupts are similar, but usually have external causes (e.g., I/O)
Computer Architecture, Data Path and Control
Slide 30
Exception
Control
States
Cycle 1
Cycle 2
Jump/
Branch
Cycle 3
Cycle 4
State 5
ALUSrcX = 1
ALUSrcY = 1
ALUFunc = ‘’
JumpAddr = %
PCSrc = @
PCWrite = #
State 6
Cycle 5
InstData = 1
MemWrite = 1
sw
State 0
InstData = 0
MemRead = 1
IRWrite = 1
ALUSrcX = 0
ALUSrcY = 0
ALUFunc = ‘+’
PCSrc = 3
PCWrite = 1
State 1
ALUSrcX = 0
ALUSrcY = 3
ALUFunc = ‘+’
lw/
sw
Start
ALUtype
Illegal
operation
Fig. 14.10
State 2
ALUSrcX = 1
ALUSrcY = 2
ALUFunc = ‘+’
lw
State 3
State 4
InstData = 1
MemRead = 1
RegDst = 0
RegInSrc = 0
RegWrite = 1
State 7
State 8
ALUSrcX = 1
ALUSrcY = 1 or 2
ALUFunc = Varies
RegDst = 0 or 1
RegInSrc = 1
RegWrite = 1
State 10
IntCause = 0
CauseWrite = 1
ALUSrcX = 0
ALUSrcY = 0
ALUFunc = ‘’
EPCWrite = 1
JumpAddr = 1
PCSrc = 0
PCWrite = 1
Overflow
State 9
IntCause = 1
CauseWrite = 1
ALUSrcX = 0
ALUSrcY = 0
ALUFunc = ‘’
EPCWrite = 1
JumpAddr = 1
PCSrc = 0
PCWrite = 1
Exception states 9 and 10 added to the control state machine.
Computer Architecture, Data Path and Control
Slide 31