Transcript Slide 1

Verilog HDL
ECE 4680
Computer Architecture
Verilog Presentation I.
Outline
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What is Verilog?
Basic HDL Concepts
Verilog Language Rules and Syntax
Behavioral and Structural Models
Control Statement
Test Methodology
Examples
HDL
-Hardware Design Languages
A Hardware Description Language is a language used
to describe a digital system, for example, a computer or a
component of a computer. One may describe a digital system
at several levels.
Example:
Switch level: wires, resistors and transistors
Gate level: logical gates and flip flops
Register Transfer Level (RTL): registers and the transfers of
information between registers.
Today Two Major HDLs in Industry
· VHDL
· Verilog HDL
First Verilog Example –
An AND Gate
In1
out
in2
module and (out, in1, in2);
input
in1, in2;
output
out;
assign out = in1 & in2;
endmodule
Verilog HDL vs. VHDL
VHDL Verses Verilog HDL
VHDL (“V” short for VHSIC)
[Very High Speed Integrated Circuits]
• Designed for and sponsored by US Department of Defense.
• Designed by committee (1981- 1985).
• Syntax based on Ada programming language.
• VHDL was made an IEEE Standard in 1987
Verilog HDL
• Verilog was introduced in 1985 by Gateway Design System Corporation,
now a part of Cadence Design Systems, Inc.'s Systems Division.
•Verilog was made an IEEE Standard in 1995
•Syntax based on C programming language.
Design Methodology
Structure and Function
(Behavior) of a Design
HDL
Specification
Simulation
Synthesis
Verification: Design
Behave as Required?
Functional: I/O Behavior
Register-Level (Architectural)
Logic-Level (Gates)
Transistor-Level (Electrical)
Timing: Waveform Behavior
Generation: Map
Specification to
Implementation
Verilog Identifiers
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An identifier (name) in Verilog is composed of a space-free
sequence of uppercase and lowercase letters from
alphabet, the digits(0,1,….9), the underscore( _ ) and the $
symbol.
Verilog is a case sensitive language.
e.g. c_out_bar or C_OUT_BAR
Verilog treats these as different names.
The name of a variable may not begin with a digit or $, and
may up to 1,024 characters long.
e.g. clock_, state_3
Verilog Statement Terminator
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Verilog models consist of a list of statements declaring
relationships between a model and its environment, and
between signals within a model.
E.g. module and endmodule
Statements are terminated by a semicolon( ; )
module full_addr (A, B, Cin, S, Cout);
input
A, B, Cin;
output
S, Cout;
assign {Cout, S} = A + B + Cin;
endmodule
Verilog comments
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There are two kinds of comments:
Single line and multiline
A single-line comment begins with two forward slashes(//)
A multiline comment begins with the pair of characters /* and
terminate with the characters */
e.g.
// This is a single-line comments
/* This is a multiline comments
more comments here
………………………………….
*/
Verilog Numbers
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Numbers are stores as binary words in the host machine.
<size><base format><number> form where
<size> is the size of the constant in the number of bits,
<base format> is the single character ' followed by one
of the following characters b, d, o and h. There are four
base specifiers: binary(b or B), decimal(d or D), hexadecimal (h or H),
and octal(o or O).
<number> contains unsigned digits. Sized Numbers : can be sized to a
specified word length
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12’b0000_0100_0110 - binary number with 12 bits (_ is ignored)
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12’h046
- hexadecimal number with 12 bits
Unsized Numbers
If a number is given without a size, it will be stored in a word having a
length of at least 32 bits.
e.g. ‘HAA is stored having a word length of 32 bits as
0000_0000_0000_0000_0000_0000_1010_1010.
A number without a base will be interpreted as a decimal value
Verilog Operators I
Verilog Operators II
Verilog Value Logic System
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Data type for signals
Bits - value on a wire
 0, 1
 X
- unknow value
 Z
- a high impedance value, tri-state buffer
Vectors of bits
 A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0]
 Concatenating bits/vectors into a vector
 B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};
 B[7:0] = {3{A[3]}, A[3:0]};
Verilog Data Types- Constants
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Two kinds of data in Verilog:
Constant and Variables
Constant: is declared with the keyword parameter in a
statement assigning a name and a value to the constant
The value of a constant is fixed during simulation.
e.g. parameter HIGH_INDEX= 31;
parameter BYTE_SIZE=8;
// integer
Verilog Data Types -Variables
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Two basic families of data types for variables
Nets and Registers
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Net variables – e.g. wire
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Variable used simply to connect components together
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Usually corresponds to a wire in the circuit, like wires in a physical
circuit and establish connectivity between modules
Register variables – e.g. Reg
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Variable used to store data as part of a behavioral description
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Like variables in ordinary procedural languages
Notes:
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Reg should only be used with always blocks (sequential logic, to
be presented …)
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The reg variables store the last value that was procedurally
assigned to them whereas the wire variables represent
physical connections between structural entities such as gates.
Verilog Continuous Assignment
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A continuous assignment statement is declared with the
keyword assign, followed by a net(e.g. type wire) variable, an
assignment operator(=), and an expression.
assign corresponds to a connection or a simple component with
the described function
Target is NEVER a reg variable
use of Boolean operators
assign A = X | (Y & ~Z);
assign B[3:0] = 4'b01XX;
assign C[15:0] = 16'h00ff;
(~ for bit-wise, ! for logical negation)
bits can take on four values
(0, 1, X, Z)
variables can be n-bits wide
(MSB:LSB)
assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;
multiple assignment (concatenation)
use of arithmetic operator
delay of performing computation, only used by simulator, not synthesis
Procedural Assignment & String
• Procedural assignments have the form
<reg variable> = <expression>
where the <reg variable> must be a register or
memory.
e.g. reg enable, d;
#1 enable = 0;16
#1 d = 0;
• String is a sequence of characters enclosed in “”
quotes,
e.g., “digital”, “I am a student of ECE4680 class”
Program Structure: Modules
Any digital system is a set of modules.
The modules may run concurrently, but usually there is one top
level module to specify a closed system containing both test data
and hardware models.The top level module invokes instances of
other modules.
A module is never called, is instantiated.
Modules can be specified behaviorally or structurally (or a
combination of the two).
A behavioral specification defines the behavior of a digital
system using traditional programming language constructs,
e. g., if else, assignment statements.
A structural specification expresses the behavior of a
digital system (module) as a hierarchical interconnection of
sub modules.
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Simple Behavioral Model
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Combinational logic
 Describe output as a function of inputs
 Note use of assign keyword: continuous assignment
module and_gate (out, in1, in2);
input
in1, in2;
output
out;
assign out = in1 & in2;
endmodule
The structure of a module
The structure of a module is the following:
module <module name> (<port list>);
<declares>
<module items>
endmodule
Where
<module name> is an identifier that uniquely names the module.
<port list> is a list of input, output and inout ports which are
used to connect to other modules.
<declares> specifies data objects as registers, memories & wires
as wells as procedural constructs such as functions & tasks.
<module items> may be initial constructs, always constructs,
continuous assignments or instances of modules.
Verilog Module Example 1-bit Adder
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Corresponds to a circuit component
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“Parameter list” is the list of external connections, “ports”
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Ports are declared “input”, “output” or “inout”
 inout ports used on tri-state buses
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Port declarations imply that the variables are wires
module name
ports
module full_addr (A, B, Cin, S, Cout);
input
A, B, Cin;
output
S, Cout;
assign {Cout, S} = A + B + Cin;
endmodule
declares
module item
Mixed Structural/Behavioral Model
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Example 4-bit ripple adder
module full_addr (S, Cout, A, B, Cin );
input
A, B, Cin;
output
S, Cout;
Behavior
assign {Cout, S} = A + B + Cin;
endmodule
module adder4 (S, Cout, A, B, Cin);
input [3:0] A, B;
input
Cin;
output [3:0] S;
output
Cout;
wire
C1, C2, C3;
full_addr
full_addr
full_addr
full_addr
endmodule
fa0
fa1
fa2
fa3
(S[0],
(S[1],
(S[2],
(S[3],
C1,
C2,
C3,
Cout,
A[0],
A[1],
A[2],
A[3],
B[0],
B[1],
B[2],
B[3],
Cin);
C1);
C2);
C3);
Structural
Behavioral Model of a NAND gate
// Behavioral Model of a NAND gate
module NAND(inp1, inp2, out);
input inp1, inp2;
output out; // inp1, inp2 and out are labels on wires.
// continuous assign statement
assign out = ~(inp1 & inp2);
endmodule
Structural Model of a AND gate
/*Structural specification of a module AND using NAND
gates*/
module AND(in1, in2, out);
input in1, in2;
output out;
wire w1;
NAND NAND1(in1, in2, w1); // instantiation of the
NAND NAND2(w1, w1, out); // module NAND
Endmodule
1-bit Comparator Example
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module Comparator1 (A, B, Equal, Alarger, Blarger);
input
A, B;
output
Equal, Alarger, Blarger;
assign Equal = (A & B) | (~A & ~B);
assign Alarger = (A & ~B);
assign Blarger = (~A & B);
endmodule
A
B
Equal
L1
Alarger
L2
Blarger
L3
4-bit Comparator Example
// Make a 4-bit comparator from 4 1-bit comparators
module Compare4(A4, B4, Equal, Alarger, Blarger);
input [3:0] A4, B4;
output Equal, Alarger, Blarger;
wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2,
Bl3;
Compare1 cp0(A4[0], B4[0], e0, Al0, Bl0);
Compare1 cp1(A4[1], B4[1], e1, Al1, Bl1);
Compare1 cp2(A4[2], B4[2], e2, Al2, Bl2);
Compare1 cp3(A4[3], B4[3], e3, Al3, Bl3);
assign Equal = (e0 & e1 & e2 & e3);
assign Alarger = (Al3 | (Al2 & e3) |
(Al1 & e3 & e2) |
(Al0 & e3 & e2 & e1));
assign Blarger = (~Alarger & ~Equal);
endmodule
Procedural Blocks
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There are two types of procedural blocks in Verilog
initial - single-pass behavior : initial blocks execute
only once at time zero (start execution at time zero).
always - cyclic behavior : always blocks loop to
execute over and over again, in other words as name
means, it executes always.
Procedural assignment may only appear in initial and
always constructs.
The initial and always constructs are used to model
sequential logic.
Continuous statement is used to model combinational
logic.
Example - initial
module initial_example();
2 reg clk,reset,enable,data;34
initial begin5
clk = 0;6
reset = 0;7
enable = 0;8
data = 0;9
end1011\
endmodule
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In the above example, the initial block execution at time 0.
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Initial block without waiting just executed all the statements
within begin and end statement.
Example - always
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module always_example();2
reg clk,reset,enable,q_in,data;34
always @ (posedge clk)5
begin
if (reset) begin6
data <= 0;7
end
else if (enable)
begin 8
data <= q_in;9
end
end11
endmodule
In always block, when the trigger event occurs, the code inside begin
and end is executed and the once again the always block waits for next
posedge of clock. This process of waiting and executing on event is
repeated till simulation stops.
Control Constructs
• Control Constructs
Can be used in the procedural sections of code.
• Selection - if and case Statements
if (A == 4)
begin
B = 2;
end
else
begin
B = 4;
end
case (<expression>)
<value1>: <statement>
<value2>: <statement>
default: <statement>
endcase
Verilog Control Statement – if I.
• Same as C if statement
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel;
// 2-bit control signal
input A, B, C, D;
output Y;
reg Y;
// target of assignment
always @(sel or A or B or C or D)
if (sel == 2’b00) Y = A;
else if (sel == 2’b01) Y = B;
else if (sel == 2’b10) Y = C;
else if (sel == 2’b11) Y = D;
endmodule
Verilog Control Statement – if II.
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel;
// 2-bit control signal
input A, B, C, D;
output Y;
reg Y;
// target of assignment
always @(sel or A or
if (sel[0] == 0)
if (sel[1] == 0)
else
else
if (sel[1] == 0)
else
endmodule
B or C or D)
Y = A;
Y = B;
Y = C;
Y = D;
Verilog case-Simple 4-1 mux
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Sequential execution of cases
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Only first case that matches is executed
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Default case can be used
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel;
// 2-bit control signal
input A, B, C, D;
output Y;
reg Y;
// target of assignment
always @(sel
case (sel)
2’b00: Y
2’b01: Y
2’b10: Y
2’b11: Y
endcase
endmodule
or A or B or C or D)
=
=
=
=
A;
B;
C;
D;
Conditions tested in
top to bottom order
Verilog case-Simple
Binary Encoder
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Without the default case, this example would create a latch for Y
Assigning X to a variable means synthesis is free to assign any value
module encode (A, Y);
input [7:0] A;
// 8-bit input vector
output [2:0] Y;
// 3-bit encoded output
reg
// target of assignment
[2:0] Y;
always @(A)
case (A)
8’b00000001: Y = 0;
8’b00000010: Y = 1;
8’b00000100: Y = 2;
8’b00001000: Y = 3;
8’b00010000: Y = 4;
8’b00100000: Y = 5;
8’b01000000: Y = 6;
8’b10000000: Y = 7;
default:
endcase
endmodule
Y = 3’bX;
// Don’t care when input is not 1-hot
Verilog case – Decoder
module decoder_using_case (8binary_in , decoder_out , enable);12
input [3:0] binary_in ;13 // 4 bit binary input
input enable ;14
// Enable for the decoder11
output [15:0] decoder_out ; // 16-bit out1516
reg [15:0] decoder_out ;1718
always @ (enable or binary_in)1
9begin20
decoder_out = 0;21
if (enable)
begin22
case (binary_in)23
4'h0 : decoder_out = 16'h0001;24
4'h1 : decoder_out = 16'h0002;25
4'h2 : decoder_out = 16'h0004;26
4'h3 : decoder_out = 16'h0008;27
4'h4 : decoder_out = 16'h0010;28
4'h5 : decoder_out = 16'h0020;29
4'h6 : decoder_out = 16'h0040;30
4'h7 : decoder_out = 16'h0080;31
4'h8 : decoder_out = 16'h0100;32
4'h9 : decoder_out = 16'h0200;33
4'hA : decoder_out = 16'h0400;34
4'hB : decoder_out = 16'h0800;35
4'hC : decoder_out = 16'h1000;36
4'hD : decoder_out = 16'h2000;37
4'hE : decoder_out = 16'h4000;38
4'hF : decoder_out = 16'h8000;39
endcase40
End41
End424
3endmodule
Repetition - for, while and repeat Statements
for(i = 0; i < 10; i = i + 1) // for loop
begin
$display("I = %0d", i);
end
i = 0; //while statement acts in the normal fashion.
while(i < 10)
begin
$display("I = %0d", i);
i = i + 1;
end
repeat (5) //repeats the block 5 times,
begin
$display("I = %0d", i);
i = i + 1;
end
Test Methodology
•A circuit must be tested and verified systematically to
ensure that all of its logic has been exercised and
found to be functionally correct.
•A testbench is a separate Verilog module, which
contains a stimulus generator, a response monitor and
an instantiation of the unit under test.
Stimulus Generator
Unit Under Test
Response Monitor
•During simulation, the response monitor selectively
gathers data on signals and displays them in a text or
graphical format.
Testbench Example
module test_AND ();
reg a, b;
wire out1, out2;
initial begin
a = 0; b = 0;
#1 a = 1;
#1 b = 1;
#1 a = 0;
end
initial begin
//module to test the two other modules
// Test data
// Set up monitoring
$monitor("Time=%0d a=%b b=%b out1=%b out2=%b", $time, a, b, out1, out2);
end
// Instances of modules AND and NAND
NAND gate2(a, b, out1);
AND gate1(a, b, out2);
endmodule
Testbench Result
// output for program above
Time=0 a=0 b=0 out1=1 out2=0
Time=1 a=1 b=0 out1=1 out2=0
Time=2 a=1 b=1 out1=0 out2=1
Time=3 a=0 b=1 out1=1 out2=0
Note: $display is used for printing text or variables to stdout (screen),
Syntax is same as printf.
$monitor is bit different, $monitor keeps track of changes to the variables
that are in the list ($time, a, b, out1, out2). When ever anyone of them changes,
it prints their value, in the respective radix specified.
Blocking and Non-blocking
Procedural Assignments
• The
blocking assignment statement (= operator) acts much
like in traditional programming languages.
Blocking statement must complete execute before the next
statement in the behavior can execute.
•The non-blocking (<= operator) evaluates all the right-hand
sides for the current time unit and assigns the left-hand sides
at the end of the time unit.
Non-blocking assignment statements execute concurrently
rather than sequentially.
Testing blocking & non-blocking
assignment module blocking
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;
$display("Blocking: A= %b B= %b", A, B );
A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule
Output is :
Blocking: A= 00000100 B= 00000101
Non-blocking: A= 00000100 B= 00000100
Structural Model - XOR
module xor_gate ( out, a, b );
input
a, b;
output
out;
wire
abar, bbar, t1, t2;
inverter
inverter
and_gate
and_gate
or_gate
invA (abar, a);
invB (bbar, b);
and1 (t1, a, bbar);
and2 (t2, b, abar);
or1 (out, t1, t2);
A
invA
B
invB
endmodule
By default, identifiers are wires
and
1
and
2
t1
or1
t2
out
2-to-1 MUX Behavioral Description
//Does not assume that we have
// defined a 4-input mux.
//4-input mux behavioral description
module mux4 (in0, in1, in2, in3, select, out);
input in0,in1,in2,in3;
input [1:0] select;
output
out;
reg
out;
always @ (in0 in1
case (select)
2’b00:
2’b01:
2’b10:
2’b11:
endcase
endmodule // mux4
in2 in3 select)
out=in0;
out=in1;
out=in2;
out=in3;
Structural Model: 2-to1 MUX
//2-input multiplexor in gates
module mux2 (in0, in1, select, out);
input in0,in1,select;
output out;
wire s0,w0,w1;
not (s0, select);
and (w0, s0, in0),
(w1, select, in1);
or (out, w0, w1);
endmodule // mux2
D Flip-Flop
// D flip-flop Code
module d_ff ( d, clk, q, q_bar);
input d ,clk;
output q, q_bar;
wire d ,clk;
reg q, q_bar;
always @ (posedge clk)
begin
q <= d;1
q_bar <= !d;
End
endmodule

d
q
DFF
q_bar
clk
8-Bit Simple Up Counter
Using D Flip-Flop
module up_counter ( out, enable, clk, reset);
output [7:0] out;
input enable, clk, reset;
reg [7:0] out; //------------Internal Variables-------//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end
else if (enable) begin
out <= out + 1;
end
endmodule
Final thoughts
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Verilog looks like C, but it describes hardware
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Multiple physical elements, Parallel activities
Temporal relationships
Basis for simulation and synthesis
figure out the circuit you want, then figure out
how to express it in Verilog
Understand the elements of the language
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Modules, ports, wires, reg, primitive, continuous
assignment, blocking statements, sensitivity lists,
hierarchy
Best done through experience
References
1. Cadence Design Systems, Inc., Verilog-XL Reference Manual.
2. Ciletti, Michael D., Starting Guides to Verilog 2001, Prentice Hall 2004
3. World Wide Web Pages:
http://www.eg.bucknell.edu/~cs320/Fall2003/verilog.html
http://www.verilog.net/index.html
http://www.eecs.berkeley.edu/~culler
http://www-inst.eecs.berkeley.edu/~cs150