Transcript Cacac

Where is CERN?
Lake Geneva
Geneve
The
Alps
17-Jul-15
Drew Baden
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Angels and Demons?
• CERN’s very own X-33 space plane!
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LHC
• 27km proton-proton ring at CERN
• Reuse the tunnel previously home for the LEP collider
• Dig new collision areas for new experiments
– ATLAS & CMS
• All high pT physics, hermetic,
large, general purpose
– LHCb & Alice
• Smaller in size and physics scope
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LHC Layout
• 8 arcs + 8 straight
sections
CMS
– 4 intersections have
experiments
RF & beam
instrumentation
Beam
dump
• CMS, Atlas, Alice,
LHCb
– 4 have
instrumentation,
beam dump, beam
focusing, etc
Betatron
“cleaning”
Momentum
“cleaning”
Alice
LHCb
Atlas
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Injection
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LHC/LEP Tunnel
• 27km long bored deep
underground tunnel
– Boring is more stable than
cut/fill or blasted tunnels
– 3km are actually under the Jura
mountains
• Diameter 4 - 6m
• Depth 50 - 175m depending
on location
• 1.4 x 106 m3 ~ (100m)3 soil
extracted to dig it
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LHC (cont)
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LHC Progress
……
27Installation
km of dipoles…whew!
in progress…
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LHC Stats
• Ebeam = 7 TeV, 2 countercirculating proton beams
• Bunched beam structure
– Crossing every 25ns
– Number of bunches 3654
– 1.1x1011 particles/bunch
• DC beam current .56Amps
• Stored beam energy 350 MJoules
– Equivalent to ~100 kW-hrs Superconducting NbTi magnets @ 1.9K
– Dipole field 8.33T @ 7 TeV full beam energy
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CMS (cont)
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TriDAS Overview
• CMS Trigger: Emphasis is on bandwidth and commercial processors
• Level 1
– 3 ms latency inside L1 trigger
– 100 kHz average L1 accept rate (1/400)
– 100 Gbyte/sec into Level 2
Baden is HCAL “Level 3 WBS Manager” for TriDAS
“Front End”
CMS
HCAL
HCAL
Data
Trigger/DAQ
QIE
Fibers
Level 2/3
DAQ
Level 1
Trigger
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HCAL Electronics Overview
S-Link: 64 bits @ 25 MHz
Trigger Primitives
S
B
S
Rack CPU
Level 1
TRIGGER
C
L
K
D
C
C
H
T
R
H
T
R
H
T
R
READ-OUT Crate
• 1 PC Interface
•12 HTRs
• 1 Clk board
• 2 DCC
TTC
FRONT-END
Readout Box
CERN
Transmitter
40 bits
@40 MHz
HPD
QIE
QIE
QIE
(RBX)
On detector
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QIE
CCA
QIE
Shield
Wall
GOL
CCA
analog optical
signals from
HCAL
CCA
QIE
20 bits
@ 80 MHz
=1.6 Gbps
FIBERS
GOL
FE MODULE
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HTR Principal Functions
1. Receive HCAL data from front-ends
•
•
•
•
Synchronize optical links
Data validation and linearization
Form “trigger primitives” and transmit to Level 1 at 40 MHz
Pipeline data, wait for Level 1 accept
– Upon receiving L1A:
»
»
»
Zero suppress, format, & transmit raw data to the concentrator (no filtering)
Transmit all trigger primitives along with raw data
Handle DAQ synchronization issues (if any)
2. Calibration processing and buffering of:
•
•
Radioactive source calibration data
Laser/LED calibration data
3. Support a VME data spy monitoring
• Data: total of approximately 650 TB/sec flowing through our
boards!!!
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HCAL Trigger/Readout (HTR) Board
Fiber Data
Serial Optical Data
LC
CLK80
TTC
RX_BC0
RX_CLK40
Crystal
FPGA logic
20
PLL
x2
SLB
TTC Broadcast
SLB
Async Fifo
SYS40 Clk
Fiber digital data
Copper output to L1 and
DCC
Recovered
Clk
TTCrx
TTC 40 Clk
All I/O on front panel
Ref
Clk
SYS80 Clk
Princeton
Fanout Card
(1/VME crate)
Deserializers (8)
SLB
Fully programmable
TPG
Path
SLB
XILINX
SLB
SLB
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HTR Card Production Version (Rev 4)
Dual-LC O-to-E
Stiffeners
VME
TTC mezzanine
Deserializers
6 SLBs
Xilinx XC2V3000-4
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Firmware
•
DAQ format evolving
–
Maryland/Boston/Princeton collaboration
•
Top-level view:
•
See http://cmsdoc.cern.ch/cms/HCAL/document/CountingHouse/HTR/design/Rev4MainFPGA.pdf
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LHC Clocking
• LEP ring is sensitive to:
– Distortions in the large (27 km) circumference
• Tidal distortions
• Pressure from Lake Geneva
Train to Bellgarde EFFECT
– Return currents from DC trains running nearby
• LHC RF clock keeps 3564 buckets of protons circulating
– CMS must remain synchronous with this clock
– LEP was concerned about DE~few MeV, LHC will be
concerned with Df ~ 25 ppm
• We have learned to handle this…
TIDAL EFFECTS
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LAKE Geneva EFFECTS
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Timing Signal Distribution
Trigger Timing Control
TTC Stream
(“RX_CLK”)
Rack-to-Rack CAT 7
F
A
H H H H D
N
T T T T C
O
R R R R C
U
T
F
A
N
O
U
T
F
A
H H H H D
N
T T T T C
O
R R R R C
U
T
HCAL VME Crates
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F
A
N
O
U
T
F
A
N
O
U
T
ECAL
Timing is critical in a synchronous pipeline experiment!
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Fanout board
2 operating modes: Global or Crate
TTC Broadcast
TTC fiber
TTCrx
40MHz
QPLL can run
stand-alone
G
Clk80
C
G
QPLL
18 Outputs
G
RX_CLK = 40MHz
C
G
INT_BC0
RX_BC0
C EXT_BC0
FPGA
Delay
RX_CLK = 40MHz
Input from
GLOBAL Fanout
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RX_BC0
EXT 80MHz
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Overall TriDAS Project Cost
• Contingency:
– Effort: 50%
– M&S: 75%
– Based on the
uncertainty in the
requirements,
which will certainly
change over time.
Item
Effort:
Engineering
$802,669
Technician
$138,684
Total
M&S:
$941,353
R&D
$ 218,100
Production
$1,929,374
Total
Misc:
$2,147,474
$45,000
Grand Total
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Cost
Drew Baden
$3,133,827
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