Transcript ITRS Update

Winter Public Conference
ORTC 2010 Update
A. Allan, Rev 2, 12/02/10
1
IRC 2010 Update Messages:
 450mm timing presently unchanged from 2009 ITRS position
 However, FI will extend 300mm wafer generation in parallel line item header with 450mm; and
 Emphasize compatibility of productivity extensions into the 450mm generation;
 FI update also indicates that its activities are relevant to legacy wafer generations (e.g. MtM
technologies)
 More than Moore white paper final ITWG draft is completed and available online
 New “Moore’s Law and More” Graphic update proposal for the 2011 ITRS Executive
Summary Renewal
 The 2010 ITWG work is based on frozen 2009 Headers

Technology Pacing focus issues identified and addressed (see Technology Pacing agenda Foil)
 Beyond CMOS –
 Research tools and material (pre-alpha material and tool) timing needs to be taken into
account
 PIDS and ERD and ERM are coordinating new technology transfers (e.g. InGaAs; Ge)
for 2011 ITRS work Kickoff proposals
 ESH shifting focus to future material use and risk mitigation (living “white paper” proposed) on
ITRS forum site
 IRC 2010 Summary special topics
 Energy topic Updated
 ERD/ERM Next Memory Storage Spring Meeting completed 3rd conference in Japan at
Winter meeting
 Technology Pacing CTSG proposals are integrated into PIDS Tables and ORTC
Table1 at Dec’10 Japan Workshop for the 2011 ITRS Executive Summary Renewal
 Equivalent scaling graphic update for the 2011 ITRS Executive Summary Renewal
 Parallel bulk and SOI pathways
 Clarification of gate mobility materials pathway
 Comparison alignment with ITRS dimensional vs. industry typical “node” trends
2
IRC/CTSG Winter 2010
Technology Pacing Cross-TWG Study Group (CTSG) Agenda:
IRC/Technology Pacing CTSG TOPICS - CTSG 2010 Proposals considered
During Winter Meeting 2011 Renewal work from 2H10 CTSG Discussions:
– PIDS and FEP Memory Survey Proposal Updates - to be used for 2011
Renewal
– FEP and Design and System Drivers – will investigate MPU and Leading Edge
Logic technology trend proposals for 2011 Renewal
Plus Continued 1Q11 CTSG 2011 Renewal work on:
– Litho – develop proposals utilizing # of Mask layers inputs [see ICKnowledge
(ICK) contribution in backup]
– Design/Interconnect - Andrew/Juan-Antonio/Chris Case - reconciled the
Interconnect and Design Tables alignment issues
– A&P/Design - Bill Bottoms/Andrew/Juan-Antonio – work on proposals for
reconciling the Power Dissipation (absolute "hot spot" basis rather than total
chip area for 2011 Renewal
– PIDS/Design – work on 2011 Renewal proposals for
• New Max Chip Frequency trends (lower model basis plus long term trend)
• Changes to the 13% PIDS Overhead trend vs. new Design Max Chip Frequency
trends;
• Updates regarding ring-oscillator basis;
• Timing changes to “equivalent scaling” tradeoffs with dimensional scaling
– ORTC model update proposals added from work in 2H10 CTSG work for 2011
Renewal
3
2010 ITRS Summary Figure 4
Figure 4 The Concept of Moore’s Law and More
More than Moore: Diversification
Baseline CMOS: CPU, Memory, Logic
More Moore: Miniaturization
Analog/RF
Passives
HV
Power
Sensors
Actuators
Biochips
130nm
Interacting with people and environment
90nm
Non-digital content
System-in-package
(SiP)
65nm
45nm
32nm
22nm
Information
Processing
Digital content
System-on-chip
(SoC)
16 nm
.
.
.
V
Beyond CMOS
4
2010- Update Flash Poly Definition
2009 Definition of the Half Pitch – New Poly Definition
[No single-product “node” designation; DRAM half-pitch still litho driver; however,
other product technology trends may be drivers on individual TWG tables]
FLASH Poly Silicon ½ Pitch
= Flash Poly Pitch/2
Poly
Pitch
DRAM ½ Pitch
= DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch
= MPU/ASIC M1 Pitch/2
Metal
Pitch
8-16 Lines 32-64 Lines
Typical flash
Un-contacted Poly
Source: 2009 ITRS - Exec. Summary Fig 1
Typical DRAM/MPU/ASIC
Metal Bit Line
5
2010 ITRS Summary Figure 3 “Equivalent Scaling” Roadmap
Figure 3 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes”
and ITRS trends for comparison)
Gate-stack
material
Metal
Metal
Metal
High k
High k
High k
2nd generation
Channel
material
nth generation
D
S
Updated Proposal
- for 2011 work
[from 11/11 CTSG;
11/15 IRC telecon]
D
S
High-µ
InGaAs; Ge; ?
Si + Stress
Possible
Pull -in
Bulk
Multi-gate
(on bulk or SOI)
Structure
(electrostatic
control)
Possible
Delay
PDSOI
2009 ITWG Table Timing:
2009
2009 IS ITRS DRAM M1 :
2007
54nm 45nm
68nm
MPU/hpASIC “Node”:
“45nm”
“32nm”
2009 IS ITRS Flash Poly :
FDSOI
2010
32nm
45nm
2012
“22nm”
2013
22nm
32nm
2015
“16nm”
2016
16nm
22nm
2018
2019
11nm
16nm
“11nm”
“8nm”
2009 ITRS MPU/hpASIC M1 :
76nm 65nm 54nm 45nm
38nm
32nm 27nm
19nm
13nm
2009 ITRS hi-perf GLpr :
54nm 47nm
47nm 41nm
35nm
31nm 28nm
20nm
14nm
2009 ITRS hi-perf GLph :
32nm 29nm
29nm 27nm
24nm
22nm 20nm
15nm
12nm
See also PIDS, FEP, ERD, and ERM chapters’ text and tables for additional detail)
2021
2021
6
= Additional timing movement
considerations for 2011 ITRS work
1)
2010 Update ITRS ORTC Technology Trend Pre-Summary
ORTC Model Proposals to TWGs for TWG Interdependency Preparation for other ORTC
section features:
1)
2)
3)
2)
MPU contacted M1
1)
2)
3)
4)
5)
6)
3)
Unchanged for 2010 [validated by FEP data]
2-year cycle trend through 2013
Cross-over DRAM M1 2010/45nm
Smaller 60f2 SRAM 6t cell Design Factor
Smaller 175f2 Logic Gate 4t Design Factor
Two proposals [2011 Renewal work]: for Design TWG to evaluate possible 1-year M1 delay (IC
TWG: two companies not meeting roadmap); and also evaluate alignment of “nodes” with latest
M1 industry status and also High Performance/Low Power timing needs (Taiwan IRC request)
DRAM contacted M1
1)
2)
4)
“Equivalent Scaling” timing unchanged in 2010 for ERD/ERM early research and transfer to PIDS; however
need for continued discussion about transfer of alternative Gate Material technology in 2011 Renewal
Logic “Equivalent Scaling” Roadmap Timing Update underway, and ongoing discussion of alignment of
“node” and dimensional Trends for 2011 Renewal
New “More than Moore” (MtM) white paper completed for 2011 ITRS Renewal impact and added to the ITRS
website at www.itrs.net
Unchanged for 2010: Dimensional M1 half-pitch trends remain unchanged from 2007/08/09 ITRS;
new 4f2 Design factor begins 2011
Proposal [2011 Renewal work]: 1-year pull-in of M1 and bits/chip trends to end of roadmap*; 4f2
push out [to 2013]; *no Flattening of DRAM M1 as with Flash Poly**
Flash Un-contacted Poly
1)
Unchanged for 2010: 2yr cycle trend through 2010/32nm; then 3yr cycle and also added “equivalent
scaling” bit design:
1)
2)
3)
Inserted 3bits/cell MLC 2009-11; and delayed 4bits/cell (2 companies in production) until 2012
Proposal #1[2011 Renewal work]: 1.5-2-year pull-in of Poly; however slower ~4-year cycle trend
to 2015/18nm; then 3-year trend to 2022; ** then Flat Poly after 2022/8nm; and 3bits/cell
extended to 2018; 4bits/cell delay to 2019
Additional Proposal consideration underway for 2011 Renewal due to recent announcements
7
2010 Update ITRS ORTC Technology Trend Pre-Summary (cont.)
5)
6)
Unchanged for 2010 Tables: MPU GLpr – ’08-’09 2-yr flat; Low operating and standby line
items track changes
Unchanged for 2010 Tables: MPU GLph – ’08-’09 2-yr flat with equiv. scaling process
tradeoffs; Low operating and standby line items track changes
1)
7)
Primarily Unchanged [corrections to Intro Level product line items – see backup] for
2010 Tables: MPU Functions/Chip and Chip Size Models
1)
2)
3)
8)
smaller Chip Sizes (<60mm2) with 4f2 design factor included
ORTC model impact updating from PIDS/FEP Survey proposals evaluation underway for 2011
Renewal]
Flash Bits/Chip and Chip Size Model Unchanged for 2010 Tables
1)
2)
3)
10)
Utilized Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing
trends and updated cell design factors
ORTC line item OverHead (OH) area model, includes non-active area
ORTC model impact updating from PIDS/FEP Survey proposals evaluation underway for 2011
Renewal]
DRAM Bits/Chip and Chip Size Model Unchanged for 2010 Tables - 3-year generation
“Moore’s Law” doubling cycle;
1)
2)
9)
Performance targets (speed, power) on track with tradeoffs
2-year generation “Moore’s Law” doubling cycle;
growing Chip Sizes after return to 3-year technology cycle
ORTC model impact updating from PIDS/FEP Survey proposals evaluation underway for 2011
Renewal]
IRC 450mm Position: Pilot lines/2012; Production/2014-16 Unchanged for 2010; also
Unchanged: “double S-curve” graphic in 2010 Update Summary
1)
2)
3)
450mm Program status and Long-Range IEM v12 Demand Update Scenario was presented by
ISMI to IRC for 2011 ITRS Renewal preparation
ISMI is pursuing 450mm program activities to meet the ITRS Timing
Evaluation of possible impact of a delayed scenario is underway for 2011 ITRS Renewal
preparation
8
2010 ITRS Summary Figure 1
Figure 1 ORTC Table 1 with PIDS update proposals for 2011 ITRS effort)
Table ORTC-1 ITRS Technology Trend Targets
[including PIDS 2011 Roadmap Flash and DRAM Trend Driver Proposals]
2009
2010
2011
2012
2013
2014
2015
2016
Flash ½ Pitch (nm) (un-contacted Poly)(f)[A]
38
32
28
25
23
20
18
15.9
Flash ½ Pitch (nm) (un-contacted Poly)(f) [B]
N/A
26
24
22
20
19
18
16
DRAM ½ Pitch (nm) (contacted)[C]
52
45
40
36
32
28
25
22.5
DRAM ½ Pitch (nm) (contacted) [D]
N/A
42
36
31
28
25
24.0
21.0
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2]
54
45
38
32
27
24
21
18.9
MPU Printed Gate Length (GLpr) (nm) ††[1]
47
41
35
31
28
25
22
19.8
MPU Physical Gate Length (GLph) (nm)[1]
29
27
24
22
20
18
17
15.3
ASIC/Low Operating Power Printed Gate Length (nm) ††[1]
54
47
41
35
31
25
22
19.8
ASIC/Low Operating Power Physical Gate Length (nm)[1]
32
29
27
24
22
18
17
15.3
Year of Production
2010 ORTC
2010 PIDS Projection
based on survey data
2010 WAS
2010 PIDS Projection
based on survey data
38
32
29
27
22
18
17
15.3
1.6039
1.5296
1.4588
1.4237
1.3895
1.3561
1.3235
1.2917
2017
2018
2019
2020
2021
2022
2023
2024
2025
14.2
12.6
11.3
10.0
8.9
8.0
7.1
6.3
N/A
14
13
12
11
9
8
8
8
N/A
20.0
17.9
15.9
14.2
12.6
11.3
10.0
8.9
N/A
18.0
16.0
14.0
13.0
12.0
10.0
9.0
8.0
N/A
16.9
15.0
13.4
11.9
10.6
9.5
8.4
7.5
N/A
17.7
15.7
14.0
12.5
11.1
9.9
8.8
7.9
N/A
14.0
12.8
11.7
10.7
9.7
8.9
8.1
7.4
N/A
17.7
15.7
14.0
12.5
11.1
9.9
8.8
7.9
N/A
14.0
12.8
11.7
10.7
9.7
8.9
8.1
7.4
N/A
14.0
12.8
11.7
10.7
9.7
8.9
8.1
7.4
N/A
1.2607
1.2304
1.2008
1.1720
1.1438
1.1163
1.0895
1.0633
N/A
ASIC/Low Standby Power Physical Gate Length (nm)[1]
MPU Etch Ratio GLpr/GLph (nm)[1]
Note: additional proposals for 2011 ITRS work are
under consideration due to recent additional industry
technology implementation acceleration
announcements. Updates will be delivered at public
meetings in 2011.
9
2010 ITRS Summary Figure 2
Figure 2 ORTC Table 1 Graphical Trends (including overlay of PIDS update proposals for 2011 ITRS effort)
2009 ITRS - Technology Trends
1000
2009 ITRS Flash ½ Pitch (nm) (un-contacted
Poly) - [2-yr cycle to 2010; then 3-yr cycle]
2009 ITRS DRAM ½ Pitch (nm) (contacted)
[2.5yr cycle '00-'10, then 3-yr cycle]
Nanometers (1e-9)
100
2013: PIDS DRAM 4f2 Design Factor bits/cell push-out
2019: PIDS Flash 4 bits/cell push-out
16nm
10
PIDS Flash Projection
~2-yr pull-in
26nm Poly half-pitch to 2010 (2 co’s);
Then ~4-yr cycle to 2020/10nm;
Then 3-year cycle to 2022/8nm;Then flat
Near-Term
1
1995
2000
2005
Year of Production
2010
Source: 2009 ITRS - Executive Summary Fig 7a
Memory
PIDS 2011
Proposals
PIDS DRAM Projection
~1-yr pull-in
42nm M1 to 2010 (2 co’s);
Then 3-yr cycle to 2024/8nm;
Long-Term
2015
2020
2025
2009 ITRS: 2009-2024
10
2010 ITRS Summary Figure 5a
Figure 5a DRAM and Flash Memory Half Pitch Trends
2009 ITRS - Technology Trends
1000
2009 ITRS Flash ½ Pitch (nm) (un-contacted
Poly) - [2-yr cycle to 2010; then 3-yr cycle]
2009 ITRS DRAM ½ Pitch (nm) (contacted)
[2.5yr cycle '00-'10, then 3-yr cycle]
Nanometers (1e-9)
100
16nm
10
Near-Term
1
1995
2000
2005
Year of Production
2010
Source: 2009 ITRS - Executive Summary Fig 7a
Long-Term
2015
2020
2025
2009 ITRS: 2009-2024
11
2010 ITRS Summary Figure 5b
Figure 5b MPU/high-performance ASIC Half Pitch and Gate Length Trends
2009 ITRS - Technology Trends
1000
2009 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm)
[historical trailing at 2-yr cycle; extended to 2013;
then 3-yr cycle]
2009 ITRS MPU Printed Gate Length (GLpr) (nm)
[3-yr cycle from 2011/35.3nm]
100
Nanometers (1e-9)
2009 ITRS MPU Physical Gate Length (nm) [begin
3.8-yr cycle from 2009/29.0nm]
16nm
10
Near-Term
1
1995
2000
2005
Year of Production
2010
Long-Term
2015
2020
2025
2009 ITRS: 2009-2024
12
2010 ITRS Summary Figure 6
Figure 6 2009 ITRS Product Function Size Trends:
MPU Logic Gate Size (4-transistor); Memory Cell Size [SRAM (6-transistor); Flash (SLC and MLC),
and DRAM (transistor + capacitor)]
2009 ITRS
- Function
Size
Function
Size
2009 DRAM Cell area per bit (1 bits/cell) (um2)
1.00E+04
1.00E+03
1.00E+02
MPU/ASIC
Alignment
With Latest
Design TWG
Actual SRAM [60f2]
& Logic Gate [175f2]
2009 Flash SLC area per bit (1 bits/cell) [SLC cell area/1] (um2)
2009 Flash MLC Ave area per bit (2 bits/cell) [SLC cell area/2] (um2)
2009 Flash MLC Ave area per bit (3 bits/cell) [SLC cell area/3] (um2)
2009 Flash MLC Ave area per bit (4 bits/cell) [SLC cell area/4] (um2)
2009 SRAM Cell (6-transistor) Area (um2)
2009 Logic Gate (4-transistor) Area (um2)
Square
Millimeters
(um2)
Micrometers
Square
1.00E+01
1.00E+00
1.00E-01
1.00E-02
1.00E-03
DRAM
4f2
Added
Beginning
2011
1.00E-04
1.00E-05
1.00E-06
1995
2000
Flash [4f2]
1) 2-yr Cycle
Extended to 2010;
2) 3 bits/cell added
2009-2011;
3) 4 bits/cell moved
To 2012
2005
Year of Production
2010
2015
2009 ITRS: 2009-2024
2020
2025
13
2010 ITRS Summary Figure 7a
Figure 7a 2009 ITRS Product Technology Trends:
Memory Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends
2009 ITRS - Functions/chip and Chip Size
Flash SLC
1 Tera-bit!
10000.00
Flash
= 2x/2yrs
Gigabits (1e9) and Square Millimeters
1000.00
<143mm2
(22 x 6.5)
100.00
<60mm2
(11 x 5.5)
10.00
1.00
Flash
"Hwang's
Law"
= 2x/1yr
DRAM
= 2x/3yrs
2009 ITRS DRAM Functions per chip (Gbits)
2009 ITRS Flash (Gbits) SLC [2-year cycle]
DRAM
= 2x/2yrs
2009 ITRS Functions per chip (Gbits) MLC (2 bits/cell)
2009 ITRS Functions per chip (Gbits) MLC (3 bits/cell) ADDED
0.10
2009 Functions per chip (Gbits) MLC (4 bits/cell)
Average "Moore's
Law" = 2x/2yrs
2009 Flash Chip size at production (mm2)
2009 DRAM Chip size at production (mm2)
0.01
1995
2000
2005
Year of Production
2010
2015
2020
2009 ITRS: 2009-2024
2025
14
2010 ITRS Summary Figure 7b
Figure 7b 2009 ITRS Product Technology Trends:
MPU Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends
2009 ITRS - Functions/chip and Chip Size
10000000
Million Transistors (1e6) and Square Millimeters
2009 ITRS Cost-Performance MPU Functions
per chip at production (Mtransistorst)
1000000
Average "Moore's
Law" = 2x/2yrs
2009 ITRS High-Performance MPU Functions
per chip at production (Mtransistors)
100000
10000
1000
2009 Cost-Performance MPU Chip size at
production (mm2)
MPU
= 2x/2yrs
MPU
= 2x/3yrs
2009 High-Performance MPU Chip size at
production (mm2)
2011: “22nm”/(38nm M1)
MPU Model Generations
<260mm2
<140mm2
100
10
1995
2000
2005
Year of Production
2010
2015
2020
2025
2009 ITRS: 2009-2024
15
2010 ITRS Summary Figure 8
Figure 8 A Typical Wafer Generation Pilot Line and Production “Ramp” Curve applied to Forecast Timing
Targets of the 450 mm Wafer Generation
Production
Development
Volume
Consortium
Alpha
Tool
Beta
Tool
450mm 32nm M1 half-pitch
Pilot Line Ramp
2011
22nm (extendable
to 16nm) M1 halfpitch capable tools
Tools for
Pilot line
32nm (extendable to 22nm) M1
half-pitch capable Beta tools by
end of 2011
2010
Manufacturing
Pilot Line
2012
Beta Production
Tool
Tool
2013
Years
2014
2015
2016
16
2010 Winter Meeting Public Conference Backup
•
•
•
•
ITRS “S-curves” Ramp Timing definition
ERD/ERM “Beyond CMOS” Definition Graphic
ORTC Table 2D corrections
SICAS Capacity Analysis Graphics 60nm Split-out Analysis
Update
• Typical Industry “Node” Tracking vs ITRS Technology Trends
17
Work in Progress – Do Not Publish!
2009 WAS
2010 Unchanged
Production
Ramp-upModel
Model and
Technology/Cycle
Timing Timing
Production
Ramp-up
and
Technology Cycle
Development
200K
Production
Volume (Wafers/Month)
20K
*Examples: 25Kwspm ~=
4.5Mu/mo @ 280mm2
10Mu/mo @ 140mm2
15Mu/mo @ 100mm2
22mu/mo @ 70mm2
Alpha
Tool
Beta
Tool
Production
Tool
-24
200
First Two
Companies
Reaching
Production
First
Conf.
Papers
Additional
Lead-time:
ERD/ERM
Research and
PIDS Transfer
2K
-12
Source: 2009 ITRS - Exec. Summary Fig 2a
0
Months
12
Work in Progress – Do Not Publish!
20
2
24
18
ERD/ERM Long-Range R&D and PIDS Transfer Timing Model Technology Cycle Timing
[Example: MOSFET High-mobility Channel Replacement Materials]
Development
Production
200K
20K
2K
Transfer to
PIDS/FEP
Alpha Beta Product
Tool Tool Tool
(96-72mo
Leadtime)
First
Tech. Conf.
Device Papers
Up to ~12yrs
Prior to Product
-96
Hi-m
Example:
1st 2 Co’s
Reach
Product
First
Tech. Conf.
Circuits Papers
Up to ~ 5yrs
Prior to Product
-72
-48
200
-24
0
20
2
24
Months
2011
2013
2015
Source: 2009 ITRS - Executive Summary Fig 2b
2017
Work in Progress – Do Not Publish!
2019
2021
19
Volume (Wafers/Month)
Research
2009 WAS
2010
Unchanged
[2009 – Unchanged]
2008 ITRS “Beyond CMOS” Definition Graphic
Baseline Ultimately
Functionally
CMOS
Scaled CMOS Enhanced CMOS
32nm
22nm
16nm
11nm
Ferromagnetic Spin Logic
Nanowire
Electronics Logic Devices Devices
8nm
Multiple gate MOSFETs
Channel Replacement Materials
Low Dimensional Materials Channels
New State Variable
New Devices
New Data Representation
New Data Processing
Algorithms
“More Moore”
“Beyond CMOS”
Computing and Data Storage Beyond CMOS
Source: Emerging Research Device Working Group
20
Work in Progress – Do Not Publish!
INDEX
ORTC Table 2D - Including Corrections
2009
2010
2011
2012
2013
2014
2015
2016
Flash ½ Pitch (nm ) (un-contacted Poly)(f)
38
32
28
25
23
20
18
15.9
DRAM ½ Pitch (nm ) (contacted)
52
45
40
36
32
28
25
22.5
MPU/ASIC Metal 1 (M1) ½ Pitch (nm )
54
45
38
32
27
24
21
18.9
MPU Printed Gate Length (GLpr) (nm ) ††
47
41
35
31
28
25
22
19.8
MPU Physical Gate Length (GLph) (nm )
29
27
24
22
20
18
17
15.3
Year of Production
Logic (Low-volum e Microprocessor) High-perform ance ‡
WAS
Generation at Introduction
IS/Correction
WAS
Functions per chip at introduction (m illion transistors)
IS/Correction
2
WAS
Chip size at introduction (m m )
IS/Correction
WAS
Generation at production **
IS/Correction
Functions per chip at production (m illion transistors)
2
p10h
p12h
p12h
p14h
p14h
p14h
p17h
p17h
p11h
p11h
p13h
p13h
p16h
p16h
p16h
p19h
4,424
4,424
8,848
8,848
8,848
17,696
17,696
17,696
4,424
4,424
8,848
8,848
17,696
17,696
17,696
35,391
520
368
520
413
328
520
413
328
520
368
520
368
520
413
328
520
p08h
p10h
p10h
p12h
p12h
p14h
p14h
p14h
p09h
p09h
p11h
p11h
p13h
p13h
p13h
p16h
2,212
2,212
4,424
4,424
8,848
8,848
8,848
17,696
260
184
260
184
260
206
164
260
OH % of Total Chip Area
29.5%
29.5%
29.5%
29.5%
29.5%
29.5%
29.5%
29.5%
Logic Core+SRAM (Without OH Average Density (Mt/cm 2)
1,207
1,707
2,414
3,414
4,828
6,083
7,664
9,656
851
1,203
1,701
2,406
3,403
4,287
5,402
6,806
851
1,203
1,701
2,406
3,403
4,287
5,402
6,806
858
858
858
858
858
858
858
858
7,299
10,323
14,599
20,646
29,198
36,787
46,348
58,395
2017
2018
2019
2020
2021
2022
2023
2024
14.2
12.6
11.3
10.0
8.9
8.0
7.1
6.3
20.0
17.9
15.9
14.2
12.6
11.3
10.0
8.9
16.9
15.0
13.4
11.9
10.6
9.5
8.4
7.5
17.7
15.7
14.0
12.5
11.1
9.9
8.8
7.9
14.0
12.8
11.7
10.7
9.7
8.9
8.1
7.4
Chip size at production (m m
) §§
2
High-perform ance MPU Mtransistors/cm
at introduction
and production (including on-chip SRAM) ‡
ASIC
ASIC usable Mtransistors/cm
2
(auto layout)
2
ASIC m ax chip size at production (m m ) (m axim um
lithographic field size)
ASIC m axim um functions per chip at production
(Mtransistors/chip) (fit in m axim um lithographic field size)
p17h
p20h
p20h
p20h
p23h
p23h
p23h
p24h
p19h
p19h
p22h
p22h
p22h
p25h
p25h
p25h
35,391
35,391
35,391
70,782
70,782
70,782
70,782
70,782
35,391
35,391
70,782
70,782
70,782
141,564
141,564
141,564
520
413
328
520
413
328
520
413
413
328
520
413
328
520
413
328
p17h
p17h
p17h
p20h
p20h
p20h
p23h
p23h
p16h
p16h
p19h
p19h
p19h
p22h
p22h
p22h
17,696
17,696
35,391
35,391
35,391
70,782
70,782
70,782
206
164
260
206
164
260
206
164
29.5%
29.5%
29.5%
29.5%
29.5%
29.5%
29.5%
29.5%
12,166
15,328
19,312
24,332
30,656
38,625
48,664
61,313
21,608
27,224
34,300
43,215
Work in Progress
– Do 13,612
Not Publish!
8,575
10,804
17,150
21
ORTC Table 2C - Including Corrections
ITWG
INDEX
Table ORTC-2C
MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model
2009
2010
2011
2012
2013
2014
2015
2016
Flash ½ Pitch (nm ) (un-contacted Poly)(f)
38
32
28
25
23
20
18
15.9
DRAM ½ Pitch (nm ) (contacted)
52
45
40
36
32
28
25
22.5
MPU/ASIC Metal 1 (M1) ½ Pitch (nm )
54
45
38
32
27
24
21
18.9
MPU Printed Gate Length (GLpr) (nm ) ††
47
41
35
31
28
25
22
19.8
MPU Physical Gate Length (GLph) (nm )
29
27
24
22
20
18
17
15.3
SRAM Cell (6-transistor) Area factor ++
60
60
60
60
60
60
60
60
Logic Gate (4-transistor) Area factor ++
175
175
175
175
175
175
175
175
SRAM Cell (6-transistor) Area efficiency ++
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
Logic Gate (4-transistor) Area efficiency ++
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.17
0.12
0.09
0.061
0.043
0.034
0.027
0.021
0.275
0.194
0.137
0.097
0.069
0.055
0.043
0.034
0.50
0.35
0.25
0.18
0.13
0.10
0.079
0.063
Year of Production
SRAM Cell (6-transistor) Area (µm
2
)++
SRAM Cell (6-transistor) Area w/overhead (µm
2
)++
Logic Gate (4-transistor) Area (um 2) ++
Logic Gate (4-transistor) Area w/overhead (µm
Transistor density SRAM (Mtransistors/cm
Transistor density logic (Mtransistors/cm
2
2
2
) ++
)
)
WAS
Generation at introduction *
IS/Correction
Functions per chip at introduction (m illion transistors
[Mtransistors])
WAS
IS/Correction
WAS
Chip size at introduction (m m
IS/Correction
2
) ‡
1.00
0.71
0.50
0.35
0.25
0.20
0.16
0.13
2,182
3,086
4,365
6,173
8,730
10,999
13,858
17,459
399
564
798
1,129
1,596
2,011
2,534
3,193
p11c
p11c
p13c
p13c
p13c
p16c
p16c
p16c
p11c
p11c
p13c
p13c
p16c
p16c
p16c
p19c
1546
1546
3092
3092
3092
6184
6184
6184
1546
1546
3092
3092
6184
6184
6184
12368
280
198
280
222
176
280
222
176
280
198
280
222
280
222
176
280
2017
2018
2019
2020
2021
2022
2023
2024
14.2
12.6
11.3
10.0
8.9
8.0
7.1
6.3
20.0
17.9
15.9
14.2
12.6
11.3
10.0
8.9
16.9
15.0
13.4
11.9
10.6
9.5
8.4
7.5
17.7
15.7
14.0
12.5
11.1
9.9
8.8
7.9
14.0
12.8
11.7
10.7
9.7
8.9
8.1
7.4
60
60
60
60
60
60
60
60
175
175
175
175
175
175
175
175
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.017
0.014
0.011
0.009
0.007
0.005
0.004
0.003
0.027
0.022
0.017
0.014
0.011
0.0086
0.0068
0.0054
0.050
0.039
0.031
0.025
0.020
0.016
0.012
0.010
0.10
0.079
0.063
0.050
0.039
0.031
0.025
0.020
21,997
27,715
34,919
43,995
55,430
69,838
87,990
110,860
4,022
5,068
6,385
8,045
10,136
12,770
16,090
20,272
p19c
p19c
p19c
p22c
p22c
p22c
p25c
p25c
p19c
p19c
p22c
p22c
p22c
p25c
p25c
p25c
12368
12368
12368
24736
24736
24736
49471
49471
12368
12368
24736
24736
24736
49471
49471
49471
280
222
176
280
222
176
280
222
222
176
280
222
176
280
222
176
Work in Progress – Do Not Publish!
22
4Q09 SICAS Update Proposal
From Furukawa-san/Japan
To IRC 3/28/10 (modified by AA)
Technology Cycle Timing Compared to
Actual Wafer Production Technology Capacity Distribution
>0.7mm
10
W.P.C.= Total Worldwide Wafer Production Capacity* Sources: SICAS
Feature Size (Half Pitch) (mm)
W.P.C
W.P.C
.
W.P.C
W.P.C
.
W.P.C
.
W.P.C
.
W.P.C
W.P.C
.
W.P.C
.
W.P.C
0.7-0.4mm
W.P.C
.
0.4-0.3mm
0.3- 0.2mm
1
0.2- 0.16mm
0.16-.12mm
0.08-.12mm
0.1
<0.08mm
= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual
= 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target
= 2009 ITRS Flash Un-contacted Poly Half Pitch Target
= 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target
<0.06mm
2008/09 ITRS: 2.5-Year Ave Cycle for DRAM
3-Year Cycle
2-Year DRAM Cycle
0.01
1999
2000
2001
2002
3-Year DRAM Cycle ; 2-year Cycle Flash and MPU
2003 2004
Year
Year
2005
2006
2007
2008
2009
3-Year Cycle
After 2010 for
Flash; after 2013
For MPU
2010
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2009.
The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that range
of the feature size (y-axis). Data are based upon capacity if fully utilized.
Source: 2009 ITRS - Executive Summary Fig 3
Work in Progress – Do Not Publish!
2013
23
Industry “Node”* Alignment w/ITRS [2009 ITRS]
DRAM Density “Equiv. Scaling”:
Flash Density MLC “Equiv. Scaling”:
MPU Perform/Power “Equiv. Scaling”:
8f2
8f2
16/11/8/5.5/4f2: 2b/cell
Copper
6f2
2.0f2:
2b/cell
Strain
Dimensional Half Pitch Scaling (EOT not shown):
Year
4f2
1.5f2:
HiK/MG I, II
1.0f2:4b/cell
3b/cell
FDSOI
TBD
TBD
TBD
2.5
7.5
‘99 ‘00 ‘01 ‘02 ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20 ‘21 ‘22 ‘23 ‘24 ‘25
“180”“160”“130”“110” “90” “80” “65” “55” “45” “40” “32” “28” “22” “20” “16”
’91-’93: <200mm ->200mm
@ 0.5u->0.35u M1
’01-’03: 200mm->300mm
@ 180nm->130nm M1
Past  Future
“8.0”
“5.6”
“4.0”
207 180 157 136 119 103 90 78 68 59 52 45 40 36 32 28 25 22
16
11
8
207 180 151 127 107 90 76 64 54 45 38 32 28 25 22 20 18 16
11
8
6
->
“11”
303 255 214 180 151 127 107 90 76 64 54 45 38 32 27 24 21 19
2007
54nm 45nm
68nm
MPU/hpASIC “Node*”: “45nm”
2009 ITRS MPU/hpASIC M1 : 76nm 65nm
2009 ITRS hi-perf GLpr :
54nm 47nm
2009 ITRS hi-perf GLph :
32nm 29nm
2009 IS ITRS Flash Poly :
2009 IS ITRS DRAM M1 :
MUGFET; SiGE
TBD
TBD
Hi-u tbd
Past  Future
“Node”
Hi-Performance
MPU/hpASIC
~Actual
Public Node
DRAM Actual M1
References*;
+extrapolation
Flash Actual Poly
2009 ITWG Table Timing:
TBD
TBD
’14-’16: 300mm->450mm
@ 32nm->22nm M1
Industry Typical “Node” vs ITRS M1 and Poly Alignment
2010
2013
32nm
22nm
45nm
32nm
“32nm”
“22nm”
“16nm”
54nm 45nm 38nm 32nm 27nm
47nm 41nm 35nm 31nm 28nm
29nm 27nm 24nm 22nm 20nm
2016
16nm
22nm
“11nm”
19nm
20nm
15nm
2019]
11nm
16nm
“8nm”
13nm
14nm
12nm
2009 ITRS: 2009-2024
*Notes on “Nodes”: DRAM, Flash “Nodes” ~= M1 and Poly Half-pitch.
However high performance Logic (MPU, hpASIC) may have node “labels” Associated with their dimensional technology progress, as referenced in:
1) MPU reference: Mark Bohr Tutorial, Jul’09: http://www.wesrch.com/Documents/view_editorial.php?flag=3&editorial_id=EL1FYLN
2) hpASIC reference TSMC “Nodes” Articles: http://www.xbitlabs.com/news/other/display/20080930205529_TSMC_Unveils_32nm_28nm_Process_Technologies_Roadmap.html ;
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=177100620
MPU & ASIC Low-Power versions typically lag Gate Length to manage power and performance trade-offs at the same M1-based density “Node” as high-performance versions
24