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Computertechniek
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Wouter van Ooijen
Mail: [email protected]
Sheets en info:
www.voti.nl/hvu/D4ECPT2
Onderwerp: Programmeren van een Embedded Systeem
Literatuur:
ARM system on chip architecture
S.B. Furber
Addison Wesley Longman
0-201-67519-6
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Computertechniek
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inleiding embedded/real-time/microcontrollers
embedded programming
ARM assembly language
…
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ontstaansgeschiedenis
wat is een microcontroller
wat is embedded
wat is real-time
soorten microcontrollers
productniveaus
embedded development
cost engineering
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Computertechniek
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steeds meer transistoren op een chip...
losse transistor
analoge ICs
logica
micro processor
micro controller
programmeerbare
logica
‘super’
microprocessor
klant-specifieke
logica
uC als IP
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meestal:
 ‘computer-achtig’ ding
 geschikt voor real-time
 geschikt voor embedded gebruik
 combinatie van processor, ROM, RAM, I/O, ...
 compact
 goedkoop
 zuinig
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 ergens in,
deel van een geheel
 vaste functie,
dus niet vrij programmeerbaar
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Computertechniek
niet:
 snel
 zo snel mogelijk
 interactief, batch
wel:
 op tijd!
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Computertechniek
nut
responstijd
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desktop PC
een PC als besturing van een rontgen toestel
industriele PC104 single-board PC
(computer) muis
furbie
ontsteker van een torpedo
besturing van een videorecorder
palmtop computer
electronische agenda
MP3 speler
ansichtkaart met melodietje
Microsoft X-box
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Computertechniek
ultra-goedkoop
chinees, inclusief de documentatie
lastig verkrijgbaar
general-purpose
PIC, Atmel, 8051, 68HC
high-end
ARM, PowerPC
special purpose
DSP, ethernet, USB, analoog, ...
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IP
kale chip
chip in behuizing
module
PCB
box (bv PLC)
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Computertechniek
bijna altijd cross-development:
 jij werkt op een PC
 daar draait je editor, compiler,
assembler, linker
 loader of programmer om te laden
 cross-debugger, ICE
 primitiever: burn and crash
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Computertechniek
C (of een andere HLL): grof
 makkelijk en snel
 reduceert de ontwikkelkosten
Assembler: nauwkeurig
 moeilijker, specifiek, meer werk
 reduceert de hardware kosten
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Computertechniek
 vaak het meeste in C
 kritische delen in assembler
 kennis van assembler is nuttig
voor efficient gebruik
van een controller, ook in C !
 het zal je maar gebeuren:
een bug in je compiler...
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eenmalige kosten
 ontwikkelsysteem, software
 kennis, traning
per-unit kosten
 de microcontroller zelf
 invloed op de rest van het product
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CISC
 doe zo veel mogelijk per instructie
 codeer instructies compact
RISC
 voer zoveel mogelijk instructies uit
 codeer instructies simpel
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1983 : een opvolger voor the BEEP
uit pure noodzaak: RISC, klein
Acorn RISC Machine
zuinig (veel MIPS per Watt)
krachtig
beschikbaar als chip, maar ook als IP
interne of externe bus
MAC
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Computertechniek
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ARM
Advanced RISC Machines
• load store architecture
• fixed length 32-bit instructions
• 3-address instruction formats
• many instructions execute in one cycle
• instructions are conditionally executed
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ARM User Programming model
31
0
r0
r1
r2
r3
r4
r5
r6
r7
31
0
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
0
31
CPSR
Status register
NZCV
r13: stack pointer
r14: link register
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The Program Status Registers
(CPSR and SPSRs)
31
28
4
8
N Z CV
I F T
0
Mode
Copies of the ALU status flags (latched if the
instruction has the "S" bit set).
*
*
Condition Code Flags
N = Negative result from ALU flag.
Z = Zero result from ALU flag.
C = ALU operation Carried out
V = ALU operation oVerflowed
Mode Bits
M[4:0] define the processor mode.
*
Interrupt Disable bits.
I = 1, disables the IRQ.
F = 1, disables the FIQ.
*
T Bit
(Architecture v4T only)
T = 0, Processor in ARM state
T = 1, Processor in Thumb state
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Condition Flags
Flag
Logical Instruction
Arithmetic Instruction
Negative
(N=‘1’)
No meaning
Bit 31 of the result has been set
Indicates a negative number in
signed operations
Zero
(Z=‘1’)
Result is all zeroes
Result of operation was zero
Carry
(C=‘1’)
After Shift operation
‘1’ was left in carry flag
Result was greater than 32 bits
oVerflow
(V=‘1’)
No meaning
Result was greater than 31 bits
Indicates a possible corruption of
the sign bit in signed
numbers
Are changed if s-flag is set
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The ARM condition code field
31
28 27
0
cond
All instructions are conditionally executed!
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Conditions
Opcode
[31:28]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Mnemonic
extension
EQ
NE
CS/HS
CC/LO
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
NV
Interpretation
Equal / equals zero
Not equal
Carry set / unsigned higher or same
Carry clear / unsigned lower
Minus / negative
Plus / positive or zero
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Signed greater than or equal
Signed less than
Signed greater than
Signed less than or equal
Always
Never (do not use!)
Status flag state for
execution
Z set
Z clear
C set
C clear
N set
N clear
V set
V clear
C set and Z clear
C clear or Z set
N equals V
N is not equal to V
Z clear and N equals V
Z set or N is not equal to V
any
none
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basic instruction groups
• data processing
• single address load and store
• flow control
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Data processing Instructions
• Largest group of instructions, all sharing the same instruction format.
• Contains:
–
–
–
–
Arithmetic operations
Comparisons (no results - just set condition codes)
Logical operations
Data movement between registers
• Remember, this is a load / store architecture
– These instruction only work on registers, NOT memory.
• They each perform a specific operation on one or two operands.
– First operand always a register - Rn
– Second operand sent to the ALU via barrel shifter.
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Data processing instruction binary encoding
31
28 2726 25 24
cond
21 20 19
0 0 # opcode S
1615
Rn
12 11
0
operand 2
Rd
destination register
first operand register
set condition codes
arithmetic/logic function
25
11
8 7
#rot
1
0
8-bit immediate
immediate alignment
11
7 6 5 4 3
#shift
25
immediate shift length
0
shift type
Sh 0
0
Rm
second operand register
11
8 7 6 5 4 3
Rs
0 Sh 1
0
Rm
register shift length
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Arithmetic Operations
• Operations are:
–
–
–
–
–
–
ADD
ADC
SUB
SBC
RSB
RSC
operand1 + operand2
operand1 + operand2 + carry
operand1 - operand2
operand1 - operand2 + carry -1
operand2 - operand1
operand2 - operand1 + carry - 1
• Syntax:
– <Operation>{<cond>}{S} Rd, Rn, Operand2
• Examples
– ADD r0, r1, r2
– SUBGT r3, r3, #1
– RSBLES r4, r5, #5
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Comparisons
• The only effect of the comparisons is to
– UPDATE THE CONDITION FLAGS. Thus no need to set S bit.
• Operations are:
–
–
–
–
CMP
CMN
TST
TEQ
operand1 - operand2, but result not written
operand1 + operand2, but result not written
operand1 AND operand2, but result not written
operand1 EOR operand2, but result not written
• Syntax:
– <Operation>{<cond>} Rn, Operand2
• Examples:
– CMP
– TSTEQ
r0, r1
r2, #5
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Logical Operations
• Operations are:
–
–
–
–
AND
EOR
ORR
BIC
operand1 AND operand2
operand1 EOR operand2
operand1 OR operand2
operand1 AND NOT operand2 [ie bit clear]
• Syntax:
– <Operation>{<cond>}{S} Rd, Rn, Operand2
• Examples:
– AND
– BICEQ
– EORS
r0, r1, r2
r2, r3, #7
r1,r3,r0
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Data Movement
• Operations are:
– MOV
– MVN
operand2
NOT operand2
Note that these make no use of operand1.
• Syntax:
– <Operation>{<cond>}{S} Rd, Operand2
• Examples:
– MOV
– MOVS
– MVNEQ
r0, r1
r2, #10
r1,#0
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The Barrel Shifter
• The ARM doesn’t have actual shift instructions.
• Instead it has a barrel shifter which provides a
mechanism to carry out shifts as part of other
instructions.
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Barrel Shifter - Left Shift
• Shifts left by the specified amount (multiplies by powers of
two) e.g.
LSL #5 = multiply by 32
Logical Shift Left (LSL)
C
Destination
0
Only if S flag set
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Barrel Shifter - Right Shifts
Logical Shift Right
•Shifts right by the
specified amount (divides
by powers of two) e.g.
Logical Shift Right
...0
Destination
C
LSR #5 = divide by 32
Arithmetic Shift Right
•Shifts right (divides by
powers of two) and
preserves the sign bit, for
2's complement
operations. e.g.
ASR #5 = divide by 32
Arithmetic Shift Right
Destination
Sign bit shifted in
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Barrel Shifter - Rotations
Rotate Right (ROR)
• Similar to an ASR but the bits
wrap around as they leave the
LSB and appear as the MSB.
e.g. ROR #5
Rotate Right
Destination
C
• Note the last bit rotated is also
used as the Carry Out.
Rotate Right Extended (RRX)
• This operation uses the CPSR C
flag as a 33rd bit.
• Rotates right by 1 bit. Encoded
as ROR #0.
Rotate Right through Carry
Destination
C
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Using the Barrel Shifter
Operand 1
Operand 2
Barrel
Shifter
ALU
• Shifted Register
• Shift value can be either be:
– 5 bit unsigned integer
– Specified in bottom byte of another
register.
* Immediate value (constant)
• 8 bit number rotated right trough an
even number of positions
Result
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Shift Register value
• The amount by which the register is to be shifted is contained
in either:
– the immediate 5-bit field in the instruction
• NO OVERHEAD
• Shift is done for free - executes in single cycle.
– the bottom byte of a register (not PC)
• Then takes extra cycle to execute
• ARM doesn’t have enough read ports to read 3 registers at once.
• Then same as on other processors where shift is
separate instruction.
• If no shift is specified then a default shift is applied: LSL #0
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Using a Shifted Register
• Using a multiplication instruction to multiply by a constant means
waiting a number of internal cycles for the instruction to complete.
• A more optimum solution can often be found by using some combination
of MOVs, ADDs, SUBs and RSBs with shifts.
– Multiplications by a constant equal to a ((power of 2) ± 1) can be done in one
cycle.
• Example: r0 = r1 * 5
Example: r0 = r1 + (r1 * 4)
ADD
r0, r1, r1, LSL #2
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Immediate Value (1)
• There is no single instruction which will load a 32 bit immediate constant
into a register.
– All ARM instructions are 32 bits long
11
8 7
#rot
x2
0
8-bit immediate
Shifter
ROR
• These 8 bits can then be rotated right through an even number of
positions (ie RORs by 0, 2, 4,..30).
– This gives a much larger range of constants that can be directly loaded,
though some constants will still need to be loaded
from memory.
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Immediate Value (2)
•
This gives us:
–
–
–
–
•
0 - 255
256,260,264,..,1020
1024,1040,1056,..,4080
4096,4160, 4224,..,16320
These can be loaded using, for example:
– MOV r0, #0x40, 26
•
; => MOV r0, #0x1000 (ie 0x40 ror 26)
The bitwise complements can also be formed using MVN:
– MOV r0, #0xFFFFFFFF
•
; => MOV r0, #0x1000 (ie 4096)
To make this easier, the assembler will convert to this form for us if simply given
the required constant:
– MOV r0, #4096
•
[0 - 0xff]
[0x100-0x3fc, step 4, 0x40-0xff ror 30]
[0x400-0xff0, step 16, 0x40-0xff ror 28]
[0x1000-0x3fc0, step 64, 0x40-0xff ror 26]
; assembles to MVN r0, #0
If the required constant cannot be generated, an error will
be reported.
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Load / Store Instructions
• The ARM has three sets of instructions which interact with main
memory. These are:
– Single register data transfer (LDR / STR).
*
Syntax:
• <LDR|STR>{<cond>}{<size>} Rd, <address>
– Block data transfer (LDM/STM).
– Single Data Swap (SWP).
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Data transfer instruction binary encoding
31
28 2726 25 2423 2221 20 19
cond
0 1 # P U BW L
1615
Rn
12 11
0
of f set
Rd
source/desti nation reg ister
base r eg ister
load/store
write- back (auto- index)
unsig ned byte/word
up/down
pre- /post-i ndex
25
11
0
12-bit immediat e
0
25
11
7 6 5 4 3
#shif t
1
Sh 0
0
Rm
immediate shift leng th
shift type
offset reg ister
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Addressing mode: Base Register
• The memory location to be accessed is held in a base register
– STR r0, [r1]
; Store contents of r0 to location pointed to
; by contents of r1.
; Load r2 with contents of memory location
; pointed to by contents of r1.
– LDR r2, [r1]
Memory
r0
Source
Register
for STR
0x5
r1
Base
Register
0x200
r2
0x200
0x5
0x5
Destination
Register
for LDR
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Addressing mode: Pre-indexed
•
Memory
Example: STR r0, [r1,#12]
r0
0x5
Source
Register
for STR
Offset
12
0x20c
0x5
r1
Base
Register
0x200
0x200
•
•
To store to location 0x1f4 instead use: STR r0, [r1,#-12]
To auto-increment base pointer to 0x20c use: STR r0, [r1, #12]!
•
If r2 contains 3, access 0x20c by multiplying this by 4:
– STR r0, [r1, r2, LSL #2]
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Addressing mode: Post-indexed
Memory
• Example: STR r0, [r1], #12
Updated
Base
Register
Original
Base
Register
r1
Offset
0x20c
12
r1
r0
0x5
0x20c
0x200
Source
Register
for STR
0x5
0x200
• To auto-increment the base register to location 0x1f4 instead use:
– STR r0, [r1], #-12
• If r2 contains 3, auto-incremenet base register to 0x20c by multiplying
this by 4:
– STR r0, [r1], r2, LSL #2
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Branch and Branch link
*Branch :
*Branch with Link :
31
28 27
Cond
1
B{<cond>} label
BL{<cond>} sub_routine_label
25 24 23
0
0
1 L
Offset
Link bit
0 = Branch
1 = Branch with link
Condition field
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Branch instructions (2)
• When executing the instruction, the processor:
– shifts the offset left two bits, sign extends it to 32 bits, and adds it to PC.
• Execution then continues from the new PC, once the pipeline has
been refilled.
• The "Branch with link" instruction implements a subroutine call
by writing PC-4 into the LR of the current bank.
– i.e. the address of the next instruction following the branch with link
(allowing for the pipeline).
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The Program Counter (R15)
• All instructions are 32-bits
• All instructions must be word aligned
PC value is stored in bits [31:2] with bits [1:0] equal to zero
• R14 is the subroutine link register (LR) stores the return address at
Branch Link, calculated from the PC.
• Thus to return from a linked branch
– MOV r15,r14
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doen
lees hoofdstuk 1, 2, 3
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