Transcript 投影片 1 - University of California, Los Angeles

NTHU H.264/AVC Video
Encoder & Decoder
Youn-Long Lin
Department of Computer Science
National Tsing Hua University
Hsin-Chu, TAIWAN 300
[email protected]
2007/02/10
IC-DFN, Las Vegas
Evolution of Video Coding Standards
DVD/DTV
ITU-T
Standards
H.263
H.261
Joint ITU-T/ISO
Standards
H.263+
H.262/
MPEG-2
ISO
Standards
H.264
MPEG-4
MPEG-1
1984
1986
VCD
1988
1990
1992
1994
MP3
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1996
1998
2000
2002
2004
DV/IPCam
2
Get More (Quality) for Less (Bit-rate)
H.264
MPEG2
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Effectiveness of basic techniques
1) No MC;
2) Adding Skip mode to
form a CR coder.
3) Allow only zero-valued
MVs.
4) Allow integer-pel MC.
5) Allow half-pel MC
6) Allowing 4-MV;
7) Allowing quarter-pel MC.
Ref: G. Sullivan & T. Wiegand, “Video Compression—From Concepts to the H.264/AVC
Standard”, Proceedings of the IEEE, Vol 93, No.1, Jan 2005
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Features of Video Coding Standards
Standard
MPEG-1
MPEG-2
MPEG-4
H.264
MB size
16*16
16*16(frame)
16*16
16*16
Block size
8*8
8*8
16*16, 8*8
16*16, 16*8, 8*16, 8*8, 8*4, 4*8,
4*4
Transform
DCT
DCT
DCT/ Wavelet
4*4 int transform
Entropy coding
VLC
VLC
VLC
VLC, CAVLC and CABAC
ME, MC
Yes
Yes
Yes
41 MVs per MB
Pixel accuracy
½ pel
½ pel
¼ pel
¼ pel
Reference frames One frame
One frame
One frame
Multiple (5) frames
Picture type
I, P, B
I, P, B
I, P, B
I, P, B
Transmission rate
Up to
1.5 Mbps
2-15 Mbps
64kbps~2Mbps 64kbps ~ 150Mbps
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Competing Standards
• H.264 Advanced Video Coding (H.264/AVC)
– Also Called MPEG-4 Part 10
• WMV/VC-1 (MicroSoft)
• Chinese AVS (Audio Video Coding Standard)
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H.264/AVC Profiles
Extended
profile
SP, SI
slice
B slice
Interlace
Data
partition
Weighted
prediction
CABAC
Slice
group
I slice
ASO
P slice
Baseline
profile
Redundant
Slice
CAVLC
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8x8
transform
Main
profile
FREext
(High)
profile
Quantization
matrix
Color
Sampling
8/10/12 bit
sampling
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Global UniChip
Multimedia SOC Platform
Accelerator
(FPGA)
CPU
ROM/
Flash Memory
SRAM
USB(PHY)
Daughter Board
FPGA
VIC
Static
memory
USB 2.0
SDRAM
SDRAM Controller(4-CH)
High-Speed Bus
JPEG
Codec
DMA
SRAM
PWM
WDT
TIMER
APB
Bridge
Capture
Display
Controller
Video-In
CCIR601
TV/LCD
Peripheral Bus
DAI
Audio Codec
I2S
SSI
Flash memory
with SSI
SD
SM
Flash Card
UART
GPIO
Button
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12C
LED
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H.264/AVC Decoder System Diagram
ARM926EJS
TV
Master
Timer
Slave
SD Card
Slave
Slave
SDC
Slave
Slave
H264
Master
LM
Slave
SDC
Slave
UART
Slave
AHB1
SDRAM
SDRAM
AHB2
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H.264/AVC Decoder Architecture
CPU
SD Card
SDRAM
Storage Device
Input/Ref./Display
Frame
Display
AHB
MV
SRAM
Parser
Ref idx
SRAM
Para
SRAM
reconstruct
SRAM
MC
CABAD
MBinfo
SRAM
CAVLD
Coeff
SRAM
Intra
pred
Pred
SRAM
Residual
IQ/IDCT
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SRAM
Pic
Rec
unfilter
SRAM
DF
DECODER
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AMBA interface
AHB A
LM
slave wrapper
control register
H.264 Decoder
MFU
VLC & TV OUT
DF & MC
arbiter 1
arbiter 2
master wrapper 1
master wrapper 2
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AHB B
SDC
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NTHU Design Flow
Software spec. in C
& Acceleration
specify
SW lib.
C models,
drivers
User Spec.
Platform spec.
API
System
configuration
System.h
Embedded
Software
Compilation
Acceleration
Acceleration
Software
image
Co-Sim
System
descriptio
n
HW/SW
co-simulation
HW lib.
HDL IPs
System
generation
HW IP
Synthesizer
Accelerator.v
Evaluation
System
Integrate
Area & Timing
& Power
evaluation
No Performance
constraint
Yes
FPGA
prototyping
FPGA Verify
System.v
Parameterized
ISS
Platform
model
Integration
Hardware
image
Pin assignment & Hardware compilation
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Demo Video
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Encoder Demo – Video Capturing
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NTHU-PKU Collaboration
Porting NTHU H.264/AVC Encoder and
Decoder to PKU SOC Platform
Participants
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Job Function
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Schedule
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Schedule
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System Overview
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FPGA Prototyping
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Results
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Future Systems
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High-Performance QFHD
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SuperHDTV (3840x2160 QFHD)
3840x2160 - SuperHDTV
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Summary
• H.264/AVC Encoder & Decoder IP
– Two Platforms: UniChip and PKU
– Very High Performance (Cycles per MB)
• Future Directions
–
–
–
–
Super High Resolution (4X HDTV, 16X HDTV)
Low Power Design
Enhanced Platform and Design Flow
Chip Implementation
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