Transcript CORDIC-Based VLSI Architectures for Digital Signal Processing

VLSI Signal Processing
CORDIC
(Coordinate rotation digital computer)
For VLSI Signal Processing Course
Ref: Y. H. Hu, “CORDIC based VLSI architecture for
digital signal processing,” IEEE Signal Processing Mag.,
pp.16-35, July 1992.
2001/4/30
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VLSI Signal Processing
Rotation Operation
 x' cos
 y'   sin 
  
You need:
 sin    x(i) 
.


cos   y(i)
4 multipliers.
2 adders.
or ROM for Table Look-up
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VLSI Signal Processing
•What is “CORDIC” ?
–COordinate Rotation DIgital Computer
•Why do we use “CORDIC” ?
–MAC dominates the implementational
cost in some DSP functions.
–The DSP approach, CORDIC, helps to
save the hardware cost.
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VLSI Signal Processing
Basic Concept of The CORDIC
•To decompose the desired rotation angle (θ)
into the weighted sum of a set of predefined
elementary rotation angles (am(i))
•Such that the rotation through each of them
can be accomplished with simple shift-andadd operation.
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VLSI Signal Processing
Behavior of CORDIC
V(1)
V(3)
V(0)
x  y 1
2
2
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VLSI Signal Processing
In General Case:
 x(i  1) 
cos am
 y (i  1)   sin am



 sin am   x(i ) 
.

cos am   y(i )

 x(i  1) 
 1
 y (i  1)  cos am   t an am



 t an am   x(i ) 



1
y
(
i
)
 

In CORDIC Algorithm:
 x(i  1)  
 y (i  1)  

 

1
i
i2

 2i . x(i)
i
1


  y (i )
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VLSI Signal Processing
CORDIC Algorithm
n -1
n -1
i 0
i 0
     i    iam(i)
tan 1(a
)  2i
m
a  tan 1(2i )
m

 1 1  2 3  4.........
  tan 1(2 0 )  tan 1(21)  tan 1(2 2 ).........
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VLSI Signal Processing
Initiation:Given x(0),y(0),z(0)
For i=0 to n-1 ,Do
/*CORDIC iteration equation */
 x(i  1)   1
 y (i  1)  

 i2i
 i 2i   x(i ) 
.

1   y (i )
/*Angle updating equation*/
z(i  1)  z(i) -  i a m (i)
End i loop
/*Scaling Operation (required for m=±1 only)*/
 xf 
 x(n )
1
 yf   K m(n )  y (n )




Km ( n ) 
1
n 1
 cosa
m
i 0
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VLSI Signal Processing
X(i)
X-Reg
Barrel
shifter
Y(i)
Basic
processor for
CORDIC
Y-Reg
a(n-1)
Barrel
shifter
a(1)
a(0)
+/-
X(i+1)
+/-
Y(i+1)
Z-reg
i
Z(i+1)
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VLSI Signal Processing
Modes of Operations
• Vector rotation mode (θ is given) :
determined by the set of 
The objective is to compute the final
vector (Usually, we set z(0)= θ.)
n 1
z(0)- z(n)   - z(n)    a (i)
i m
i 0
 = sign of z(i)
θ
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VLSI Signal Processing
Modes of Operations (cont’d)
• Angle accumulation mode (θ is
not given)
The objective is to rotate the given initial
vector back to x-axis ,and the angle can
be accrued.(Now, we let z(0)=0.)
V(0)
θ
X-axis
 = - sign of x(i)·y(i)
V(1)
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VLSI Signal Processing
Scaling Operation
n 1
K m   1  m 2
2
i
 2 s ( m ,i )
i 0
P
1
Type.1 :
  k p 2 ip
K m (n) p 1
Q
1
Type.2 :
  (1  k q 2 iq )   q
K m (n) q 1
k p  1; k q  1;   2
b
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VLSI Signal Processing
X(n)
Y(n)
Scaling Stage
X-Reg
X(n)
Y(n)
Y-Reg
Type1 :
x ' (i  1)  x ' (i )  2
Barrel
shifter
i p
y ' (i  1)  y ' (i )  2
Barrel
shifter
x(n )
i p
y (n)
Type 2 :
i
x ' (i  1)  x ' (i )  2 q x ' ( n )
+/-
xf
+/-
yf
y ' (i  1)  y ' (i )  2
 iq
y ' (n )
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VLSI Signal Processing
Advantages and disadvantages
Simple Shift-and-add Operation.
(2 adders+2 shifters v.s. 4 mul.+2 adder)
-It needs n iterations to obtain n-bit
precision.
-Slow carry-propagate addition.
-Low throughput rate
-Area consuming shifting operations.
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How to improve CORDIC ?
• Use Pipelined Architecture
• Improve the Performance of the Adders
(redundant arithmetic, CSA)
• Reduce Iteration Number
– High radix CORDIC. (e.g., Radix-4, Radix-8)
– Find a optimized shift sequence (e.g., AR-CORDIC)
• Improve the Scaling Operation
– Canonical multiplier recoding
– Force Km to 2.
P
1
  k p 2ip
K m (n) p 1
k p  1
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VLSI Signal Processing
Parallel and Pipelined Arrays
x(0)
y(0)
Basic
Basic
Basic
CORDIC
CORDIC
CORDIC
Processor
1
Processor
2
Processor
n+s
vn s (1)
vns1 (0)
vns1 (2)
xf
yf
v2 (n  s  1)
v1 (n  s)
Basic
L
Basic
L
L
Basic
xn  s 1 (0)
CORDIC
A
CORDIC
A
A
CORDIC
xf
yn  s 1 (0)
Processor
T
T
C
C
Processor
yf
H
H
1
T
C
H
Processor
2
n+s
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VLSI Signal Processing
In General Case:
 x(i  1) 
cos am
 y (i  1)   sin am



 sin am   x(i ) 
.

cos am   y(i )

 x(i  1) 
 1
 y (i  1)  cos am   t an am



 t an am   x(i ) 



1
y
(
i
)
 

In CORDIC Algorithm:
 x(i  1)  
 y (i  1)   

 
2
i
1
 s (m,i )
 2 s(m,i) . x(i) 
m
i
1


  y (i )

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VLSI Signal Processing
Generalized CORDIC Algorithm
n -1
    iam(i)
i 0
1
a 
tan 1[ m 2 s(m,i) ] 
m
m
s(0,1)
2
tan12s(1,i)
tanh12s(1,i)
m0
m1
m1
m0 , linear system ;
m=1 , circular system ;
m=-1 , hyperbolic system.
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VLSI Signal Processing
V(1)
V(3)
V(4)
V(2)
V(0)
Circular
Different
coordinates
x2  y2  1
V(1)
V(3)
V(3)
V(2)
V(2)
V(1)
V(0)
V(0)
Linear
Hyperbolic
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VLSI Signal Processing
Initiation: Given x(0),y(0),z(0)
For i=0 to n-1 ,Do
/*CORDIC iteration equation */
1
 x (i  1)  


 y (i  1)

  i 2 s(m,i )
 mi 2
 s(m,i )  x (i )


.

  y (i ) 
1

/*Angle updating equation*/
z(i  1)  z(i) -
 a (i)
i
m
End i loop
/*Scaling Operation (required for m=±1 only)*/
 xf 
 x(n )
1
 yf   K m(n )  y (n )




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VLSI Signal Processing
Shift Sequence
{s(m,i); 0in-1}
Determine the convergence of the CORDIC
iteration, as well as the magnitude of the scaling
factor Km(n).
m=0 or 1 , s=(m,i)=i
m=-1 , s(-1,i)=1,2,3,4,4,5,….,12,13,14,14,..
An angle approximation
error:
  

n 1

i 0
 (i)am (i)
am (n 1)
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Application to DSP Algorithms
•
•
•
Linear transformation:
- DFT, Chirp-Z transform, DHT, and FFT.
Digital filters:
- Orthogonal digital filters, and adaptive lattice filters.
Matrix based digital signal processing
algorithms:
- QR factorization, with applications to Kalman
filtering
- Linear system solvers, such as Toeplitz and
covariance system solvers,……,etc.
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FFT application
a
b
a'
e  j 2nk N
-1
b'
a'  a  b  e  j 2nk N
b'  a  b  e
 j 2nk N
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VLSI Signal Processing
Butterfly unit
aR
+
a'R
aI
+
a'I
-
b' R
-
b' I
bR
bI
CORDIC
processor
e  j 2nk N
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VLSI Signal Processing
Conclusions
1. In some cases, CORDIC evaluates rotational
functions more efficiently than MAC units.
2. CORDIC saves more hardware cost.
3. By the regularity, the CORDIC based
architecture is very suitable for implementation
with pipelined VLSI array processors.
4. The utility of the CORDIC based architecture
lies in its generality and flexibility.
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