Transcript Dry Etching for Photomasks

Silicon Etch Process Options for Micro- and
Nanotechnology using Inductively Coupled Plasmas
C.C. Welch*, A.L.Goodyear*, G.Ditmer†, G.Tan‡
1.
Introduction
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Profile [degrees]
Silicon is suitable material for an ever-expanding range of micro- and nano-scale devices such as 2dphotonic crystals [1-3], micro-silicon waveguides [4], nano-SOI MOSFETS [5] and grating structures [6].
However until recently exploitation of such technology has been restricted by the difficulty of fabricating the
continually decreasing smaller features and higher aspect ratios demanded. In this work several solutions are
presented for the micro- and nano-scale etching of silicon using inductively coupled plasmas (ICP).
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Typically the important features of a silicon etching process for micro- and nanotechnology are as follows:
1) Feature sizes down to 0.1µm or less with aspect ratios at least 2:1
2) Controllable sidewall profile (generally vertical needed)
3) Smooth contamination free sidewalls
4) Sufficiently high selectivity over the mask and if applicable high selectivity over underlying layers.
5) Good uniformity and good reproducibility
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In Section 3, a choice of three complementary process strategies are described which provide excellent
solutions to the challenges of micro- and nano-scale etching of silicon.
Fig. 7 and Fig. 8 shows the flexibility of the process in its use for a 1µm wide x 5µm deep waveguide and for
50nm wide trenches (300nm deep) respectively.
Experimental Details
Figure 1: Plasmalab System100 ICP 180 Schematic
Figure 7: Room temperature F-based etch.
1µm wide x 5µm deep Si waveguide
C.
Table 1 summarizes the expected minimum process performance of the three process strategies as used for
micro- and nano-scale etching of silicon. The processes are then in turn described further and discussed
mentioning advantages and disadvantages of each.
TABLE 1. SUMMARY OF PROCESS PERFORMANCE FOR SILICON MICRO- AND NANO-SCALE ETCHING
Process
Depth [µm]
Feature size [µm]
Aspect ratio
Etch rate [nm/min]
Uniformity
>100:1
>3:1
80-92°
>10:1
>5:1
80-92°
>30:1
>15:1
80-92°
<5nm
<5nm
<5nm
Cryogenic silicon etch process
The primary control of profile angle in the cryogenic process is with O2:SF6 gas flow ratio and temperature.
These parameters determine the amount and volatility of the oxy-fluoride sidewall passivation respectively.
Low temperature and high O2:SF6 encourages a tapered profile. By balancing the parameters a vertical profile
may be readily achieved if desired.
HBr
RT F-base
Cryogenic
0.05µm to 1µm 0.05µm to 10µm 0.2µm to >100µm
≥25nm
≥25nm
≥25nm
≥5:1
≥5:1
≥10:1
≥100
≥200
≥300
<±5%
<±5%
<±5%
Selectivity Si:oxide
Selectivity Si:resist
Profile
Sidewall roughness
Figure 8: RT F-based etch. 50nm wide trenches in Si
(6:1 aspect ratio). Courtesy of ITRI/MIRL, Taiwan
The cryogenic silicon etching offers the best performance of all the options by using sub-minus 100°C
processing temperatures in conjunction with a non-corrosive chemistry: sulfur hexafluoride (SF6)-oxygen (O2).
At these temperatures the etch product (a silicon oxy-fluoride) is marginally volatile and provides sidewall
passivation for good profile control [7]. Like the other processes smooth controllable profiles are achieved but
the cryogenic process excels in its high selectivity over resist (and oxide) and its very high aspect ratio
capability. It can also etch much deeper than the other processes and is extremely clean. Of course the main
disadvantage is the need for liquid nitrogen cooling.
Choice of processes
A.
Profile angle as a function of C4F8 percentage in SF6
Angles <90° represent a tapered profile and >90° a re-entrant profile
Silicon etch process development has been carried out in commercial inductively coupled plasma (ICP) etch
equipment from Oxford Instruments Plasma Technology. Fig 1 is a schematic diagram of the Plasmalab
System 100 ICP180 tool suitable for substrates up to 100mm diameter. The Plasmalab System 100 ICP380
tool is similar but has a larger ICP tube and is suitable for substrates up to 200mm diameter. Pictures of actual
systems are shown in figure 2. Wafers are loaded into the chamber via a load lock to maintain good stability of
chamber vacuum and hence repeatability of etching results. Wafers are either mechanically or electrostatically clamped to the temperature-controlled lower electrode. Helium pressure is applied to the back of the
wafers to provide good thermal conductance between the electrode and the wafer. When necessary, smaller
samples are mounted on silicon carrier wafers with thermally conductive glue.
The Plasmalab System 100 ICP has control of substrate temperature over range -150°C to +400°C. This very
wide range permits great flexibility in processing as temperature controls the volatility of the etch species and
hence influences the chemical component of the process, affecting outputs such as etch rate, selectivity and
profile. Suitable flow rates of process gases are admitted to the chamber and controlled to a pressure usually in
the range 1mT to 100mT. Then RF power at 13.56MHz is applied to the ICP coil (up to 3000Watts) to generate
a high-density etching plasma. 13.56MHz power is also applied to the lower electrode (up to 600Watts) for
independent control of substrate DC bias. Unused feed gas and volatile etch products are pumped away by a
turbo molecular pump (with speed typically 1300l/sec) backed by a wet or dry pump (typically 40-60m3 /hr).
Silicon etching results were assessed by standard methods: thin film thicknesses by ellipsometry or Nanospec,
step heights by profilometer and profiles by scanning electron microscopy (SEM).
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C4F8 percentage
Figure 6.
2.
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Fig. 9 shows 20:1 aspect ratio silicon waveguides etched with the cryogenic process, while Fig 10 shows
0.1µm trenches etched to 1µm depth.
Figure 2: Actual Plasmalab System100 ICP Tools
Hydrogen Bromide (HBr) based silicon-on-insulator (SOI) process
2)
This process is useful when very high selectivity over a silicon dioxide insulator is required, such as for nanoscale MOSFETS [5] where the gate oxide is extremely thin. It is also a good choice for other SOI applications
where the selectivity demands are not so high because the process is free from notching effects at the siliconinsulator interface. Such applications include 2d-photonic crystals [3] where the addition of an insulator layer
such as silicon dioxide provides vertical confinement of light in the silicon (SiO2 having a lower refractive
index than Si). The HBr-based process has other benefits of smooth controllable profiles, high aspect ratio
capability and is very clean. Disadvantages are the need for corrosive gas HBr, the relatively low etch rate and
the depth limitation (the profile becomes difficult to control much beyond 1µm depth).
Generally oxide masking is preferred as this yields very high selectivity (so that etching back at the top of the
silicon sidewall is unlikely), but a vertical resist mask is also acceptable. The processing temperature is around
room temperature.
Profile control
Fig. 4 shows a fine dimension doped or undoped polycrystalline silicon etch stopping on very thin oxide.
Fig. 5 shows how the profile can be controlled from vertical to a tapered angle if desired (here for photonic
crystal holes 0.2µm wide x 0.3µm deep).
Figure 9: Cryogenic Si etch. 0.5µm wide
waveguidesx10µm deep with no mask undercut
4.
Figure 10: Cryogenic Si etch.
0.1µm gaps etched 1µm deep.Aspect ratio 10:1
Conclusion
Three complementary silicon etching process strategies are described, which provide excellent solutions to the
challenges of micro- and nano-scale etching of silicon. The processes address differing performance needs of
the widespread application types yet all may be used within the same ICP technology.
References
1)
Selectivity control
[1]
Oxygen substitution is used to raise selectivity of silicon over SiO2. Fig. 3 shows that extremely high
selectivities can be achieved once the O2 level reaches about 10%.
[2]
[3]
250
1500
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150
900
100
600
50
300
0
0
0
1
2
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Figure 5:
Selectivity PolySi:SiO2
PolySi ER nm/min
[4]
B.
5
Oxygen flow rate [sccm]
PolySi ER
Sel Poly:SiO2
Figure 3: Selectivity of polysilicon over SiO2
as a function of O2 flow
Figure 4: HBr based etch of 90nm polysilicon
lines and spaces stopping on 3nm gate SiO2.
HSQ masked.
a. Vertical HBr-based SOI etch.
b. Tapered HBr-based SOI etch.
Room temperature fluorinated chemistry silicon etch process
This option has the benefit of using a non-corrosive octofluorocyclobutane (C4F8) – sulfur hexafluoride (SF6)
chemistry at around room temperature. Like the HBr-based process it offers smooth controllable profiles and
high aspect ratio capability. It has higher selectivity over resist masks than the HBr process and its depth range
is considerably greater. However selectivity over oxide is much lower and there may be a tendency for
notching at oxide interfaces if extended over etches are needed to clear extreme topography. Also, using a
polymerizing gas (C4F8) the process is not perfectly clean and will require periodic plasma cleaning to maintain
performance but overall the room temperature F-base process is a good all round process usable for most
micro- and nano-scale silicon etching applications.
The main control for profile angle is the C4F8 – SF6 gas ratio as Fig. 6 shows.
*Oxford Instruments Plasma Technology, North End, Yatton, Bristol BS49 4AP, England, Tel +44 1934 837000, Fax +44 1934 837001, Email: [email protected], [email protected]
† Oxford Instruments Room, 14-F, No. 1 Plaza, 800 Nanjing East Road, Shanghai, 200001, CHINA, Email: [email protected]
‡ 371, Beach Road, #02-07 Keypoint, Singapore 199597, Phone: +65 63376848, Fax: +65 6337 6286 Email: [email protected]
[5]
[6]
[7]
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See http://www.physicsweb.org/article/world/13/8/9
M. Notomi, A. Shinya, and I. Yokohama, “Successful Fabrication of 2D Photonic Crystals,” Research
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W. Aroua, D. Gamra, F. Abdelmalek, and H. Bouchriha, “Finite-difference time-domain method for
design and analysis of microcavity coupled submicron-width silicon waveguides,” The European Physical
Journal Applied Physics, Vol. 17, Issue 3, pp. 215-221, March 2002.
M. Lemme, C. Welch, T. Mollenhauer, H. Gottlob, W. Henschel, J. Efavi, and H. Kurz,
“Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs,”
Microelectronic Engineering 73-74, pp. 346-350, 2004.
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and spaces in Tungsten and Silicon,” J. Vac. Sci. Technol. B, 18 (6), Nov/Dec 2000.
I. Rangelow, “Critical tasks in high aspect ratio silicon dry etching for microelectromechanical systems,”
J. Vac. Sci. Technol. A 21(4), Jul/Aug 2003.