Transcript Dry Etching for Photomasks

Silicon Etch Process Options for
Micro- and Nanotechnology using
Inductively Coupled Plasmas
C.C.Welcha, A.L.Goodyeara, T.Wahlbrinkb and M.Lemmeb
1.
2)
Introduction
Silicon is suitable material for a continually expanding range of micro- and nanoscale opto-and microelectronic
devices such as 2d-photonic crystals [1,2], micro-silicon waveguides [3], nano-SOI MOSFETS [4], grating
structures [5] and nanopillar structures [6]. However until recently exploitation of such technology has been
restricted by the difficulty of fabricating the ever-smaller features and higher aspect ratios demanded. In this
work several solutions are presented for the micro- and nanoscale etching of silicon for devices using inductively
coupled gas plasmas (ICP).
Profile control
Figure 3 shows a fine dimension doped or undoped polycrystalline silicon etch stopping on very thin
oxide. Figures 4 and 5 show that the profile can be controlled from vertical to a tapered angle if desired
(here for photonic crystal holes 0.2µm wide x 0.4µm deep. SiO2 mask intact).
Typically the important features of a silicon etching process for micro- and nanotechnology are as follows:
1) Feature sizes down to 0.1µm or less with aspect ratios at least 2:1
2) Controllable sidewall profile (generally vertical needed)
3) Smooth contamination free sidewalls
4) Sufficiently high selectivity over the mask and if applicable high selectivity over underlying layers.
5) Good uniformity and good reproducibility
A choice of three process strategies are described which meet the above needs while offering complementary
benefits in tackling the various challenges arising in the micro- and nanoscale etching of silicon. All three process
strategies may be performed using the same ICP platform.
2.
Figure 3: HBr-based etch of 34nm
polySi lines and spaces stopping on
3nm gate SiO2. HSQ masked.
Figure 4. Vertical
HBr-based SOI etch.
Figure 5. Tapered
HBr-based SOI etch.
Experimental Details
B.
This option has the benefit of using a non-corrosive octofluorocyclobutane (C4F8) – sulfur hexafluoride
(SF6) chemistry at around room temperature. Like the HBr-based process it offers smooth controllable
profiles and high aspect ratio capability. It has higher selectivity over resist masks than the HBr process
and its depth range is considerably greater. However selectivity over oxide is much lower and there may
be a tendency for notching at oxide interfaces if extended over etches are needed to clear extreme
topography. Also, using a polymerizing gas (C4F8) the process is not perfectly clean and will require
periodic plasma cleaning to maintain performance but overall the room temperature F-base process is a
good all round process usable for most micro- and nano-scale silicon etching applications.
The main control for profile angle is the C4F8 – SF6 gas ratio as Figure 6 shows. Figures 7 and 8 show
the flexibility of the process in its use for a 1µm wide x 5µm deep waveguide and for 50nm wide trenches
(300nm deep) respectively.
92
Profile [degrees]
Silicon etch process development has been carried out in commercially available inductively coupled plasma
(ICP) etch equipment from Oxford Instruments. Figure 1 is a schematic diagram of the Plasmalab System 100
ICP180 tool suitable for substrates up to 100mm diameter. The Plasmalab System 100 ICP380 tool is similar but
has a larger ICP tube and is suitable for substrates up to 200mm diameter. Small samples pieces may be
mounted on silicon carrier wafers with thermally conductive glue (note a smaller open load system, the Plasmalab
80plus ICP65 is available if only small samples are to be etched). The Plasmalab ICP Systems have control of
substrate temperature from -150°C to +400°C. This very wide range permits great flexibility in processing.
Wafers are loaded into the chamber via a load lock and either mechanically or electrostatically clamped to the
temperature-controlled lower electrode. Helium pressure is applied to the back of the wafers to provide good
thermal conductance between the electrode and the wafer. The process gases are admitted to the chamber and
controlled to a pressure usually in the range 1mT to 100mT. Then RF power at 13.56MHz is applied to the ICP
coil (up to 3000Watts) to generate a high-density etching plasma. 13.56MHz power is also applied to the lower
electrode (0 to 600Watts) for independent control of substrate DC bias. Unused feed gas and volatile etch
products are pumped away by a turbo molecular pump (with speed typically 1300l/sec) backed by a wet or dry
pump (typically 40-60m3 /hr).
Silicon etching results were assessed by standard methods: thin film thicknesses by ellipsometry or Nanospec,
step heights by profilometer and profiles by scanning electron microscopy (SEM).
Process
HBr
Depth [µm]
0.05µm
to 1µm
≥5nm
Feature size
[nm]
Aspect ratio
Etch rate
[nm/min]
Uniformity
Selectivity
Si:oxide
Selectivity
Si:resist
Profile
Sidewall
roughness
Figure 1: Plasmalab System100 ICP 180 Schematic
3.
RT FCryogenic
base
0.05µm to 0.2µm to
10µm
>100µm
≥5nm
≥5nm
Room temperature fluorinated chemistry silicon etch process
91
90
89
88
87
86
85
84
64
71
C4F8 percentage
Figure 6. Profile angle as a
function of % C4F8 in SF6
Figure 7. RT F-based etch
1µm wide x 5µm deep Si
waveguide
Figure 8: RT F-based etch
50nm wide trenches in Si (6:1
aspect ratio).
≥5:1
≥100
≥5:1
≥200
≥10:1
≥300
<±5%
<±5%
<±5%
C.
>100:1
>5:1
>10:1
>1:1
>3:1
>5:1
80-92°
80-92°
80-92°
The cryogenic silicon etching offers the best performance of all the options by using sub-minus 100°C
processing temperatures in conjunction with a non-corrosive chemistry: sulfur hexafluoride (SF6)-oxygen (O2).
At these temperatures the etch product (a silicon oxy-fluoride) is marginally volatile and provides sidewall
passivation for good profile control [7]. Like the other processes smooth controllable profiles are achieved but
the cryogenic process excels in its high selectivity over resist (and oxide) and its very high aspect ratio
capability. It can also etch much deeper than the other processes and is extremely clean. Of course the
main disadvantage is the need for liquid nitrogen cooling.
<10nm
<10nm
<10nm
Table 1. Summary of process performance for
silicon micro- and nano-scale etching
Choice of processes
Angles <90° represent a tapered profile,
>90° a re-entrant profile
The primary controls of profile angle are the O2:SF6 gas flow ratio and the temperature. These parameters
determine the amount and volatility of the oxy-fluoride sidewall passivation respectively. Low temperature
and high O2:SF6 encourages a tapered profile. By balancing the parameters a vertical profile may be readily
achieved if that is the target. For instance, Figure 9 shows profile control by means of the O2 flow rate.
Figure 10 shows 20:1 aspect ratio silicon waveguides etched with the cryogenic process, while Figure 11
shows 0.1µm trenches etched to 1µm depth.
This process is useful when very high selectivity over a silicon dioxide insulator is required, such as for nanoscale MOSFETS [4] where the gate oxide is extremely thin. It is also a good choice for other SOI applications
where the selectivity demands are not so high because the process is free from notching effects at the siliconinsulator interface. Such applications include 2d-photonic crystals [2] where the addition of an insulator layer
such as silicon dioxide provides vertical confinement of light in the silicon (SiO2 having a lower refractive index
than Si). The HBr-based process has other benefits of smooth controllable profiles, high aspect ratio
capability and is very clean. Disadvantages are the need for the corrosive gas HBr, the relatively low etch
rate and the depth limitation (the profile becomes difficult to control much beyond 1µm depth).
Generally oxide masking is preferred as this yields very high selectivity (so that etching back at the top of the
silicon sidewall is unlikely), but a vertical resist mask may also be acceptable. The processing temperature is
around room temperature.
Cryo Si etch Profile vs O2 flow
Profile [degrees]
Hydrogen Bromide (HBr) based silicon-on-insulator (SOI) process
Courtesy of ITRI/MIRL, Taiwan
Cryogenic silicon etch process
Table 1 summarizes the process performance of the three process strategies as used for micro- and nanoscale etching of silicon. The processes are now further described and discussed mentioning advantages and
disadvantages of each.
A.
67
96
94
92
90
88
86
84
82
80
6
8
10
12
14
16
O2 flow rate [sccm ]
Figure 9 Cryogenic Si etch
Profile control by means of
the O2 flow rate in SF5
Figure 10 Cryogenic Si etch
0.5µm wide x 10µm deep
waveguides
Figure 11 Cryogenic Si etch
0.1µm gaps etched 1µm deep.
Aspect ratio 10:1
References
Oxygen substitution is used to raise selectivity of
silicon over SiO2. Figure 2 shows that extremely
high selectivities can be achieved once the O2
level reaches about 10%.
250
1500
200
1200
150
900
100
600
50
300
0
0
0
1
2
3
4
Selectivity PolySi:SiO2
Selectivity control
PolySi ER nm/min
1)
5
Oxygen flow rate [sccm]
Figure 2: Selectivity of polysilicon over SiO2
as a function of O2 flow in 50sccm HBr
a
PolySi ER
Sel Poly:SiO2
Oxford Instruments Plasma Technology, North End, Yatton, Bristol BS49 4AP, UK Tel +44 1934 837000,
Fax +44 1934 837001, e-mail [email protected]
b Advanced Microelectronic Center Aachen (AMICA), AMO GmbH, Huyskensweg 25, 52074, Aachen, Germany.
email [email protected]
[1] See http://www.physicsweb.org/article/world/13/8/9
[2] ‘Successful Fabrication of 2D Photonic Crystals’, Notomi et al, Research Activities in NTT Basic
Research Laboratories, Vol.11, August 2001.
[3] Finite-difference time-domain method for design and analysis of microcavity coupled submicron-width
silicon waveguides, Aroua et al, The European Physical Journal Applied Physics, Vol 17, Issue 3,
215-221, March 2002
[4] Highly selective etch process for silicon-on-insulator nano-devices, T.Wahlbrink, M.C.Lemme et al,
Microelectronic Engineering 78-79 (2005) 212 –217.
[5] High resolution ICP etching of 30nm lines and spaces in Tungsten and Silicon, A.L.Goodyear, D
Olynick et al. JVST. B 18 (6), Nov/Dec 2000
[6] Fabrication of silicon nanopillars using self-organized gold-chromium mask, V.Ovchinnikov et al
Material Science and Engineering B69-70 (2000) 459-463
[7] I.Rangelow, “Critical tasks in high aspect ratio silicon dry etching for microelectromechanical
systems,” J. Vac. Sci. Technol. A 21(4), Jul/Aug 2003.