Transcript Memory - Oakland University

Designing State Machines
Discussion D8.5
Section 13.9
Sequence Detectors
• Mealy and Moore Machines
• A Sequence Detector using D Flip-flops
• Verilog Program
Canonical Sequential Network
s(t+1)
next
state
State Register
x(t)
present
input
Combinational
Network
clr
clk
s(t)
present
state
present
z(t) output
Mealy Machine
s(t+1)
C1
x(t)
present
input
next
state
State Register
clr
clk
s(t)
present
state
z(t)
C2
Moore Machine
s(t+1)
C1
x(t)
present
input
next
state
State Register
clr
clk
z(t)
s(t)
present
state
C2
Verilog
Canonical Sequential Network
s(t+1)
next
state
State Register
x(t)
present
input
Combinational
Network
clr
clk
always @(present_state or x)
s(t)
present
state
present
z(t) output
always @(posedge clk or posedge clr)
Verilog
Mealy Machine
always @(present_state or x)
s(t+1)
C1
x(t)
present
input
next
state
State Register
clr
s(t)
present
state
always @(present_state or x)
clk
always @(posedge clk or posedge clr)
z(t)
C2
Verilog
Moore Machine
s(t+1)
C1
x(t)
present
input
next
state
State Register
clr
z(t)
s(t)
present
state
C2
always @(present_state or x)
clk
always @(present_state or x)
always @(posedge clk or posedge clr)
Sequence Detectors
• Mealy and Moore Machines
• A Sequence Detector using D Flip-flops
• Verilog Program
Example
Detect input sequence 1101
din
clk
fsm
dout
clr
din
dout
1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0
0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0
Creating a State Diagram
Detect input sequence 1101
0
S1
0
1
S0
0
0
S11
0
0
CLR
1
1
0
1
0
S1101
1
1
S110
0
Sequence Detectors
• Mealy and Moore Machines
• A Sequence Detector using D Flip-flops
• Verilog Program
seqdet.v
din
clk
seqdet
dout
clr
// Sequence detector -- Detect 1101
module seqdet(clk, clr, din, dout);
input clk, clr, din;
output dout;
reg dout;
seqdet.v
reg[2:0] present_state, next_state;
s(t+1)
C1
din
x(t)
present
input
next
state
State Register
init clr
z(t)
s(t)
present
state
C2
dout
clk
parameter S0 = 3'b000, S1 =3'b001, S11 = 3'b010,
S110 = 3'b011, S1101 = 3'b100;
seqdet.v
always @(posedge clk or posedge clr)
begin
if (clr == 1)
present_state <= S0;
else
present_state <= next_state;
end
s(t+1)
C1
din
x(t)
present
input
next
state
State Register
init clr
clk
z(t)
s(t)
present
state
C2
dout
seqdet.v
// C1: Next State
0
always @(present_state or din)
1
S0
begin
0
0
case(present_state)
S0: if(din == 1)
0
CLR
next_state <= S1;
0
else next_state <= S0;
S1101
S1: if(din == 1)
1
next_state <= S11;
1
else next_state <= S0;
S11: if(din == 0)
next_state <= S110;
else next_state <= S11;
S110: if(din == 1)
next_state <= S1101;
else next_state <= S0;
S1101: if(din == 0)
next_state <= S0;
else next_state <= S11;
default next_state <= S0;
endcase
end
S1
0
1
S11
0
1
S110
0
1
0
seqdet.v
s(t+1)
C1
din
x(t)
present
input
next
state
init clr
State Register
// C2: Outputs
always @(present_state)
begin
if(present_state == S1101)
dout <=1;
else
dout <= 0;
end
endmodule
clk
z(t)
s(t)
present
state
C2
dout
Detect input sequence 1101