Transcript Gain calibration of pipelined ADCs

FE8113 ”High Speed
Data Converters”
Part 2: Digital background
calibration
Papers 5 and 6
J.Keane et.al: “Background Interstage Gain Calibration Technique for Pipelined
ADCs”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol.
52,No. 1, January 2005, pp 32-43
J.Li, U-K.Moon: “Background Calibration Techniques for Multistage Pipelined
ADCs With Digital Redundancy”, IEEE Transactions on Circuits and Systems-II:
Analog and Digital Signal Processing, Vol. 50, No. 9, September 2003, pp 531538
J.Keane et.al: “Background Interstage Gain Calibration Technique for
Pipelined ADCs”
Outline: A background self-calibration technique is
proposed that can correct both linear and nonlinear
errors in the inter-stage amplifiers of pipeline and
algorithmic ADCs. Simulations show that the proposed
algorithm yields a 72dB SNDR and a 112dB SFDR for a
12-bit pipeline. The calibration tracking time constant is
approximately 8*105 samples
J.Keane et.al: “Background Interstage Gain Calibration Technique for
Pipelined ADCs”
Ideal N-bit ADC with input range (-Vref, Vref)
Assuming an ideal stage DASC, and an interstage gain of G1, the ADC
output is calculated by:
The interstage gain G1 and the M ADSC levels must satisfy the condition
M≥G1 to prevent the backend from overloading. Typically, M>G1,
introducing redundancy with digital correction. The primary remaining error
sources are errors in the interstage amplifier and nonmlinearity in the
DASC. In a switch-cap stage, DASC nonlinearity results primarily from
capacitor mismatch and can be measured and corrected for separately, as
presented by Galton. The remaining error source is the interstage
amplifier, and the paper describes how gain error and nonlinearity in these
can be measured an corrected for.
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Correction of gain errors, two approaches:
I:
II:
J.Keane et.al: “Background Interstage Gain
Calibration Technique for Pipelined ADCs”
With DASC
 output VDASC=K1D1Vref,
where K1 1 is the DASC gain, the
Input of a pipeline stage is
a)
b)
c)
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Equivalent model of pipeline stage
Output word:
where
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Interstage gain estimation
Allow at least two D1 levels for a given input
The output is then
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Define:
Then:
Multiply z by R:
If R is a pseudorandom sequence with zero mean, then RI(y0) will have zero mean. Then
E[Rz]=e, which is proportional to
Rz can be considered a noisy estimate of the error coefficient and used to adjust this:
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Equivalent model of pipeline stage including amplifier nonlinearity
(Weakly nonlinear)
Modified correction algorithm
Assuming ideal backend
Rewriting and simplifying
Assume
Adding test sequence
where
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Z written in general form
where
Multiplying by R
Comparing samples where
Is small to those where
is large gives an estimate of b1 independent of m1
However, this is depentent on backend behaviour. This means that tracking speed is
signal dependent
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Another technique that does nor rely on specific backend codes is presented.
By calculating covariance betrween Rz and
where
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Integrating over a large number of samples
Update equation
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Correction of backend errors
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
Example implementation
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
J.Keane et.al: “Background Interstage Gain Calibration
Technique for Pipelined ADCs”
J.Li, U-K.Moon: “Background Calibration Techniques for Multistage
Pipelined ADCs With Digital Redundancy”
Outline: The proposed digital background calibration
scheme, applicable to multistage ADCs, corrects the
linearity errors resulting from capacitor mismatches and
finite opamp gain. The calibration is achieved by
recalculating the digital output based on each stage’s
equivalent radix. The equivalent radices are extracted
in the background by using a digital correlation method.
The calibration technique takes advantage of the digital
redundancy architecture inherent to most pipelined
ADCs. The SNR is not degraded from the
pseudorandom noise sequence injected into the system
J.Li, U-K.Moon: “Background Calibration Techniques for Multistage
Pipelined ADCs With Digital Redundancy”
Introduction
- Correlation-based background digital calibration scheme in the
context of a 1.5b-per-stage pipelined or cyclic ADC
- The input signal need not be reduced to allow the injection of
pseudorandom calibration signal
- Minimal addition of analog hardware for calibration
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Capacitor flip-over MDAC
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Error sources
For cyclic:
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
”Non-capacitor-flip-over” MDAC
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Rearranging error terms for
capacitor flip-over MDAC
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Test signal injection
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Suggested implementaion of test signal injection
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Interference Cancelling
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Interference Cancelling
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Interference Cancelling
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Interference Cancelling
J.Li, U-K.Moon: “Background Calibration Techniques for
Multistage Pipelined ADCs With Digital Redundancy”
Simulation results