Transcript Chapter 2

C
S
D
A
2/e
Chapter 2: Machines, Machine
Languages, and Digital Logic
Instruction sets, SRC, RTN, and the mapping of register
transfers to digital logic circuits
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Bölüm 2: Makineler, Makine Dilleri, ve
Digital Logic
Komut kümeleri, SRC, RTN, ve register transfer eşlemelerinden
digital logic devrelere
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Chapter 2 Topics



2.1 Classification of Computers and Instructions
2.2 Kinds and Classes of Instruction Sets
2.3 Informal Description of the Simple RISC Computer, SRC




Students may wish to consult Appendix C, Assembly and
Assemblers for information about assemblers and assembly.
2.4 Formal Description of SRC using Register Transfer Notation
(RTN)
2.5 RTN Description of Addressing Modes
2.6 Register Transfers and Logic Circuits: from Behavior to
Hardware

Students may wish to consult Appendix A, Digital Logic for
additional information about Digital Logic circuits.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Bölüm 2 Konular



2.1 Bilgisayar ve Komutların Sınıflandırılması
2.2 Komut Kümeleri Çeşitleri ve Sınıfları
2.3 Basit RISC Bilgisayarların Biçimsel Olmayan Tarifi, SRC




Assembler ve assembly hakkında bilgi için Appendix C’ ye bakınız.
2.4 SRClerin Register Transfer Notation (RTN) kullanılarak
Biçimsel Tarifi
2.5 RTN Adresleme Şekillerinin Tarifi
2.6 Register Transfers ve Logic Devreler: from Behavior to
Hardware

Digital Logic devreler hakkında bilgi almak için Appendix A’ya
bakınız
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
What are the components of an ISA?
D
A
2/e  Sometimes known as The Programmers Model of the machine

Storage cells




The Machine Instruction Set




The instruction set is the entire repertoire of machine operations
Makes use of storage cells, formats, and results of the fetch/execute cycle
i. e. Register Transfers
The Instruction Format


General and special purpose registers in the CPU
Many general purpose cells of same size in memory
Storage associated with I/O devices
Size and meaning of fields within the instruction
The nature of the Fetch/Execute cycle

Things that are done before the operation code is known
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
Bir ISA’nın Bileşenleri Nedir?
D
A
2/e  Bazı zamanlar, makinenin Programcı Modeli olarak da bilinir

Depolama Hücreleri




Makine Komut Kümesi




Makine işlemlerinin hepsine komut kümesi denir.
Depolama hücrelerinin kullanılması, formatlanması ve fetch/execute
döngüsünün sonuçları
i. e. Register Transfers
Komut Biçimi


CPU da ki genel ve özel amaçlı register ları
Bellek de ki aynı boyut daki pek çok genel amaçlı hücreler
I/O aygıtları ile ilişkili depolama birimleri
Komutdaki alanların boyut ve anlamları
Fetch/Execute döngüsü

İşlem kodu bilinmeden önce yapılan şeyler
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
Fig. 2.1 Programmer’s Models of Various
S
Machines
D
A
2/eWe saw in Chap. 1 a variation in number and type of storage cells
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
Fig. 2.1 Programcı Modelinde ki Çeşitli
S
Makineler
D
A
2/e Bölüm 1’de pek çok varyasyonda depolama hücreleri gördük
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e

What Must an Instruction Specify?
Data Flow
Which operation to perform:




add r0, r1, r3
Again CPU register or memory cell
Location of next instruction

add r0, r1, r3
In CPU registers, memory cells, I/O locations, or part of instruction
Place to store result


Ans: Op code: add, load, branch, etc.
Where to find the operand or operands

add r0, r1, r3
add r0, r1, r3
br endloop
The default is usually memory cell pointed to by program counter—PC: the
next instruction in sequence
Sometimes there is no operand, or no result, or no next instruction. Can
you think of examples?
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e

Komut Ne Gibi Özellikleri İçerir?
Veri Akışı
Hangi işlemin gerçekleştirileceği:



add r0, r1, r3
CPU register, bellek hücreleri, I/O konumu, veya komutun bir parçası
Sonucun depolanacağı yer


Cevap: Op code: add, load, branch, etc.
Operand’ların nerden bulunacağı:

add r0, r1, r3
add r0, r1, r3
CPU register veya bellek hücreleri
Sonraki komutun yeri
add r0, r1, r3
br endloop
Genelde bellek hücreleri program counter tarafından işaret edilir.
PC: Sırdaki, sonraki komut


Bazen, operand, sonuç veya sonraki komut yoktur. Ne gibi örnekler
verilebilir?
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S Fig. 2.2 Accessing Memory—Reading from Memory
D
A
2/e
For a Memory Read:
CPU applies desired address to Address lines A0-An-1
CPU issues Read command, R
Memory returns the value at that address on Data lines D0-Db-1 and asserts
the COMPLETE signal
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.2 Belleğe Ulaşılması-Bellekden Okuma
For a Memory Read:
CPU istenen adresleri, Adres yollarına A0-An-1 uygular
CPU Read komutunu işler, R
Bellek adres deki değeri Data yollarından D0-Db-1 döndürür ve COMPLETE
sinyali yollar.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S Figure 2.2 Accessing Memory—Writing to Memory
D
A
2/e
For a Memory Write:
CPU applies desired address to Address lines A0-An-1 and and data to be written on
Data lines D0-Db-1
CPU issues Write command, W
Memory asserts the COMPLETE signal when the data has been written to memory.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Figure 2.2 Belleğe Ulaşılması-Belleğe Yazma
For a Memory Write:
CPU istenen adres bilgisinin Adres yollarından A0-An-1 ve yazılacak bilgi’yi de Data
yollarından gönderir D0-Db-1
CPU Write komutunu işler, W
Data belleğe yazıldıktan sonra, bellek COMPLETE sinyali yollar.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
Instructions Can Be Divided into 3 Classes
D
A
2/e Data movement instructions




Arithmetic and logic (ALU) instructions



Move data from a memory location or register to another memory location
or register without changing its form
Load—source is memory and destination is register
Store—source is register and destination is memory
Changes the form of one or more operands to produce a result stored in
another location
Add, Sub, Shift, etc.
Branch instructions (control flow instructions)


Any instruction that alters the normal flow of control from executing the
next instruction in sequence
Br Loc, Brz Loc2,—unconditional or conditional branches
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
Komutlar 3 Sınıfa Ayrılabilirler
D
A
2/e Bilgi (Data) Aktarma Komutları




Arithmetic ve logic (ALU) komutları



Bilginin bellekten veya register dan, başka bir bellek veya register a
biçiminin değiştirilmeden aktarımı
Load—Kaynak bellektir ve ulaşılacak yer ise register dır.
Store—Kaynak register dır ve ulaşılacak yer ise bellektir.
Bir veya daha fazla operand ın formunun değiştirilerek bir sonuç üretilip,
depolanmasını sağlayan komutlardır.
Add, Sub, Shift, etc.
Dallanma Komutları (control flow instructions)


Normal şekilde işleyen komut dizilerinin sırasının değiştirilmesi için
kullanılan komutlar.
Br Loc, Brz Loc2,—unconditional or conditional branches
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Tbl. 2.1 Examples of Data Movement
Instructions


Lots of variation, even with one instruction type
Notice differences in direction of data flow left-to-right or right-to-left
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Tbl. 2.1 Veri Aktarım Komutlarına Örnekler


Bir komut çeşidinin pek çok varyasyonu vardır.
Veri akışının yönündeki farklara dikkat edilmeli left-to-right veya
right-to-left
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Table 2.2 Examples of ALU
(Arithmetic and Logic Unit) Instructions
Instruction
MULF A, B, C
nabs r3, r1
ori $2, $1, 255
DEC R2
SHL AX, 4
Meaning
multiply the 32-bit floating point values at
mem loc’ns. A and B, store at C
Store abs value of r1 in r3
Store logical OR of reg $ 1 with 255 into reg $2
Decrement the 16-bit value stored in reg R2
Shift the 16-bit value in reg AX left by 4 bits
Machine
VAX11
PPC601
MIPS R3000
DEC PDP11
Intel 8086
Notice again the complete dissimilarity of both syntax and semantics
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Table 2.2 ALU (Arithmetic and Logic Unit)
Komut Örnekleri
Instruction
MULF A, B, C
Machine
VAX11
nabs r3, r1
Meaning
bellekten 32 bitlik floating point değerlerin
çarpılması. A ve B, C’ye depola
r1’in mutlak değeri r3’e depolanır
ori $2, $1, 255
DEC R2
SHL AX, 4
$1 reg’in 255 ile OR lanıp reg $2 ye depolanması
16-bitlik değeri azaltıp reg R2 ‘ye depola
reg AX deki 16 bitlik değeri 4 bit sola ötele
MIPS R3000
DEC PDP11
Intel 8086
PPC601
Sözdizimi ve anlamsal farklara dikkat edin
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Table 2.3 Examples of Branch Instructions
Instruction
BLSS A, Tgt
bun r2
beq $2, $1, 32
SOB R4, Loop
JCXZ Addr
Meaning
Machine
Branch to address Tgt if the least significant
VAX11
bit of mem loc’n. A is set (i.e. = 1)
Branch to location in R2 if result of previous
PPC601
floating point computation was Not a Number (NAN)
Branch to location (PC + 4 + 32) if contents
MIPS R3000
of $1 and $2 are equal
Decrement R4 and branch to Loop if R4  0
DEC PDP11
Jump to Addr if contents of register CX = 0.
Intel 8086
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Table 2.3 Dallanma Komut Örnekleri
Instruction
BLSS A, Tgt
Meaning
Eğer A bellek adresinin least significant biti
Machine
VAX11
set edildiyse(=1), Tgt adresine dallan
bun r2
beq $2, $1, 32
SOB R4, Loop
JCXZ Addr
eğer bir önceki işlemin sonucu sayı değilse
R2 konumuna dallan
Eğer $1 ve $2 nin içerikleri eşitse, (PC + 4 + 32)
konumuna dallan
Eğer R4  0 ise R4 ü azalt ve Loop a dallan
Eğer register CX=0 ise Addr e zıpla.
Computer Systems Design and Architecture Second Edition
PPC601
MIPS R3000
DEC PDP11
Intel 8086
© 2004 Prentice Hall
C
S
D
A
2/e
CPU Registers Associated with Flow of
Control—Branch Insts.



Program counter usually contains the address of, or "points to" the
next instruction
Condition codes may control branch
Branch targets may be contained in separate registers
Processor State
C N V Z
Program Counter
Condition Codes
•
•
•
Branch Targets
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
CPU Registers Associated with Flow of
Control—Branch Insts.



Program counter genelde bir sonraki komutun adresini içerir.
Durum Kodları(Condition codes) dallanmayı kontrol edebilir.
Branch targets may be contained in separate registers
Processor State
C N V Z
Program Counter
Condition Codes
•
•
•
Branch Targets
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
HLL Conditionals Implemented by Control Flow
S
Change
D
A
2/e


Conditions are computed by arithmetic instructions
Program counter is changed to execute only instructions
associated with true conditions
;the comparison
;conditional branch
;action if true
;action if false
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
HLL Conditionals Implemented by Control Flow
S
Change
D
A
2/e


Durumlar aritmetik komutlar tarafından hesaplanır.
Program counter sadece doğru durumlarla ilişkili komutların
işlenmesinde değiştirilir.
;karşılaştırma
;koşullu dallanma
;eğer doğru ise çalış
;eğer yanlış ise çalış
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
CPU Registers may have a “personality”


Architecture classes are often based on where the operands and
result are located and how they are specified by the instruction.
They can be in CPU registers or main memory
Stack
Arithmetic
Registers
Address
Registers
General Purpose
Registers
•
•
•
•
•
•
Push Pop
Top
Second
•
•
•
•
•
•
St ack Machine
Accumulat or
Computer Systems Design and Architecture Second Edition
Machine
General Regist er
Machine
© 2004 Prentice Hall
C
S
D
A
2/e
CPU Register Çeşitleri


Mimari sınıfları, genelde operandların ve sonuçların yerleşimine
ve komut tarafından nasıl belirtildiğine bağlıdır.
Bunlar CPU register ları veya ana bellek de olabilir.
Stack
Arithmetic
Registers
Address
Registers
General Purpose
Registers
•
•
•
•
•
•
Push Pop
Top
Second
•
•
•
•
•
•
St ack Machine
Accumulat or
Computer Systems Design and Architecture Second Edition
Machine
General Regist er
Machine
© 2004 Prentice Hall
C
S
3, 2, 1, & 0 Address Instructions
D
A
2/e The classification is based on arithmetic instructions that have two






operands and one result
The key issue is “how many of these are specified by memory
addresses, as opposed to being specified implicitly”
A 3 address instruction specifies memory addresses for both operands
and the result: R  Op1 op Op2
A 2 address instruction overwrites one operand in memory with the
result: Op2  Op1 op Op2
A 1 address instruction has a register, called the accumulator register
to hold one operand & the result (no address needed):
Acc  Acc op Op1
A 0 address uses a CPU register stack to hold both operands and the
result: TOS  TOS op SOS where TOS is Top Of Stack, SOS is
Second On Stack)
The 4-address instruction, hardly ever seen, also allows the address of
the next instruction to specified explicitly.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
3, 2, 1, ve 0 Adres Komutları
D
A
2/e Sınıflandırma, 2 operand ve 1 sonuç içeren aritmetik komutlara






dayanır.
The key issue is “how many of these are specified by memory
addresses, as opposed to being specified implicitly”
3 adresli komut 2 operand ve 1 result için bellek adresi belirtir:
R  Op1 op Op2
2 adresli komut sonucu bir operand ın üzerine yazar:
Op2  Op1 op Op2
1 adresli komut, 1 operand ve sonucu tutan accumulator register
denilen bir register e sahiptir (no address needed):
Acc  Acc op Op1
0 adres sonuç ve operand ı tutan CPU register yığınını kullanır:
TOS  TOS op SOS where TOS is Top Of Stack, SOS is Second On
Stack)
4 adresli komutta, ek olarak bir sonraki komutun adres bilgisine de yer
verilir.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.3 The 4 Address Instruction


Explicit addresses for operands, result & next instruction
Example assumes 24-bit addresses

Discuss: size of instruction in bytes
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.3 4 Adres Komutu


Operand, sonuç ve sonraki komut için kapalı adresler
Örneğin; 24-bit adrealer düşünün

Discuss: komutun boyutu (byte cinsinden)
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e

Fig 2.4 The 3 Address Instruction
Address of next instruction kept in a processor state register


the PC (Except for explicit Branches/Jumps)
Rest of addresses in instruction

Discuss: savings in instruction word size
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e

Fig 2.4 3 Adres Komutu
Bir sonraki komutun adresi işlemci durum register’ında tutulur


PC Program Counter (Except for explicit Branches/Jumps)
Komuttaki kalan diğer adresler

Tartışma: Komut boyutundaki tasarruf
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e



Fig. 2.5 The 2 Address Instruction
Be aware of the difference between address, Op1Addr, and data stored at that address,
Op1.
Result overwrites Operand 2, Op2, with result, Res
This format needs only 2 addresses in the instruction but there is less choice in placing data
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e



Fig. 2.5 2 Adres Komutu
Op1Addr adresi ve verinin depolandığı Op1 adresi arasındaki fark
Sonuç Res olarak Operand 2 Op2’ ye yazılır
Bu format sadece 2 adres bulundurur fakat verinin yerleştirileceği yer seçimi azdır.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.6 1 Address Instructions
We now need
instructions to load
and store
operands:
LDA OpAddr
STA OpAddr


Special CPU register, the accumulator, supplies 1 operand and stores result
One memory address used for other operand
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.6 1 Adres Komutu
Yükleme ve
depolama işlemleri
için komut a ihtiyaç
var:
LDA OpAddr
STA OpAddr


Özel CPU register ları, accumulator, 1 operand sağlarlar ve sonucu depolarlar
Diğer operand için bir bellek adresi kullanılır.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e



Fig. 2.7 The 0 Address Instruction
Uses a push down stack in CPU
Arithmetic uses stack for both operands. The result replaces them on the TOS
Computer must have a 1 address instruction to push and pop operands to and
from the stack
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e



Fig. 2.7 0 Adres Komutu
CPU daki push down yığını kullanılır.
Arithmetic her iki operand içinde yığını kullanır. The result replaces them on the
TOS
Bilgisayar yığın dan operandları çekmek ve eklemek için 1 adres komutuna
sahip olmalıdır.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Example 2.1 Expression evaluation for 3-0
address instructions.
Evaluate a = (b+c)*d-e for 3- 2- 1- and 0-address machines.


# of instructions & # of addresses both vary
Discuss as examples: size of code in each case
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Example 2.1 3-0 Adres Komutlarının İfade
Edilmesi
a = (b+c)*d-e işlemini 3- 2- 1- ve 0-adresli makineler için işleyin


Adreslerin ve komutların sayısı farklılık arz edebilir.
Tartışma:her durumda ki kod boyutu
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e




Fig. 2.8 General Register Machines
It is the most common choice in today’s general purpose computers
Which register is specified by small “address” (3 to 6 bits for 8 to 64 registers)
Load and store have one long & one short address: 1 1/2 addresses
2-Operand arithmetic instruction has 3 “half” addresses
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e




Fig. 2.8 Genel Register Makineleri
Günümüz genel amaçlı makinelerinin en yaygın tercih edilenleridir.
Register küçük adres ile belirtilir (3 to 6 bits for 8 to 64 registers)
Load ve store bir uzun ve bir kısa adrese sahiptir: 1 1/2 addresses
2-Operand arithmetic komutu 3 yarım adrese sahiptir
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Real Machines are Not So Simple



Most real machines have a mixture of 3, 2, 1, 0, 1 1/2 address
instructions
A distinction can be made on whether arithmetic instructions
use data from memory
If ALU instructions only use registers for operands and result,
machine type is load-store


Only load and store instructions reference memory
Other machines have a mixture of register-memory and
memory-memory instructions
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Gerçek Makineler oldukça Basit değildir.



Pek çok gerçek makine 3, 2, 1, 0, 1 1/2 address komutlarının
karışımına sahiptir.
Farklılık bellekten veri kullanan aritmetik komutlardan
oluşabilir.
Eğer ALU komutları operand ve sonuçlar için sadece register
kullanıyorsa, makine tipi load-store


Sadece load ve store komutları belleğe referans gösterir
Diğer makineler register-bellek ve bellek-bellek komutlarının
karışımına shiptirler.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e


Addressing Modes
An addressing mode is hardware support for a useful way of
determining a memory address
Different addressing modes solve different HLL problems



Some addresses may be known at compile time, e.g. global vars.
Others may not be known until run time, e.g. pointers
Addresses may have to be computed: Examples include:

Record (struct) components:


Array components:


variable base(full address) + const.(small)
const. base(full address) + index var.(small)
Possible to store constant values without using another memory cell by
storing them with or adjacent to the instruction itself.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e


Adresleme Şekilleri
Adresleme şekli, bellek adresinin kullanışlı bir şekilde belirlenmesi için
donanım desteğidir.
Farklı Adresleme şekilleri farklı HLL problemlerini çözer



Bazı adresler derleme zamanında bilinir. örneğin: global değişkenler.
Diğerleri çalışma zamanında bilinmeyebilir. örneğin: pointers
Adresler hesaplanabilir.Örneğin:

Kayıt (struct) Elemenları:


Dizi Elemanları:


variable base(full address) + const.(small)
const. base(full address) + index var.(small)
Sabit değişkenleri bir başka bellek hücresi kullanmadan, bitişik komutuyla
birlikte depolanması mümkündür.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e

HLL Examples of Structured Addresses
C language: rec -> count






Count
Rec 
C language: v[i]


rec is a pointer to a record: full address variable
count is a field name: fixed byte offset, say 24
v is fixed base address of array: full address constant
i is name of variable index: no larger than array size
Variables must be contained in registers or memory cells
Small constants can be contained in the instruction
Result: need for “address arithmetic.”

V[i]
V
E.g. Address of Rec -> Count is address of Rec + offset of
count.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e

HLL de Kalıplaşmış Adreslerin Örnekleri
C dili: rec -> count






Count
Rec 
C dili: v[i]


rec bir kayıta işaretçidir: full address variable
count alan adıdır: fixed byte offset, say 24
v dizi adresinin başlangıç noktasıdır: full address constant
i değişken dizininin ismidir: dizi boyutundan büyük olamaz
Değişkenler register veya bellek hücrelerinde tutulur
Küçük sabitler komutlarda tutulabilir
Sonuç: need for “address arithmetic.”

V[i]
V
E.g. Address of Rec -> Count is address of Rec + offset of
count.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig 2.9 Common Addressing Modes a-d
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig 2.9 Common Addressing Modes e-g
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.10a Example Computer, SRC
Simple RISC Computer



32 general purpose registers of 32 bits
32 bit program counter, PC and instruction register (IR)
232 bytes of memory address space
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.10a Örnek Bilgisayar, SRC Basit RISC
Bilgisayarı



32 bitlik 32 genel amaçlı register
32 bitlik program counter, PC ve instruction register (IR)
232 byte lık bellek adres alanı
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e








SRC Characteristics
(=) Load-store design: only way to access memory is through load and store
instructions
(–) Operation on 32-bit words only, no byte or half-word operations.
(=) Only a few addressing modes are supported
(=) ALU Instructions are 3-register type
(–) Branch instructions can branch unconditionally or conditionally on whether
the value in a specified register is = 0, <> 0, >= 0, or < 0.
(–) Branch-and-link instructions are similar, but leave the value of current PC
in any register, useful for subroutine return.
(–) Can only branch to an address in a register, not to a direct address.
(=) All instructions are 32-bits (1-word) long.
(=) – Similar to commercial RISC machines
(–) – Less powerful than commercial RISC machines.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e








SRC Karakteristikleri
(=) Load-store tasarımı: belleğe ulaşım sadece load ve store komutlarıyla
sağlanır.
(–) işlemler 32 bitlik word lerdedir, byte veya half-word işlemleri yoktur.
(=) Sadece birkaç adresleme şekli desteklenir.
(=) ALU komutları 3-register tiplidir
(–) Dallanma komutları koşullu veya koşulsuz olarak registerda belirlenen
değerin = 0, <> 0, >= 0, or < 0 durumlarına göre dallanabilir.
(–) dallanma-ve-bağlantı komutları benzerdir, but leave the value of current
PC in any register, useful for subroutine return.
(–) sadece, register daki adrese dallanabilir, direk adrese değil.
(=) Bütün komutlar 32-bitlik(1 word) uzunluğundadır.
(=) – Ticari RISC makinelerine benzerdir
(–) – ticari RISC makinelerine göre daha güçsüzdür
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
SRC Basic Instruction Formats



There are three basic instruction format types
The number of register specifier fields and length of the
constant field vary
Other formats result from unused fields or parts
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Basit SRC Komut Formatları



3 basit komut format tipi vardır.
Register belirtme alanları ve sabit alanlarının uzunluğu
değişiklik gösterebilir.
Kullanılmayan alan ve parçalardan diğer formatlar sonuçları
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig 2.10 cont'd. SRC instructions (1)
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig 2.10 cont'd. SRC instructions (2)
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Tbl 2.4 Example Load & Store Instructions:
Memory Addressing


Address can be constant, constant+register, or constant+PC
Memory contents or address itself can be loaded
Instruction
ld r1, 32
ld r22, 24(r4)
st r4, 0(r9)
la r7, 32
ldr r12, -48
lar r3, 0
op
1
1
3
5
2
6
ra
1
22
4
7
12
3
rb
0
4
9
0
–
–
c1
32
24
0
32
-48
0
Meaning
R[1]  M[32]
R[22]  M[24+R[4]]
M[R[9]]  R[4]
R[7]  32
R[12]  M[PC -48]
R[3]  PC
Addressing Mode
Direct
Displacement
Register indirect
Immediate
Relative
Register (!)
(note use of la to load a constant)
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Tbl 2.4 Load & Store Komutlarına Örnekler:
Bellek Adresleme


Adres constant, constant+register, veya constant+PC şeklinde
olabilir.
Bellek içerikleri veya adresler kendi yüklenebilir.
Instruction
ld r1, 32
ld r22, 24(r4)
st r4, 0(r9)
la r7, 32
ldr r12, -48
lar r3, 0
op
1
1
3
5
2
6
ra
1
22
4
7
12
3
rb
0
4
9
0
–
–
c1
32
24
0
32
-48
0
Meaning
R[1]  M[32]
R[22]  M[24+R[4]]
M[R[9]]  R[4]
R[7]  32
R[12]  M[PC -48]
R[3]  PC
Addressing Mode
Direct
Displacement
Register indirect
Immediate
Relative
Register (!)
(note use of la to load a constant)
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Assembly Language Forms of Arithmetic and
Logic Instructions
Format
neg ra, rc
not ra, rc
add ra, rb, rc
sub ra, rb, rc
and ra, rb, rc
or ra, rb, rc
addi ra, rb, c2
andi ra, rb, c2
ori ra, rb, c2

Example
neg r1, r2
not r2, r3
add r2, r3, r4
addi r1, r3, 1
Meaning
;Negate (r1 = -r2)
;Not (r2 = r3´ )
;2’s complement addition
;2’s complement subtraction
;Logical and
;Logical or
;Immediate 2’s complement add
;Immediate logical and
;Immediate logical or
Immediate subtract not needed since constant in addi may be
negative
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Aritmetik ve Logic Komutlarının Assembly
Dilindeki Formları
Format
neg ra, rc
not ra, rc
add ra, rb, rc
sub ra, rb, rc
and ra, rb, rc
or ra, rb, rc
addi ra, rb, c2
andi ra, rb, c2
ori ra, rb, c2

Example
neg r1, r2
not r2, r3
add r2, r3, r4
addi r1, r3, 1
Meaning
;Negate (r1 = -r2)
;Not (r2 = r3´ )
;2’nin tümleyeni toplama
;2’nin tümleyeni çıkarma
;Mantıksal ve
;mantıksal veya
;Immediate 2’nin tümleyeni topla
;Immediate mantıksal ve
;Immediate mantıksal veya
(Immediate)Hemen çıkarma ya ihtiyaç yoktur, çünkü addi de ki
sabit negatif olabilir
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Branch Instruction Format
There are actually only two branch op codes:
br rb, rc, c3<2..0>
;branch to R[rb] if R[rc] meets
; the condition defined by c3<2..0>
brl ra, rb, rc, c3<2..0>
; R[ra]  PC; branch as above
• It is c3<2..0>, the 3 lsbs of c3, that governs what the branch condition is:
lsbs
000
001
010
011
100
101
condition
never
always
if rc = 0
if rc  0
if rc ≥ 0
if rc < 0
Assemly lang form
brlnv
br, brl
brzr, brlzr
brnz, brlnz
brpl, brlpl
brmi, brlmi
Example
brlnv r6
br r5, brl r5
brzr r2, r4
• Note that branch target address is always in register R[rb].
•It must be placed there explicitly by a previous instruction.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Dallanma Komutları Formatı
Sadece iki dallanma opcode u vardır:
br rb, rc, c3<2..0>
brl ra, rb,
;R[rb] ye dallan eger R[rc]
c3<2..0> deki şartla uyuşuyorsa
rc, c3<2..0>
; R[ra]  PC; yukardaki gibi dallan
• It is c3<2..0>, the 3 lsbs of c3, dallanma şartının ne olduğunu yönetir:
lsbs
000
001
010
011
100
101
condition
never
always
if rc = 0
if rc  0
if rc ≥ 0
if rc < 0
Assemly lang form
brlnv
br, brl
brzr, brlzr
brnz, brlnz
brpl, brlpl
brmi, brlmi
Example
brlnv r6
br r5, brl r5
brzr r2, r4
• Dallanma hedefi adresi genelde R[rb] register ındadır.
•It must be placed there explicitly by a previous instruction.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
STable 2.6 Dallanma Komutları(Branch Instruction) Examples
D
A Ass’y Example instr. Meaning
op ra
rb rc c3
Branch
2/e lang.
2..0 Cond’n.
brlnv
br
brl
brlnv r6
br r4
brl r6,r4
brzr
brzr r5,r1
brlzr
brnz
brlnz
brlzr r7,r5,r1
brnz r1, r0
brlnz r2,r1,r0
brpl
brlpl
brpl r3, r2
brlpl r4,r3,r2
brmi
brlmi
brmi r0, r1
brlmi r3,r0,r1
R[6]  PC
PC  R[4]
R[6]  PC;
PC  R[4]
if (R[1]=0)
PC  R[5]
R[7]  PC;
if (R[0]0) PC R[1]
R[2]  PC;
if (R[0]0) PC R[1]
if (R[2]•0) PC R[3]
R[4]  PC;
if (R[2]•0) PC R[3]
if (R[1]<0) PC R[0]
R[3]  PC;
if (r1<0) PC R[0]
Computer Systems Design and Architecture Second Edition
9
8
9
6
—
6
—
4
4
— 000
— 001
— 001
never
always
always
8
—
5
1
010
zero
9
8
9
7
—
2
5
1
1
1
0
0
010
011
011
zero
nonzero
nonzero
8
9
—
4
3
3
2
2
100
plus
plus
8
9
—
3
0
0
1
1
101
minus
minus
© 2004 Prentice Hall
C
S
D
A
2/e
Dallanma Komutları(Branch Instructions)—Example
C: goto Label3
SRC:
lar r0, Label3
br r0
• • •
Label3
; put branch target address into tgt reg.
; and branch
•••
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Example of conditional branch
in C: #define Cost 125
if (X<0) then X = -X;
in SRC:
Cost .equ 125
;define symbolic constant
.org 1000
;next word will be loaded at address 100010
X:
.dw 1
;reserve 1 word for variable X
.org 5000
;program will be loaded at location 500010
lar r31, Over
;load address of “false” jump location
ld
r1, X
;load value of X into r1
brpl r31, r1
;branch to Else if r1≥0
neg r1, r1
;negate value
Over: • • •
;continue
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Koşullu dallanma örnekleri
in C: #define Cost 125
if (X<0) then X = -X;
in SRC:
Cost .equ 125
;sembolik sabit tanımla
.org 1000
;sonraki word 100010 adresine yüklenir
X:
.dw 1
;X değişkeni için 1 word ayrılır
.org 5000
; 500010 konumuna program yüklenir.
lar r31, Over
;load address of “false” jump location
ld
r1, X
;X in değerini r1 e yükle
brpl r31, r1
; Else if r1≥0 se dallan
neg r1, r1
;değeri negatifle
Over: • • •
;devam et
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
RTN (Register Transfer Notation)








Provides a formal means of describing machine structure and
function
Is at the “just right” level for machine descriptions
Does not replace hardware description languages.
Can be used to describe what a machine does (an Abstract RTN)
without describing how the machine does it.
Can also be used to describe a particular hardware
implementation (A Concrete RTN)
At first you may find this “meta description” confusing, because it
is a language that is used to describe a language.
You will find that developing a familiarity with RTN will aid greatly
in your understanding of new machine design concepts.
We will describe RTN by using it to describe SRC.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
RTN (Register Transfer Notation)








Makine yapısı ve fonksiyonlarının tanımlanmasında biçimsel bir
araç sağlar
Makine tanımlanması için “just right” düzeyindedir.
Donanım tanımlama dili ile yer değiştirilmez.
Makinenin bir şeyi nasıl yaptığına değinmeden, ne yaptığının
tanımlanmasında kullanılır. (an Abstract RTN)
Belirli Donanım implementasyonunun tanımlanmasında da
kullanılabilir (A Concrete RTN)
İlk bakışta bu “meta description”’ı karışık bulabilirsiniz, çünkü bu
bir dili tanımlamada kullanılan dildir.
You will find that developing a familiarity with RTN will aid greatly
in your understanding of new machine design concepts.
We will describe RTN by using it to describe SRC.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Some RTN Features
Using RTN to describe a machine’s static properties
Static Properties

Specifying registers


IR31..0 specifies a register named “IR” having 32 bits numbered 31 to 0
“Naming” using the := naming operator:


op4..0 := IR31..27 specifies that the 5 msbs of IR be called op, with bits 4..0.
Notice that this does not create a new register, it just generates another name,
or “alias” for an already existing register or part of a register.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Bazı RTN Özellikleri
Makinenin static özelliklerinin tanımlanmasında RTN
kullanılması
Static Özellikler

Regiter ları Belirleme


IR31..0 IR isminde 31 den 0 a numarandırılmış 32 bitlik bir register ı belirtir
“İsimlendirme” := isimlendirme işlemi kullanılır:


op4..0 := IR31..27 IR ın 5 msbs si op denilen 4..0 a bitleri belirtir.
Bu yeni bir register oluşturma değildir, sadece yeni bir isim oluşturmadır veya
mevcut olan register ın veya bir parçasının isimlendirilmesidir.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Using RTN to Describe
Dynamic Properties
Dynamic Properties
• Conditional expressions:
(op=12)  R[ra]  R[rb] + R[rc]:
“if” condition “then”
; defines the add instruction
RTN Assignment Operator
This fragment of RTN describes the SRC add instruction. It says,
“when the op field of IR = 12, then store in the register specified
by the ra field, the result of adding the register specified by the
rb field to the register specified by the rc field.”
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Dinamic Özelliklerin Tanımlanmasında RTN
Kullanılması
Dynamic Özellikler
• Koşullu İfadeler:
(op=12)  R[ra]  R[rb] + R[rc]:
“eger” koşul “sonra”
; toplama(add) komutunu belirtir
RTN Assignment Operator
Bu RTN parçası SRC de toplama(add) ifadesini tanımlar.
“IR ın op alanı 12 ise, rc alanıyla belirtilmiş register ile
rb alanıyla belirlenmiş register ı toplayıp, sonucu ra alanı ile
Belirlenmiş register a depolanır.”
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Using RTN to Describe the SRC (static)
Processor State
Processor state
PC31..0:
program counter
(memory addr. of next inst.)
IR31..0:
instruction register
Run:
one bit run/halt indicator
Strt:
start signal
R[0..31]31..0: general purpose registers
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
SRC yi tanımlamada RTN kullanılması (static)
İşlemci Durumu
İşlemi Durumu
PC31..0:
program counter(program sayıcı)
(bir sonraki komutun bellek adresi)
IR31..0:
instruction register(komut register ı)
Run:
bir bit run/halt belirleyici
Strt:
başlama sinyali
R[0..31]31..0: genel amaçlı register lar
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
RTN Register Declarations


General register specifications shows some features of the
notation
Describes a set of 32 registers of 32-bit with names R[0] to R[31]
R[0..31]31..0:
Name of
registers
Register #
in square
brackets
Colon separates
statements with
no ordering
msb #
.. specifies
a range of
indices
Computer Systems Design and Architecture Second Edition
lsb#
Bit # in
angle
brackets
© 2004 Prentice Hall
C
S
D
A
2/e
RTN Register Açıklaması


Genel register belirtimi, bazı notasyon özelliklerini gösterir.
R[0] dan R[31] e adlandırılmış 32 bitlik 32 tane register
kümesinin tanımlanması
R[0..31]31..0:
Register’ın
ismi
Köşeli
parantezlerde
Register
sayısı .. aralık
Colon separates
statements with
no ordering
msb #
ifade edilir
Computer Systems Design and Architecture Second Edition
lsb#
Bit numarları
açılı
parantezlerde
gösterilir
© 2004 Prentice Hall
C
S
D
A
2/e
Memory Declaration:
RTN Naming Operator


Defining names with formal parameters is a powerful
formatting tool
Used to define word memory (big endian)
Main memory state
Mem[0..232 - 1]7..0: 232 addressable bytes of memory
M[x]31..0 := Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]:
Dummy
parameter
Naming
operator
Computer Systems Design and Architecture Second Edition
Concatenation
operator
All bits in
register if no
bit index given
© 2004 Prentice Hall
C
S
D
A
2/e
Bellek Açıklaması:
RTN İsimlendirme İşlemi


Biçimsel parametreler ile isimlerin belirlenmesi, güçlü
biçimlendirme aracıdır
Word belleğinin belirlenmesinde kullanılır(big endian)
Ana Bellek Durumu
Mem[0..232 - 1]7..0: 232 addressable bytes of memory
M[x]31..0 := Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]:
Dummy
parameter
İsimlendirme
işlemcisi
Computer Systems Design and Architecture Second Edition
Birleştirme
İşlemcisi
All bits in
register if no
bit index given
© 2004 Prentice Hall
C
S
D
A
2/e
RTN Instruction Formatting Uses Renaming of
IR Bits
Instruction formats
op4..0 := IR31..27:
ra4..0 := IR26..22:
rb4..0 := IR21..17:
rc4..0 := IR16..12:
c121..0 := IR21..0:
c216..0 := IR16..0:
c311..0 := IR11..0:
Computer Systems Design and Architecture Second Edition
operation code field
target register field
operand, address index, or
branch target register
second operand, conditional
test, or shift count register
long displacement field
short displacement or
immediate field
count or modifier field
© 2004 Prentice Hall
C
RTN Komutlarının şekillendirilmesinde IR
S
Bitlerini yeniden isimlendirilmesinin kullanılması
D
A
2/e
Komut Formatları
op4..0 := IR31..27:
ra4..0 := IR26..22:
rb4..0 := IR21..17:
rc4..0 := IR16..12:
c121..0 := IR21..0:
c216..0 := IR16..0:
c311..0 := IR11..0:
Computer Systems Design and Architecture Second Edition
İşlem kodu alanı
Hedef register alanı
operand, address index veya
dallanma hedef register
ikinci operand, koşul testi
veya öteleme sayaç register
uzun yer değişim alanı
kısa yer değişim veya
immediate alanı
sayaç veya güncelleme alanı
© 2004 Prentice Hall
C
S
D
A
2/e
Assembly Language for Shift

Form of assembly language instruction tells whether to set c3=0
shr ra, rb, rc
shr ra, rb, count
shra ra, rb, rc
shra ra, rb, count
shl ra, rb, rc
shl ra, rb, count
shc ra, rb, rc
shc ra, rb, count
;Shift rb right into ra by 5 lsbs of rc
;Shift rb right into ra by 5 lsbs of inst
;AShift rb right into ra by 5 lsbs of rc
;AShift rb right into ra by 5 lsbs of inst
;Shift rb left into ra by 5 lsbs of rc
;Shift rb left into ra by 5 lsbs of inst
;Shift rb circ. into ra by 5 lsbs of rc
;Shift rb circ. into ra by 5 lsbs of inst
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Öteleme için Assembly Dili

Form of assembly language instruction tells whether to set c3=0
shr ra, rb, rc
shr ra, rb, count
shra ra, rb, rc
shra ra, rb, count
shl ra, rb, rc
shl ra, rb, count
shc ra, rb, rc
shc ra, rb, count
;rc nin 5 lsbs i kadar rb yi ra ya sağa ötele
;count un 5 lsbs i kadar rb yi ra ya sağa ötele
;rc nin 5 lsbs i kadar rb yi ra ya sağa ötele
;count un 5 lsbs i kadar rb yi ra ya sağa ötele
; rc nin 5 lsbs i kadar rb yi ra ya sola ötele
; count un 5 lsbs i kadar rb yi ra ya sola ötele
; rc nin 5 lsbs i kadar rb yi ra ya dairesel ötele
; count un 5 lsbs i kadar rb yi ra ya dairesel ötele
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig 2.11 RTN’in SRC ile Bağlantısı
(The Relationship of RTN to SRC)
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e



A Note about Specification Languages
They allow the description of what without having to specify how.
They allow precise and unambiguous specifications, unlike natural language.
They reduce errors:




errors due to misinterpretation of imprecise specifications written in natural language
errors due to confusion in design and implementation - “human error.”
Now the designer must debug the specification!
Specifications can be automatically checked and processed by tools.


An RTN specification could be input to a simulator generator that would produce a
simulator for the specified machine.
An RTN specification could be input to a compiler generator that would generate a
compiler for the language, whose output could be run on the simulator.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e



Özelleştirilmiş Diller ile İlgili Özellikler
İşlemlerin nasıl gerçekleştiğini belirtmeden, ne gerçekleştirdiğinin anlatılmasını
sağlarlar.
Kesin ve açık tanımlama sağlarlar, doğal dillerden farklı olarak
Hataları azaltırlar:




Doğal dillerde yazılan kesin olmayan tanımlamaların yanlış yorumlanmasından doğan
hatalar
İmplementasyon ve tasarım da ki karışıklıklarda doğan hatalar - “insan hatası.”
Şimdi tasarımcı tanımlamaları hata ayıklamalıdır!
Tanımlamalar otomatik olarak kontrol edilebilir ve araçlar tarafından işlenebilir.


RTN tanımlaması, belirli makine için simülatör üreten simülatör üreticisine girdi(input)
olabilir.
RTN tanımlaması, çıktısı(output) simülatörde çalıştırılan dil için derleyici oluşturan
derleyici oluşturucusuna girdi(input) olabilir.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S Addressing Modes Described in RTN (Not SRC)
D
A
2/e
Mode name
Register
Register indirect
Immediate
Direct, absolute
Indirect
Indexed, based,
or displacement
Relative
Autoincrement
Autodecrement
Target register
Use
Assembler
Syntax
Ra
(Ra)
#X
X
(X)
X(Ra)
RTN meaning
X(PC)
(Ra)+
- (Ra)
R[t]  M[X + PC]
Vals stored w pgm
R[t]  M[R[a]]; R[a]  R[a] + 1
Sequential
R[a]  R[a] - 1; R[t]  M[R[a]]
access.
Computer Systems Design and Architecture Second Edition
R[t]  R[a]
R[t]  M[R[a]]
R[t]  X
R[t]  M[X]
R[t]  M[ M[X] ]
R[t]  M[X + R[a]]
Tmp. Var.
Pointer
Constant
Global Var.
Pointer Var.
Arrays, structs
© 2004 Prentice Hall
C
S
D
A
2/e
RTN de Tanımlanmış Adresleme Şekilleri (Not SRC)
Mode name
Register
Register indirect
Immediate
Direct, absolute
Indirect
Indexed, based,
or displacement
Relative
Autoincrement
Autodecrement
Hedef Register
Kullanım
Assembler
Söz dizimi
Ra
(Ra)
#X
X
(X)
X(Ra)
RTN anlamı
X(PC)
(Ra)+
- (Ra)
R[t]  M[X + PC]
Vals stored w pgm
R[t]  M[R[a]]; R[a]  R[a] + 1
Ardışık
R[a]  R[a] - 1; R[t]  M[R[a]]
uerişim
Computer Systems Design and Architecture Second Edition
R[t]  R[a]
R[t]  M[R[a]]
R[t]  X
R[t]  M[X]
R[t]  M[ M[X] ]
R[t]  M[X + R[a]]
Tmp. Var.
Pointer(İşaretçi)
Constant(Sabit)
Global Değişken
İşaretçi Değişken
Diziler, structs
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.12 Register transferinin Digital Logic Devrede
Gösterimi

Implementing the RTN statement A  B
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.13 Çoklu Bit Register Transferi

Implementing Am..1  Bm..1
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.14 Logic Kapılarıyla Veri Aktarımının
Gösterilemsi

Logic kapıları veri aktarımının kontrolünde kullanılır:
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.15 Multiplexer as a 2 Way Gated Merge

Data from multiple sources can be selected for transmission
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.15 2 Yol Kapısının Bileştirildiği Çoklayıcılar

Çoklu kaynaklardan gelen verinin aktarın için seçilebilmesi
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e

Fig. 2.16 m-bit Multiplexer and Symbol
Multiplexer gate signals Gi may be produced by a binary to one-out-of-n decoder
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e

Fig. 2.16 m-bit Çoklayıcı ve Sembolü
Çoklayıcı kapı sinyali Gi, a binary to one-out-of-n decoder tarafından oluşturulabilir.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.17 Separating Merged Data


Merged data can be separated by gating at the right time
It can also be strobed into a flip-flop when valid
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.17 Birleştirilmiş Verinin Ayrılması


Birleştirilmiş veri doğru zamanda kapılanarak ayrıştırılabilir.
It can also be strobed into a flip-flop when valid
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
Fig. 2.18 Multiplexed Register Transfers using
S
Gates and Strobes
D
A
2/e


Selected gate and strobe determine which Register is Transferred to where.
AC, and BC can occur together, but not AC, and BD
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.18 Kapı ve stroboskop kullanılarak
Multiplexed Register Transferi


Seçilen kapı ve strobe, hangi register ın nereye transfer olacağına karar verir.
AC, ve BC birlikte olabilir, fakat AC, ve BD olmaz
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.19 Open-Collector NAND Gate Output
Circuit
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.20 Wired AND Connection of OpenCollector Gates
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.21 Open Collector Wired OR Bus




DeMorgan’s OR by not of AND of nots
Pull-up resistor removed from each gate - open collector
One pull-up resistor for whole bus
Forms an OR distributed over the connection
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.22 Tri-state Gate Internal Structure and
Symbol
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e



Fig. 2.23 Registers Connected by a
Tri-state Bus
Can make any register transfer R[i]R[j]
Can’t have Gi = Gj = 1 for i≠j
Violating this constraint gives low resistance path from power supply to
ground—with predictable results!
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e



Fig. 2.23 Tri-state Veri yolu ile Bağlanmış
Register lar
Herhangi register transferi gerçekleştirilebilir R[i]R[j]
Can’t have Gi = Gj = 1 for i≠j
Bu sınırlamaları bozmak güç kaynağından toprağa düşük dirençli yol
verir.—tahmin edilebilir sonuçlar ile!
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.24 Registers and Arithmetic Connected
by One Bus
Example
Abstract RTN
R[3]  R[1]+R[2];
Concrete RTN
Y  R[2];
Z  R[1]+Y;
R[3]  Z;
Combinational
Logic—no
memory
Control Sequence
R[2]out, Yin;
R[1]out, Zin;
Zout, R[3]in;
Notice that what could be described in one step in the abstract RTN took
three steps on this particular hardware
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Fig. 2.24 Tek Yolla Register lar ve Aritmetik
Bağlantısı
Örnek
Soyut RTN
R[3]  R[1]+R[2];
Somut RTN
Y  R[2];
Z  R[1]+Y;
R[3]  Z;
Bağlantısal
Logic—bellek
yok
Kontrol Serisi
R[2]out, Yin;
R[1]out, Zin;
Zout, R[3]in;
Soyut RTN da tek aşamada tanımlananlar, donanımda üç aşamada
gerçekleştiğine dikkat ediniz
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S
D
A
2/e
Figure 2.25 Timing of the Register Transfers

Discuss: difference
between gating
signals and strobing
signals

Discuss factors
influencing
minimum clock
period.
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall
C
S Figure 2.2 Register Transferinin Zamanlanması
D
A
2/e


Tartışma: kapılama
sinyalleri ile strobe
sinyalleri arasındaki
farklar
Minimum clock
perioduna etki eden
faktörleri tartışma
Computer Systems Design and Architecture Second Edition
© 2004 Prentice Hall