Transcript EET 251 Unit 2 - PEOPLE.SINCLAIR.EDU

EET 1131 Unit 11
Counter Circuits



Read Kleitz, Chapter 12, skipping
Sections 12-10 and 12-11.
Homework #11 and Lab #11 due next
week.
Quiz next week.
Counting in Binary
As you know, the binary count sequence follows a
familiar pattern of 0’s and 1’s as described in
Section 2-2 of the text.
000
001
010
011
100
The next bit changes on
101
every fourth number.
110
111
LSB changes on every
number.
The next bit changes
on every other number.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Counting in Binary
A counter can form the same pattern of 0’s and 1’s with
logic levels. The first stage in the counter represents the
least significant bit – notice that these waveforms follow
the same pattern as counting in binary.
LSB
MSB
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
1
0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Synchronous versus Asynchronous

1.
2.
The synchronous/asynchronous
distinction has different meanings:
As applied to inputs: A change on a
synchronous input doesn’t affect the
outputs until the next active clock edge,
but a change on an asynchronous input
affects the outputs immediately.
As applied to counters: in a synchronous
counter, the outputs can all change at the
same instant; but in an asynchronous
counter, there’s a brief delay between the
changing of the outputs.
Three bit Asynchronous Counter
In an asynchronous counter, the clock is applied only to
the first stage. Each subsequent stage gets its clock from
the previous stage.
The asynchronous counter shown is a three-bit counter (also
called MOD-8 counter or divide-by-8 counter). It uses J-K flipflops in the toggle mode.
HIGH
Q0
J0
CLK
C
K0
Q1
J1
C
Q0
K1
Q2
J2
C
Q1
K2
Waveforms are on the following slide…
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Three bit Asynchronous Counter
Notice that the Q0 output is triggered on the rising edge of
the clock signal. The following stage is triggered from Q0.
The rising edge of Q0 is equivalent to the falling edge of Q0.
The resulting sequence is that of a 3-bit binary up counter.
1
CLK
2
3
4
5
6
7
8
Q0
0
1
0
1
0
1
0
1
0
Q1
0
0
1
1
0
0
1
1
0
Q2
0
0
0
0
1
1
1
1
0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Propagation Delay
Asynchronous counters are sometimes called ripple
counters, because the stages do not all change together.
For certain applications requiring high clock rates, this is
a major disadvantage.
Notice how delays
are cumulative as
each stage in a
counter is clocked
later than the
previous stage.
CLK
1
2
3
4
Q0
Q1
Q2
Q0 is delayed by 1 propagation delay, Q1 by 2 delays and Q2 by 3 delays.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The 74LS93 Asynchronous Counter
The 74LS93 has one independent toggle J-K flip-flop
driven by CLK A and three toggle J-K flip-flops that form
an asynchronous counter driven by CLK B.
The counter can be extended to form a 4-bit counter by connecting
Q0 to the CLK B input. Two inputs are provided that clear the count.
CLK B
(1)
J
CLK A
(14)
J1
C
K0
All J and K inputs
are connected
internally HIGH
RO (1)
RO (2)
J2
J3
0
C
C
C
K1
K2
K3
(2)
(3)
(12)
Q0
(9)
Q1
(8)
Q2
(11)
Q3
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Some Asynchronous Counter ICs

7490 Four bit decade counter (MOD 10)

7492 Four bit divide-by-12 counter (MOD
12)

7493 Four bit binary counter (MOD 16)
Asynchronous Decade Counter
This counter uses a NAND gate to recycle the count
sequence to zero after the 1001 state, resulting in a
MOD-10 counter (or decade counter). Other truncated
sequences can be obtained using a similar technique.
CLR
HIGH
J0
CLK
C
K0
Q0
Q1
J1
J2
Q2
J3
C
C
C
K1
K2
K3
Q3
Waveforms are on the following slide…
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Asynchronous Decade Counter
When Q1 and Q3 are HIGH together, the counter is
cleared by a “glitch” on the CLR line.
CLK
1
2
3
4
5
6
7
8
9
10
Q0
Q1
Glitch
Glitch
Q2
Q3
CLR
Glitch
Glitch
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
BCD Decoder/Driver
A special-purpose decoder is the 7447. This is a BCD-toseven segment display with active LOW outputs.
VCC
(16)
The a-g outputs are
designed for much
higher current than most
devices (hence the word
driver in the name).
BCD/7-seg
BI/RBO
BCD
inputs
LT
RBI
(7)
(1)
(2)
(6)
(3)
(5)
a
b
c
d
e
f
g
1
2
4
8
LT
RBI
74LS47
(4)
(13)
(12)
(11)
(10)
(9)
(15)
(14)
BI/RBO
Outputs
to seven
segment
device
(8)
GND
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
BCD Decoder/Driver
Here the 7447 is an connected to an LED seven segment
display. Notice the current-limiting resistors, required to
prevent overdriving the LED display.
+5.0 V
1.0 kW
BCD
input
74LS47 16
BCD/7-seg
VCC
3
LT
a
4
BI/RBO
b
5 RBI
c
6 A
d
2 B
e
1 C
f
g
7
D
GND
+5.0 V
MAN72
R's =
330 W
13
12
11
10
9
15
14
1
13
10
8
7
2
11
3, 9, 14
a
b
c
d
e
f
g
8
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
7447 BCD-to-7-Segment Decoder/Driver





4 input pins for BCD code.
7 output pins to control the seven
segments of a 7-segement display.
Also has a lamp test input.
Also a ripple-blanking input and
output to suppress leading or trailing
zeroes.
Data sheet: 7447
Synchronous Counters
In a synchronous counter all flip-flops are clocked
together with a common clock pulse. Synchronous
counters overcome the disadvantage of accumulated
propagation delays, but generally they require more
circuitry to control states changes.
This 3-bit binary
synchronous counter
has the same count
sequence as the 3-bit
asynchronous counter
shown previously. CLK
HIGH
Q0
Q0
J
J1
0
Q1
Q0Q1
Q2
J
2
C
K0
C
C
K1
K2
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
A 4-bit Synchronous Binary Counter
The 74LS163 is a 4-bit IC synchronous counter with additional
features over a basic counter. It has parallel load, a CLR input, two
count enables, and a ripple count output that signals when the count
has reached the terminal count.
Data inputs
D0 D1 D2 D3
(3) (4) (5) (6)
CLR (1)
(9)
LOAD
(10)
ENT
(7)
ENP
(2)
CLK
CTR DIV 16
TC = 15
(15)
RCO
C
(14) (13) (12) (11)
Q0 Q1 Q2 Q3
Data outputs
Example waveforms
are on the next slide…
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
CLR
LOAD
D0
Data
inputs
D1
D2
D3
CLK
ENP
ENT
Q0
Data
outputs
Q1
Q2
Q3
RCO
12
13 14
15
0
Count
Clear
1
2
Inhibit
Preset
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Some Synchronous Counter ICs

74160 and 74162: Four-bit synchronous
decade counters (MOD 10)

74161 and 74163: Four bit synchronous
binary counters (MOD 16)
Up/Down Synchronous Counters
The 74HC190 is a high speed
CMOS synchronous up/down
decade (MOD-10) counter with
parallel load capability. It also has
a active LOW ripple clock output
(RCO) and a MAX/MIN output
when the terminal count is
reached.
D0 D1 D2 D3 Data inputs
74HC190
(4)
(5)
(11)
LOAD (14)
CTEN
D/U
CLK
(12)
MAX/MIN
CTR DIV 10
(13)
C
RCO
(3) (2) (6) (7)
Q0 Q1 Q2 Q3 Data outputs
D0 D1 D2 D3 Data inputs
74HC191
The 74HC191 has the same
inputs and outputs but is a
synchronous up/down binary
(MOD-16) counter.
(15) (1) (10) (9)
(4)
(5)
(11)
LOAD (14)
CTEN
D/U
CLK
(15) (1) (10) (9)
(12)
MAX/MIN
CTR DIV 16
(13)
C
RCO
(3) (2) (6) (7)
Q0 Q1 Q2 Q3 Data outputs
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Some Up/Down Synchronous Counter
ICs

74190 Four bit up/down decade counter
(MOD 10)

74191 Four bit up/down binary counter
(MOD 16)
Cascading Counters



Most counter chips are 4-bit counters, with a
modulus of 16 or less.
To get larger moduli, you cascade two or
more counter chips together.
When you cascade counters, their moduli
multiply, not add.


Example: If you cascade a MOD-10 counter with a
MOD-16 counter, you get a MOD-160 counter.
The connections for cascading counters
differ depending on whether you’re
using asynchronous counters or
synchronous counters.
Cascaded asynchronous counters
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Cascaded synchronous counters
For synchronous IC counters, the next counter is enabled only
when the terminal count of the previous stage is reached.
HIGH
ƒin
Counter 1
Counter 2
16
CTEN
TC
CTEN
CTR DIV 16
CLK
C
TC
fout ƒin
256
CTR DIV 16
Q0 Q1 Q2 Q3
C
Q0 Q1 Q2 Q3
fin
a) What is the modulus of the cascaded DIV 16 counters?
b) If fin =100 kHz, what is fout?
a) Each counter divides the frequency by 16. Thus the
modulus is 162 = 256.
b) The output frequency is 100 kHz/256 = 391 Hz
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved