Transcript OIF Overview

DesignCon 2004
Introducing the OIF Common Electrical
I/O Project
Agenda





OIF Overview
• Steve Joiner, Bookham
CEI Architecture Overview
• Mike Lerer, Xilinx
CEI – Universal Interface
• Pete Hanish,
Texas Instruments
CEI 6G LR
• Graeme Boyd, PMC Sierra
• John D’ Ambrosia,
Tyco Electronics
CEI 6G SR and CEI 11G SR
• Tom Palkert, Xilinx


CEI 11G LR
• Brian Von Herzen, Xilinx
CEI Testing and
Interoperability
• Anthony Sanders,
Infineon Technologies
OIF Overview
Steve Joiner, Bookham




Launched in April of 1998 with an objective to foster
development of low-cost and scaleable internet using
optical technologies
The only industry group bringing together professionals
from the data and optical worlds
Open forum: 160+ member companies
• international
• carriers
• component and systems vendors
• testing and software companies
Mission: To foster the development and deployment of
interoperable products and services for data switching
and routing using optical networking technologies
OIF Focus

Low-cost Scaleable Optical Internetworking
• IP-Over-Switched Optical Network Architecture
• Physical layer
•
•
Control layer interoperability between data and optical layers
• Dynamic configuration using IP signaling and control
mechanisms
Accommodate legacy network under the new physical and
control layer mechanisms
•

Low-cost optical interfaces between networking elements
Standard device level electrical interfaces for low-cost systems
Output from OIF

Develop implementation agreements using
•
•
•
•


Carrier group’s requirements as input
Physical Layer User’s Group requirements as input
Existing standards and specifications when available
Developing new when necessary
Develop interoperability testing procedure to
ensure compliance and ultimately interoperable
products and networks
Provide input into other standards bodies
OIF Directors & Officers
Directors

Joe Berthold, Ciena
President
 John McDonough, Cisco
VicePresident
 Tom Afferton, Northrop Grumman
Treasurer / Secretary
 Monica Lazer, AT&T
Board Member
 Steve Joiner, Bookham Technologies
Board Member
 Marco Carugi, Nortel
Board Member
 Vishnu Shukla, Verizon
Board Member
Technical Committee
Jim Jones, Alcatel
Chair
 Trey Malpass, Mindspeed
Vice Chair

MA&E Committee

Rama Ati, Cisco Systems
Co-Chair
Michael Oltmanns,Northrop
Grumman
Co-Chair

OIF and Standards Bodies

Established Liaisons With:
•
•
•
•
•
•
•
•
•
•
American National Standards Institute - ANSI T1
International Telecommunications Union - ITU-T
Internet Engineering Task Force - IETF
ATM Forum
IEEE 802.3ae 10 Gb Ethernet
Network Processing Forum - NPF
Metro Ethernet Forum – MEF
Rapid I/O
Tele Management Forum – TMF
XFP MSA Group
Technical Committee
Six Working Groups






Architecture & Signaling
• Services, network requirements and architectures
• Protocols for automatic setup of lightpaths
Carrier
• Requirements and applications
OAM&P (Operations, Administration, Maintenance and
Provisioning)
• Network management
Interoperability
• Interoperability testing
Physical and Link Layer
• Equipment and subsystem module interfaces
Physical Layer User
• Requirements and applications
Development of OIF Implementation Agreements
Principal Member Ballot
Comments and IPR call
Define and Start Project
Develop Draft IA
(contribution driven process)
Straw Ballot
Comments and IPR call
Passes >50%?
Resolve Comments
No
Passes >75% ?
Yes
Implementation Agreement
Yes
Major Technical changes ?
No
CEI Overview
Mike Lerer, Xilinx
CEI Project Problem Statement
A faster electrical interface is required to provide
higher density and/or lower cost interfaces for
payloads of 10Gbps and higher
Including:
•
•
•
SERDES to Framer Interface (SFI)
System Packet Interface (SPI)
TDM-Fabric to Framer Interface (TFI)
PLL Interfaces


SFI – SerDes Framer
SPI – System Packet, TFI – TDM Fabric
System Packet
Interface (SPI)
OR
PHY
Device
TDM Fabric to
Framer Interface (TFI)
SERDES Framer
Interface (SFI)
FEC
SERDES Framer
Interface (SFI)
SERDES
Device
and
Optics
Optical
Interface
CEI Protocol (CEI P)
CEI Protocol Project Problem Statement

To define protocols that take advantage of the faster
electrical interface developed by the CEI project. The
target is to provide higher density and/or lower cost
interfaces for payloads of 10Gbps and higher, including
SERDES to Framer Interface (SFI), System Packet
Interface (SPI), TDM-Fabric to Framer Interface (TFI),
8b/10b based Interfaces.
Objectives


Shall conform to the data characteristics required
by the CEI project (Eg., DC balance, Transition
density, Max run-length)
Support a wide range of client signals including
SFI, SPI, TFI, 8b/10b Interfaces
CEI Project Scope
(1 of 2)


Electrical and jitter specifications for future interfaces including SFI, SPI and TFI.
The project shall define:
•
CEI-6G-SR
•
•
•
•
•
•
•
An 11G+ short reach link
0 to 200mm link with up to one connector
Data lane(s) that support bit rates from 9.95 to 11+Gbps over Printed
Circuit Boards.
CEI-11G-LR
•
A 6G+ long reach link
0 to 1m link with up to two connectors
Data lane(s) that support bit rates from 4.976 to 6+Gbps over Printed
Circuit Boards.
CEI-11G-SR
•
•
0 to 200mm link with up to one connector
Data lane(s) that support bit rates from 4.976 to 6+Gbps over Printed
Circuit Boards.
CEI-6G-LR
•
A 6+ Gigabit short reach link
An 11G+ long reach link
0 to 1m link with up to two connectors
Data lane(s) that support bit rates from 9.95 to 11+Gbps over Printed
Circuit Boards.
CEI Project Scope
(2 of 2)



The Implementation Agreement shall define the applicable data
characteristics
• e.g. DC balance, transition density, maximum run length
The Implementation Agreement shall define channel models and
compliance points / parameters.
The Implementation Agreement shall not:
• Define the pin assignments or select a specific connector
• Define a management interface
CEI Project Objectives & Requirements
(1 of 2)

The Implementation Agreement(s) shall allow single and multi-lane
applications

Shall support AC coupling

Shall support hot plug

Shall achieve Bit Error Ratio of better than 10-15 per lane with the test
requirement of 10-12 per lane
CEI Project Objectives & Requirements
(2 of 2)




Short and long reach links should interoperate under 200mm
Shall define an 11G short reach link that is capable of supporting
SONET/SDH compliance at the optical carrier (OC) interface.
The 6G long reach link shall accommodate legacy IEEE 802.3 XAUI
and TFI-5 compliant backplanes.
The primary focus of the CEI-11G-LR implementation agreement will
be for non-legacy applications, optimized for overall cost-effective
system performance including total power dissipation
CEI Project Deliverables
An Implementation Agreement with clauses which shall cover:
• Interoperability, Jitter & Compliance Methodology
• CEI-6G-SR
6G Short Reach
• for 0 to 200mm and up to 1 connector
• CEI-6G-LR
6G Long Reach
• for 0 to 1m and up to 2 connectors
• CEI-11G-SR
11G Short Reach
• for 0 to 200mm and up to 1 connector
• CEI-11G-LR
11G Long Reach
• for 0 to 1m and up to 2 connectors
CEI Project Schedule

CEI
•
Includes
•
•
•
•
•

Now going to fourth round of straw ballot cycles
Additional Clause 9
• Adds
•
•

Interoperability, Jitter & Compliance Methodology
CEI-6G-SR
CEI-6G-LR
CEI-11G-SR
CEI-11G-LR
Now going to second round of straw ballot cycles
Remember
• Straw Ballots continue until there are no additional technical
changes.
• Followed by Principal Member Ballot with no technical changes
and the specification is published.
CEI Universal Electrical Interface
Optimized for System Design
Pete Hanish, Texas Instruments



Minimize overall throughput cost for higher capacity
systems
• Groundwork for 6G/11G PHY interfaces
Deliver value to the entire system chain
• Decrease overall system cost
• Interoperable components for system vendor options
• Development cost leverage for component vendors
Fosters interoperability
• Verification method to ensure interoperability
• Demonstrations already taking place
CEI Universal Electrical Interface
Optimized for System Design



Broad application space
• Standard products, system-on-a-chip, FPGA’s, ASICs
• Multiple technology nodes
Interface specifies only electrical and jitter
• Building block for protocols like
CEI-P, TFI-x, SFI-x, SPI-x, other interfaces
• Backplanes, networking, interconnect, CPU interface
Opportunity to converge standards
• Higher layer standardization flexible
• Liaisons with several bodies
CEI Universal Electrical Interface
Flexibility
Component
Edge
0 – 200mm
or
0 – 1000mm
Component
Edge
Egress
TX
TE
Channel
RE
RX
Ingress
RX
RI
Channel
Does specify
Data char
Channel models
Compliance points
Jitter
BER
TI
TX
4.976 – 6.375Gbps
or
9.95 – 11.1Gbps
Does not specify
Lane count
Pinout
Mgt interface
Power supply
Connector
High level fn
CEI Universal Electrical Interface
Feasibility Demonstration 2003

SuperComm 2003
• CEI-6G-LR
•
•
CEI-11G-SR
•
•
Validated transceivers and
connectors
Validated round robin
interoperability of SERDES
devices, connectors and
optical transceivers
CEI-11G-LR
•
Multiple backplane and
signaling demonstrations
CEI Universal Electrical Interface
Transmit
Link Layer
Device
Receive
Link Layer
Device
System Packet
Interface (SPI)
SERDES Framer
Interface (SFI)
OR
PHY
Device
FEC
SERDES Framer
Interface (SFI)
Optical
Interface
SERDES
Device
and
Optics
TFI
TDM Fabric to
Framer Interface (TFI)
CEI-6G-LR
CEI-11G-SR
CEI-11G-SR
10GBE
10GBFC
OC-192
OC-768
CEI Universal Electrical Interface
11G-LR Industry Development
Transmit
Link Layer
Device
Receive
Link Layer
Device
System Packet
Interface (SPI)
SERDES Framer
Interface (SFI)
OR
PHY
Device
FEC
SERDES Framer
Interface (SFI)
SERDES
Device
and
Optics
TFI
TDM Fabric to
Framer Interface (TFI)
CEI-11G-LR
CEI-11G-SR
CEI-11G-SR
Optical
Interface
Interoperability Strategy
Anthony Sanders, Infineon Technologies




Define exact compliancy tests for transmitter in
terms of eye masks, output jitter and ability to
perform emphasis
Define compliancy test for channels using worst
case transmitter and reference receiver
Give guidelines concerning channel construction
and frequency domain performance
Receiver must be able to tolerate any combination
of compliant transmitter and compliant channel
thus not restricting the market in terms of
developed solutions.
Channel Interoperability Strategy
Backplanes are measured using traditional network
analysers and cascaded with a worse case model

0
Return Loss
Channel
-5
Return Loss
Transmitter &
Receiver
Magnitude (dB)
-10
-15

-20
-25
Example
crosstalk
-30
Transfer
Function with
return loss
-35
-40
0
1
2
3
4
5
6
Frequency (Hz)
7
8
9
10
9
x 10
of the
transmitter and
receiver return
loss
The receiver
pulse response
is then
calculated for a
given
transmitter pulse
shape
Channel Compliance using StatEye

0.25
Amplitude
0.2
0.15
0.1
New methodology in the analysis of channel
equalisation is developed which allows the exact
statistical nature
8
of the
7
frequency
6
response,
crosstalk and
5
jitter to be
4
analysis in terms
3
of a effective
receiver eye.
2
0.05
1
0
-0.5
0
Time Offset (UI)
0.5
0
CEI-6G: Overview
Graeme Boyd, PMC Sierra
•
•
•
•
•
•
•
Definition
Requirements
Channel information
Some typical applications
Restrictions
Specifications
Verification that specifications meet requirements
CEI-6G: Definition

Electrical and jitter specifications for future interfaces
including SFI, SPI and TFI for OIF as well as for other interfaces
unrelated to OIF (examples could include Serial Rapid IO,
SAS, Ethernet). It does not contain any protocol
implementations (that is contained within the OIF’s CEI-P
document or within other standards).
• A CEI-6G Short Reach specification for: Data lane(s) that
support bit rates from 4.976 to 6+Gsym/s over Printed
Circuit Boards.
•
•
Physical reach between 0 to 200mm and up to 1 connector.
A CEI-6G Long Reach specification for Data lane(s) that
support bit rates from 4.976 to 6+Gsym/s over Printed
Circuit Boards.
•
Physical reach between 0 to 1m and up to 2 connectors.
CEI-6G: Requirements
1.
2.
3.
4.
5.
6.
7.
Support serial baud rate from 4.976Gsym/s to 6.375Gsym/s.
Capable of low bit error rate (required BER of 10-15 with a test
requirement to verify to 10-12).
Short Reach:
• Capable of driving 0 - 200mm of PCB and up to 1 connector.
Long Reach:
• Capable of driving 0 - 1m of PCB (such as IEEE 802.3 XAUI or
TFI-5 compliant backplane) and up to 2 connector for long
reach
Shall support AC coupled operation and optionally DC coupled
operation
Shall allow single or multi-lanes.
Shall support hot plug.
HM-Zd XAUI Backplane
Layer Variation @ 20 Inches
0
-5
Sdd21 (dB)
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
Frequency (GHz)
Top
Near-Top
Near-Bottom
Bottom
XAUI
6
HM-Zd Legacy Backplane –
36” Length Configuration Variation
Very different channel
return loss
Reflections moved significantly
HM-Zd Legacy Backplane –
36” Length Configuration Variation
Large group delay differences for return loss
HM-Zd Legacy Backplane –
36” Length Configuration Variation
Modeling chip RL as RC
to the –8dB spec
Perfect chip RL
HM-Zd Legacy Backplane –
36” Length Configuration Variation
Fails channel compliance
Passes channel compliance
Large differences in the resulting eye after ideal DFE
depending on length on line cards and the backplane
CEI-6G: Some typical applications






Multiplexing a 16-lane SFI-5 or SPI-5 link to a 8-lane CEI-6G
short reach link
Multiplexing a 16-lane SFI-5 or SPI-5 link to a 8-lane CEI-6G
long reach link, thus allowing the signals across a backplane
Multiplexing 2*n TFI-5 links to a n-lane CEI-6G long reach links
Multiplexing a 4-lane XAUI or 10G Fiber Channel link to a
2-lane CEI-6G LR link
Doubling the speed of a 16-lane SPI-5 link to a 16-lane
CEI-6G link, thus allowing up to a factor of 2 over-speed for
packet processors
Custom higher speed interconnect and/or backplanes
CEI-6G: Restrictions



Average transition density and average DC balance needs to
converge to 0.5 over a long period (>109 bits) with a
probability of at least one minus the BER ratio.
Probability of run lengths over 10 to be proportional to 2-N for Nlike bits in a row (N10). Hence, a run length of 40 bits would
occur with a max probability of 2-40.
If a fixed block coding scheme is used (e.g. 8B/10B), the input
data must be either be scrambled before coding or the coded
data must be scrambled prior to transmission.
•
This will prevent input data creating killer patterns (e.g. CJPAT
patterns).
CEI-6G: Restrictions



The ground difference between the driver and the
receiver shall be within ±50mV for SR links and
±100mV for LR links.
Both driver and receiver lane-to-lane skew are
each allowed up to 500ps. Higher layers must allow
for this (1ns) skew as well as some PCB skew.
Rather than specifying materials, channel
components, or configurations, the IA focuses on
effective channel characteristics.
•
Hence a short length of poorer material should be
equivalent to a longer length of premium material. A
‘length’ is effectively defined in terms of its attenuation
rather than its physical length.
CEI-6G: Restrictions

So for CEI-6G-SR we have the standard open eye
at the receiver, however for CEI-6G-LR the eye is
closed at the receiver hence requiring receiver
equalization.
CEI-6G: Main Transmitter Specifications
Parameter
Baud Rate
T_Vdiff
T_diffRes
T_rise/fall
T_SDD22
T_SCC22
Uncorrelated Bounded High
Probability Jitter (similar to DJ)
T_DCD
T_TJ
T_X1
T_X2
T_Y1
T_Y2
Min
4.976
400
80
30
CEI-6G-SR
Typ
100
Max
6.375
750
120
Min
4.976
800
80
30
CEI-6G-LR
Typ
100
Max
6.375
1200
120
-8
-6
-8
-6
0.15
0.05
0.30
0.15
0.40
0.15
0.05
0.30
0.15
0.40
200
400
375
600
Units
Gsym/s
mVppd

ps
dB
dB
UIpp
UIpp
UIpp
UIpp
UIpp
mV
mV
CEI-6G: Main Receiver Specifications
Parameter
Baud Rate
R_Vdiff
R_diffRes
R_Vtt
R_SDD11
R_SCC11
R_SJ-max
R_SJ-hf
Bounded High Probability Jitter
(similar to DJ)
R_TJ
R_X1
R_Y1
R_Y2
Min
4.976
100
80
CEI-6G-SR
Typ
100
Max
6.375
750
120
30
-8
-6
5
0.05
Min
4.976
80
0.45
0.65
0.3
50
CEI-6G-LR
Typ
100
Max
6.375
1200
120
30
-8
-6
5
0.05
Units
Gsym/s
mVppd


dB
dB
UIpp
UIpp
0.325
UIpp
UIpp
UIpp
mV
mV
0.3
50
375
After an ideal 5 tap DFE with a T_Vdiff of 800mVppd and certain tap restrictions.
SJ requirements are over and above these numbers.
CEI-6G: Verification

A large amount of work is ongoing in the “Jitter and
Interoperability” area given the BER requirements to insure
different vendors chips can talk with each other.
 For CEI-6G-SR the OIF has chosen to specify the
transmitter and receiver. This then implies what are
compliment channels.


Similar to most other SERDES standards, except that OIF is
using statistical eye’s rather than worst case eye’s.
As CEI-6G-LR can have a closed eye at the receiver,
standard methods do not work anymore, so OIF has
chosen to move the “receiver” spec point to after an
“ideal 5 tap DFE”. Thus specifying the transmitter and
compliment channels while implying the receiver spec.

So however the real receiver is implemented it needs to be
equivalent or better than a 5 tap DFE.
OIF Electrical Specifications
Tom Palkert, Xilinx

SFI = SERDES to Framer Interface

SPI = System Packet Interface

TFI = TDM Fabric Interface

SxI = 2.5 Gbps Electrical Specification

CEI = 6G and 11G Electrical Specification
CEI-11G Short Reach Requirements
1. Support serial data rate from 9.95 to 11. 1 Gsym/s.
2. Capable of low bit error rate (required BER of 10-15 )
3. Capable of driving 0 to 200 mm of PCB and up to 1 connector.
4. Shall support AC-coupled and optionally DC-coupled operation.
5. Shall allow multi-lanes (1 to n).
6. Shall support hot plug.
OIF Electrical Specifications
Transmit
Link Layer
Device
Receive
Link Layer
Device
System Packet
Interface (SPI)
SERDES Framer
Interface (SFI)
SERDES Framer
Interface (SFI)
Data
Status
Data
OR
Status
Data
Data
Clock
Clock
PHY
Device
FEC
Data
Data
Data
Data
Clock
Clock
TFI
TDM Fabric to
Framer Interface (TFI)
SERDES
Device
and
Optics
Optical
Interface
CEI Short Reach Common Electrical Interface
System Packet
Interface (SPI)
CEI-11G-SR
Transmit
Link Layer
Device
CEI-11G-SR
SERDES Framer
Interface (SFI)
CEI-11G-SR
Data
Data
Data
SERDES
Device
and
Optics
Status
Data
Receive
Link Layer
Device
SERDES Framer
Interface (SFI)
PHY
Device
FEC
Status
Data
Data
Optical
Interface
CEI Common Electrical Interface
SERDES Framer
Interface (SFI-5)
System Packet
Interface (SPI-5)
SERDES Framer
Interface (SFI)
Transmit
Interface
(SPI-5)
Transmit
Link Layer
Device
Data
Data
Data
Status
PHY
Device
Receive
Link Layer
Device
SERDES
Device
and
Optics
FEC
Device
Data
Data
Data
Status
Receive
Interface
(SPI-5)
Provide well defined voltage levels and jitter budgets
Optical
Interface
Common Electrical Interface Short Reach
SERDES Framer
Interface (SFI)
System Packet
Interface (SPI)
SERDES Framer
Interface (SFI)
Transmit
Interface
(SPI-5)
Transmit
Link Layer
Device
Data
Data
Data
Status
8"
Receive
Link Layer
Device
PHY
Device
Data
8"
Data
FEC
Device
8"
Data
SERDES
Device
And
Optics
Status
Receive
Interface
(SPI-5)
Capable of driving at least 8 inches of FR4 with 1 connector
Optical
Interface
OIF-SFI-4 phase 1
System
REFCLK
Phase 1
to
Optics
Phase 1
REFCLK
TXDATA [15:0]
TXDATA [15:0]
TXCLK
TXCLKSRC
TXCLK
TXCLKSRC
FEC
Processor
Framer
REFCLK
RXDATA [15:0]
RXDATA [15:0]
RXCLK
RXCLK
Phase 1
Phase 1
Optics
to System
SERDES
Device
And
Optics
Possible OIF-SFI-4 phase 3
System
REFCLK
to
Optics
REFCLK
Phase 3
RXDATA
[single lane]
REFCLK
TXDATA
(single lane)
TXDATA
(single lane)
Framer
Phase 3
FEC
Processor
Phase 3
RXDATA
[single lane]
Phase 3
Optics
to System
SERDES
Device
And
Optics
CEI-11G-SR Common Electrical Interface
FEC
Processor
Differential signal amplitude [V]
TXDATA
Serdes
Normalized bit time [UI]
RXDATA
The receive eye mask specifies the jitter at the end of the line
CEI-11G-SR Common Electrical Interface
FEC
Processor
Differential signal
amplitude [V]
TXDATA
Serdes
Normalized bit time [UI]
RXDATA
The transmit eye mask specifies the jitter at the beginning of the line
CEI-11G-SR RX eye diagram
525 mv
R_Y2
55 mv
Normalized
amplitude
R_Y1
0
-R_Y1
-R_Y2
0.0
.35UI
Receiver input mask
R_X1
0.5
1-R_X1
1.0
Normalized bit time [UI]
CEI-11G-SR TX eye diagram
385 mv
T_Y2
T_Y1
180 mv
Normalized
amplitude
0
-T_Y1
-T_Y2
0.0
T_X1
T_X2
1-T_X2 1-T_X1
1.0
Normalized bit time [UI]
.15UI
Transmit eye mask
.40UI
Sinusoidal Jitter Tolerance (UIp-p)
Jitter Egress Receiver Input Telecom
Sinusoidal Jitter
15.2
-20dB/Dec
1.7
0.17
0.05
0.01E-3
2E-3
17.9E-3
0.12
Frequency (MHz)
4.08
80
Jitter Ingress Receiver Input Telecom
Sinusoidal Jitter
Sinusoidal Jitter Tolerance (UIp-p)
17
-20dB/Dec
1.7
0.17
0.05
0.01E-3
2E-3
20E-3
0.4
Frequency (MHz)
4
8
27.2
80
CEI-11G-LR : Requirements
Brian Von Herzen, Xilinx


Support baud rate from 9.95 Gig/sec to 11.1 Gig/sec
Long Reach



Optimized for Non-Legacy Systems (Greenfield)






Capable of driving 0 - 1m (39 inches) of PCB
& up to 2 connectors
Optimize System cost including Power Dissipation
Capable of low bit error rate (required BER of 10-15 or better)
Shall support AC coupled operation, DC Coupling Optional.
Shall allow multi-lanes (1 to n).
Shall support hot plug.
Shall interoperate with CEI-11G-SR up to 200mm (8 inches).
CEI-11G-LR : Backplane Applications
CEI-11G-LR : Connections up to 1 meter
CEI-11G-LR : Issues

Losses
•
Chip Packaging
•
•
•
•
•

Backplane Connectors
Vias
Cu Losses– skin effect, AC impedance, bulk R
Dielectric losses
Impedance Discontinuities
•

Insertion loss, reflections and impedance mismatches
Reflections
Noise
•
Crosstalk
CEI-11G-LR : General Characteristics





High-Speed Low Voltage Differential Drive
Unidirectional Point to Point Signaling
Uses Balanced Differential Pairs
Uses Differential 100-Ohm Nominal Impedance
Signal Scrambled Non Return to Zero (NRZ)
CEI-11G-LR : Specification Approach

Transmitter Specified
•

Channel Compliance
•
•

Tx Eye Diagram
Channel Specified with S Parameters
Compliance determined with Simulation Script
A compliant receiver shall operate with any
compliant Tx and compliant channel
•
If Tx and Channel are compliant, receiver must work.
CEI-11G-LR : Solutions


NRZ Signaling
The Transmitter
•
Tx Equalization
•
•

The Channel
•
•
•
•


Pre-emphasis of High Frequency
Compensates for Channel Loss
Note: Solution space may
grow with continued
development and further
input from industry on
application needs.
PCB Materials
Connectors
IC Packaging
Manufacturing / Layout Techniques
Assumes Closed Eye at Receiver
The Receiver
•
Rx Equalization
•
•
•
•
Opens Eye
Compensates for High Frequency Losses
Compensates for Impedance Discontinuity
Compensates for Reflections
CEI-11G-LR : Summary

CEI-11G Long Reach provides a robust solution
•
•
•
•
•
9.953 to 11 Gbps
NRZ solution
Up to 1 meter propagation distance
10-15 base error rate, correctable to 10-20 or better
Suitable for next-generation 10G+ system backplane
requirements
Transmitter Eye Mask
Anthony Sanders, Infineon Technologies

0UI
X1
0.5UI
1-X1
1UI
Sample
Population of n

Maximum of
Population
Amplitude
Eye Mask defines
limits of the transmit
jitter and amplitude
but must be
measured using a
Golden PLL
Given finite sampling
of signal, peak value
of time jitter must be
adjusted
Measuring Output Jitter
DUT
Differential
to single
ended amp
+
Golden PLL
Trigger
BERT
Clock
Ref


Signal
BERT
Output Jitter is traditionally measured using a Bit
Error Tester that is capable of introducing a variable
time delay into the trigger path.
A plot of the measured BER against time delay is
commonly known as a Bathtub measurement
Jitter Terminology
 - sampling point
Q - Error Rate
dQ
 UGJ
d



dQ
 CBGJ 2  UGJ 2
d
UBHPJ
CBHPJ  UBHPJ
Unbounded Gaussian
Jitter a.k.a. Random
Jitter
Uncorrelated Bounded
High Probability Jitter
a.k.a. Deterministic
Jitter
Correlated Bounded
Gaussian Jitter, caused
by Amplitude to Time
conversion of ISI,
becomes Correlated
Bounded High
Probability Jitter at
some Error Rate
Jitter Tolerance Testing
Data Output
Signal Filter
for defining
edge rate
Voltage
Controlled
Delay Line
BERT
Clock
Reference
Input
Clock
Reference
Calibrated
Test Data
Wander can be
optionally applied
directly to FM
input
+
Total
SJ Wander
Source

DUT
Jitter Control
Signal Filter
White Noise Source
for generating
Unbounded Gaussian
Jitter
Jitter Control
Signal Filter
PRBS Generator
for generating
uncorrelated High
Probability Jitter
For short reach, Jitter tolerance is performed using
a stressed eye with a defined amount of jitter and a
signal eye “just” at the limited of the defined
received eye mask
Jitter Tolerance Testing
Data Output
BERT
Voltage
Controlled
Delay Line
Signal Filter
for defining
edge rate
+
DUT
Compliant Channel
or Filter
Clock
Reference
Input
Calibrated
Test Data
Signal Filter
for defining
edge rate
Wander can be
optionally applied
directly to FM
input
Clock
Reference
Total
SJ Wander
Source

+
Sinusoidal Noise Source
for generating crosstalk
Jitter Control
Signal Filter
White Noise Source
for generating
Unbounded Gaussian
Jitter
Jitter Control
Signal Filter
PRBS Generator
for generating
Uncorrelated High
Probability Jitter
For long reach the inclusion of a
compliant channel is used to
generate a known amount of ISI
CEI Protocol Project Builds on CEI
to Define these Interfaces
Transmit
Link Layer
Device
Receive
Link Layer
Device
System Packet
Interface (SPI)
SERDES Framer
Interface (SFI)
OR
PHY
Device
FEC
SERDES Framer
Interface (SFI)
Optical
Interface
SERDES
Device
and
Optics
TFI
TDM Fabric to
Framer Interface (TFI)
CEI-6G-LR
CEI-11G-SR
CEI-11G-SR
10GBE
10GBFC
OC-192
OC-768
It is the mission of the OIF to
support the industry by sharing
the results of its efforts with
other organizations.
Thank You!