Transcript OIF Overview - Welcome to AMS

SFI-4.1
Brian Von Herzen, Ph.D.
Xilinx Consultant, www.FPGA.com
OIF Electrical Interfaces
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What are the OIF Electrical Interfaces?
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SPI-5
SFI-5
SPI-4.2
SPI-4.1
SFI-4
SPI-3
SFI-4
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SFI-4 (OC-192 SERDES-Framer Interface) OIF-PLL-02.0
Proposal for a common electrical interface
between SONET framer and serializer/deserializer
parts for OC-192 interfaces)
System Packet Interface Level 5 (SPI-5):
OC-768 System Interface for
Physical and Link Layer Devices
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SPI-5 connects Physical to Link Layer Devices
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Fabric interface chips (FIC)
Traffic managers
Network processing element (NPE’s)
SPI-5 Signals
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The SPI-5 interface uses clock forwarding between
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PHY
Link Layer Devices
Up to 3.125 Gbps
16 lanes
50 gigabits per sec
OC-768 with
25% overspeed
SFI-5
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SERDES Framer Interface Level 5 (SFI-5):
Implementation Agreement for 40Gb/s
Interface for Physical Layer Devices
SPI-4.2
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System Packet Interface Level 4 (SPI-4) Phase 2:
OC-192 System Interface for Physical and Link
Layer Devices
SPI-4.2 Interface for Physical and Link
Layer Devices
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Uses 16 lanes at 622 Mbps or faster
SPI-4.1
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System Physical Interface Level 4 (SPI-4) Phase 1:
A System Interface for Interconnection Between:
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Physical and Link Layer,
Peer-to-Peer Entities Operating at 10 Gbps (OC-192).
64 Data Signals at
200 MHz
SPI-3
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System Packet Interface Level 3 (SPI-3): OC-48
System Interface for Physical and Link Layer
Devices
OIF Electrical Standards Benefits
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Enables “Best-In-Class” selection of devices that
interoperate
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SERDES
FEC
Framers
Traffic Management
Fabric Interfaces
System vendors can choose their favorite feature
sets and mix and match components as needed
OIF Electrical Standards Benefits
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With interoperable standards, vendors can
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Mix and Match “best of breed” components
Minimize the engineering to connect components
Reduce time to market
Enable customization using programmable logic for key
components
System Design Example
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A systems vendor wanting to build an OC-768
switch with OIF standards can select:
A customized traffic manager from FPGA Vendor X
• A framer from ASSP vendor Y
• A SERDES module from Optical Vendor Z
FPGA Vendor X
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Optical
Vendor Z
ASSP
Vendor Y
OIF Electrical Standards Silicon Solutions
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A variety of Silicon implementation solutions are
available, including:
ASSP + FPGA
ASIC
System vendors do not get locked in to a
proprietary solution
OIF-compliant chips interoperate effectively to
enable “best of breed” system solutions