Transcript Slide 1

Ultra-shallow SIMS for
semiconductor depth profiling
Andrew T. S. Wee
Department of Physics
National University of Singapore
SIMS-17, Toronto, Sep09: “Depth Profiling" discussion session
Scope
1. Enabling technologies for ultimate CMOS
scaling
2. Solutions to surface transient problem
3. Low energy SIMS optimal conditions
4. Oblique incidence SIMS
5. Beyond Si and III-V: Graphene?
6. Future of ultrashallow profiling
Technology Navigation for Si CMOS
Performance or
Objective Function (Ion, Ioff, density)
Conventional Scaling does not give Historical Performance Improvement
Schematic Illustration of a
Performance Optimization Problem
Hitting a Performance Plateau
?
Conventional Device Scaling:
• Reduce EOT (equivalent oxide
thickness), LG, xj, etc.
• Increase doping concentration
• Reduce VDD to contain
power consumption.
What happened recently:
• EOT scaling stalls (due to
excessive leakage current).
• LG scaling slows down.
• Pitch Scaling continues for
increased circuit density.
• VDD scaling faces challenges
due to non-scalability of Vth.
Courtesy of YC Yeo
Overview of Scaling Limitations
Reduce LG
Device Density ↑
Short-Channel Effects ↑
Requires EOT, xj , NA scaling
VDD
Reduce Supply Voltage VDD
If (VGS - Vth) is fixed, Vth should ↓
 Ioff ↑
If Ioff is fixed, (VGS - Vth) ↓
 Ion ↓
LG
Reduce Junction Depth xj
Parasitic Series Resistance ↑
Reduce Gate Dielectric Thickness
Gate Leakage Current ↑
Gate Depletion Effects ↑
G
Need to Increase
Poly-Doping
but limited by
solubility of dopants
S
Simple Expression for drive current Ion
D
Increase Doping Concentration NA
Carrier Mobility ↓
Ion = mCox(W/LG)(VGS - Vth)2
If the carrier transport properties, e.g. mobility, of the channel can be engineeried,
technology evolution can take a different direction.
Courtesy of YC Yeo
World’s Smallest Strained Transistors (5 nm)
Breakthrough announced at VLSI Symp. 2008, Honolulu, HI.
Yeo’s Nanoelectronics Group
After Germanium
Epitaxy Growth
Before Growth
of Germanium
Stressor
Yeo’s Nanoelectronics Group
 5 nm Gate Length is one of the Smallest in the World.
 First Demonstration of Germanium Stressor to create High Strain
Levels in a tiny volume of Silicon Channel in a Transistor
 Significant Increase in Carrier Mobility!
 Impact: Future of Electronics.
- Potentially influence path of technology development.
- Show a way to scale Silicon Transistors towards its Ultimate Limit.
Courtesy of YC Yeo
New Paths of Technology Evolution
Performance or
Objective Function (Ion, Ioff, density)
Schematic Illustration of Path
of Future Technological Evolution
Performance
Achievable with
New Material
Capabilities
Search for New Knobs to
tweak to improve performance
Performance
Achievable with
Existing Set of
Materials
• Modification of Properties of
Existing Materials (e.g.
Strained-Si)
• New Materials (e.g. MetalGate/High-k, New Channel
Materials)
• New Device Structures (e.g.
Multiple-Gate Transistors)
Courtesy of YC Yeo
Current CMOS Research Frontiers Far
High-Mobility Materials (III-V’s),
Strain Engineering
S
D
 S/D Resistance Reduction
Dopant-Segregation,
Metallic S/D
 Metal-Gate/High-k Dielectric
Stack Technology
 New Strain Engineering
Technologies
Transistor Cross-Section
Provide Technology Solutions
For Early Evaluation
 Novel Silicide Materials
Now
Long-Term
(Beyond 2020)
Mid-Term
(Ultimate CMOS)
 Advanced Channel Materials,
Near-Term (Major
Impact in Industry)
with Sub-60 meV/decade swing:
Tunnel FETs
Explore Revolutionary
Nanodevices
SIMS challenges:
1. Ultra-thin dielectric layer
2. Ultra -shallow dopant profiles,
junction depths
 Beyond-CMOS Logic Switches
Timeline
Limitations of SIMS profiling:
• Poor lateral resolution (̴100nm);
need test structures
• Instrumental effects
• Includes unactivated dopants
Future
Courtesy of YC Yeo
SIMS Depth Profiling
• SIMS is a destructive technique whereby a crater is formed in
the sample under ion sputtering
• SIMS depth resolution depends on the choice of ion species,
incidence angle and impact energy
• During ion-beam sample interactions, surface roughening and
mixing are the main limiting factors of depth resolution
Surface roughening – the roughening
of sample surface due to inhomogeneous
incorporation of oxygen
Atomic mixing – the pushing of atoms to
deeper layers due to ion bombardment.
Surface transient & roughening in low energy SIMS
Ref: T.J. Ormsby et al. Applied Surface Science 144–145 (1999) 292–296
Ep > 2 keV, 0°<p<60°
Xp=O2+,Cs+
3 regions:
(1) Transient
(2) Steady-state
(3) Roughening
Ep < 2 keV
Region 1 & 3 coalesce
(Region 2 exists for
narrow energy dependent
range in p.)
SIMS Instrumentation
ATOMIKA 4500 SIMS Depth Profiler:
– Ultra-low energy quadrupole SIMS
– “Floating” low energy ion gun (FLIGTM) capable
of delivering stable ion beams down to 100 eV
– Incidence angles from 0 (normal) to 70
Oblique incidence SIMS:
CAMECA IMS 6f Magnetic Sector SIMS:
– EM post-acceleration system
– Sample stage with eucentric rotation capability
(20 rev/min)
– Primary ions: O2+ Incidence angle: 44°-69°
– Oxygen flooding: 1.0  10-6 torr (max)
– Energy range: 0.5 to 10.0 keV
CAMECA Wf Magnetic Sector SIMS:
- Gui D et al., Chartered Semiconductor
Samples: Ge and B delta doped Si wafers
• quantify surface transient, depth resolution, sputter rates
Scope
1. Enabling technologies for ultimate CMOS
scaling
2. Solutions to surface transient problem
3. Low energy SIMS optimal conditions
4. Oblique incidence SIMS
5. Beyond Si and III-V: Graphene?
6. Future of ultrashallow profiling
Solutions to Surface Transient problem
•
•
Cap the surface
•
Shallow implant in Si: H. U. Ehrke et al. Insight 2007, Napa, USA
•
SiON: D. Gui et al, Appl. Surf. Sci. 255, 1437-1439 (2008)
Backside depth profiling
•
•
•
Lower impact energy and select incidence angle
•
W. Vandervorst, Appl. Surf. Sci. 255, 805–812 (2008)
•
A.R. Chanbasha, A.T.S. Wee, Surf. Interface Anal. 37 (2005) 628-632; A.R. Chanbasha, A.T.S. Wee, Surf.
Interface Anal. 39 (2007) 397-404.
Atom probe for 3D profiles
•
•
18O
•
•
Yeo K. L., Wee A. T. S., Liu R., Ng C. M., Surf. Interface Anal. 33 (2002) 373.
P.A. Ronsheim et al, Appl. Surf. Sci. 255, 1547-1550 (2008)
sputtering
H. U. Ehrke et al. SIMS XVI, (2007)
PCOR-SIMS for high dose shallow implant
•
Point-by-point data corrections for all regions of profile; CEA, Application Notes, 2007
SiON with capping layer
6
1E24
-3
10
Cs2
5
+
10
4
10
1E22
+
OCs2
1E21
3
10
N
2
10
1E20
1
10
0
1E19
0
2
4
6
8
10
10
Depth/nm
N concentration/ats.cm
-3
1E24
N uncapped
N capped
1E23
1E22
1E21
Intensity/cps
N concentration/ats.cm
1E23
To achieve better device
performance, it is preferable
to have a N peak close to
the top surface of the
nitrided gate oxide, which
fabricated by using decoupled plasma nitridation
(DPN).
However, it is a challenge to
obtain accurate N dose and
profile shape due to the
surface effect. One solution
is to cap the SiON with a
thin layer of oxide.
D. Gui et al, Appl. Surf. Sci. 255,
1437-1439 (2008)
• MCs2+ technique
1E20
1E19
1E18
-5
0
5
Depth/nm
10
15
Backside SIMS depth profiling using SOI wafers
Yeo K. L., Wee A. T. S., Liu R., Ng C. M., Surf. Interface Anal. 33 (2002) 373.
Yeo K. L., Wee A. T. S., See A., Liu R., Ng C. M., Appl. Surf. Sci. 203 (2003) 335.
Yeo K. L., Wee A. T. S., Liu R., Zhou F. F., See A., J. Vac. Sci. Technol. B 21 (2003) 193.
Amorphous
Si capped
Si
SiO2
Epoxy
Dummy
Si
11B +0.5keV 5E14at./cm2 (Si pre-amorphized);
O2+1.5keV+1keV
Scope
1. Enabling technologies for ultimate CMOS
scaling
2. Solutions to surface transient problem
3. Low energy SIMS optimal conditions
4. Oblique incidence SIMS
5. Beyond Si and III-V: Graphene?
6. Future of ultrashallow profiling
Systematic low energy SIMS study
• Low energy SIMS (250 eV - 1 keV) using both O2+ and Cs+.
• Wide range of incidence angles (0 – 70) using a quadrupole
SIMS.
• Variations in surface transient widths, depth resolution
sputter rates reported.
• Optimum profiling conditions are recommended for silicon
ultrashallow profiling (using O2+ and Cs+).
1.
2.
3.
4.
•
A.R. Chanbasha, A.T.S. Wee, Surf. Interface Anal. 37 (2005) 628-632.
A.R. Chanbasha, A.T.S. Wee, J. Vac. Sci. Technol. B 24 (2006) 547-553.
A.R. Chanbasha, A.T.S. Wee, Surf. Interface Anal. 39 (2007) 397-404.
A.R. Chanbasha, A.T.S. Wee, J. Vac. Sci. Technol. B 25 (2007) 277-285.
Understanding the SIMS altered layer: In-situ XPS study
•
Tan SK, Yeo KL, Wee ATS, Surf. Interface Anal. 36 (2004) 640-644
Effect of O2+ SIMS on surface transients
A.R. Chanbasha, A.T.S. Wee, Surf. Interface Anal. 37 (2005) 628-632
Intensity (cps)
1.E+06
Ip
1.E+05
44SiO+
30Si+
1.E+04
• Ge delta layers
1.E+03
• depth markers
1.E+02
70Ge+
• depth resolution
1.E+01
1.E+00
0
50
100
Depth (nm)
150
Depth profile obtained using Ep ~250eV at  ~20o
200
Surface transient - incomplete oxidation
30Si+
1.E+06
a) 250 eV
Intensity (cps)
Intensity (cps)
1.E+05
profiles for (a) Ep ~250 eV (b) Ep ~500eV and (c) Ep ~1keV
1.E+04
0
40
10
50
20
60
30
70
1.E+03
Intensity (cps)
1.E+05
1.E+04
0
1.E+07
b) 500 eV
1
2
3
4
5
0
1
2
3
4
5
Equilibrium signals:
c) 1 keV
-1 keV : profiles at  < 40o, eqm
signals higher than initial.
1.E+06
- but not at  > 50o,
1.E+05
-500 eV: lower eqm intensities at  > 60o
1.E+04
0
2
4
6
8
Apparent Depth (nm)
10
-250 eV: eqm Intensities are higher at
all 
SIMS Altered Layer @ Steady State Sputtering
S. K. Tan, K. L. Yeo, A. T. S. Wee, Surf. Interface Anal. 36 (2004) 640.
XPS relative concentrations.
XPS Si 2p spectra of the crater surface at
steady state of 4 keV O2+ bombardment.
Si(0)
Si(II)
Si(IV)
Si(I)
Si(III)
Si(IV)
(b) 0
o
SiO2
(c) 15
Super saturation of oxygen
70
REL. CONC. (%)
(a) Si(100)
80
60
Si(I)
Si(III)
O
50
40
Si(II)
Si(IV)
30
20
10
o
0
(d) 30
(e) 45
(f) 55
sub-oxide
+
SiO2
o
o
o
(g) 70
106
0
10 20 30 40 50 60
INCIDENT ANGLE (Degree)
70
O2+ bombardment
sub-oxide
Ion
incorporation
o
104
102
100
Binding Energy (eV)
98
vs.
Sputtering
Different oxide layer
Transient Width (nm)
Surface transient – transient width
16
14
12
10
8
6
4
2
0
SiO+ (500 eV)
Si+ (500 eV)
SiO+ (1 keV)
Si+ (1 keV) ref 12
Si+(560 eV)
ref.12
+
+
Si (1 keV)
SiO (250 eV)
Si+ (250 eV)
0
10
20
30 40 50 60 70
Angle of Incidence
80
90
Difference greatest
at θ where ztr
coincides with
surface
roughening.
1keV/40o and
500eV/50o ~ θc for
oxidation
Measured transient width based on both 44SiO+ and 30Si+
-ztr < 1nm at Ep~250eV, θ~0-50o
-ztr~0.7nm at Ep~250eV, θ~0-20o
-ztr~0.7nm at Ep~500eV, θ~0-10o
-ztr 1.5nm at Ep~1keV, θ~0-10o
Sputter rates with depth
1.6
1.6
b) 500 eV
1.4
1.2
1.0
0.8
0
10
20
30
40
50
60
70
1.4
1.2
1.0
0.8
0.6
0.6
1.6
Relative Sputter Rate
Relative Sputter Rate
Relative Sputter Rate
a) 250 eV
c) 1 keV
1.4
-250eV: stable 0o<<40o diff d1-avg 7%
1.2
-500eV: stable 0o<<40o diff d1-avg10%
1.0
-1keV: stable 0o<<20o diff d1-avg 11%
0.8
0.6
0
20
40
60
80
Depth (nm)
100
120
Normalized sputter rates throughout the depth
Summary of surface transient width, sputter rate and the
onset of roughening for O2+ sputtering
250eV
500eV
1keV
Surface Spike
Nil
 > 50o - 60o
 >30o - 40o
Equilibrium signals lower than
initial
Nil
 > 60o
 > 50o
c (incomplete oxidation)
Nil
 > 60o
 > 50o
Different ztr for SiO+ and Si+
 > 60o
40o <  < 50o
30o <  < 50o
Onset of roughening
 ~ 60o
 ~ 50o
 ~ 40o
Range of  giving lowest ztr
 ~ 0o - 20o
 ~ 0o – 10o
 ~ 0o – 10o
Lowest ztr
0.7nm
0.7nm
1.5nm
Sputter rate max. at
 ~ 50o
 ~ 60o
 ~ 60o
Sputter rate min. at
 ~ 0o
 ~ 0o
 ~ 0o
Stable erosion rate at
0o <  < 40o
0o <  < 40o
0o <  < 20o
~ 10%
~ 11%
Difference in sputter rate between
near surface and throughout
depth for  with stable erosion
rate ~ 7%
O2+ SIMS depth resolution parameters (FWHM and ld)
dependence on energy for the first delta-layer profile at  ~ 0o.
Summary of results of O2+ sputtering
Lowest FWHM
250eV
500eV
1keV
1.5nm
2.2nm
3.5nm
 ~ 0 – 30o
 ~ 0 – 20o
 ~ 60 - 70o
(50nm)
 with lowest
FWHM
 ~ 0 - 40o
throughout depth
 with lowest
FWHM to a
limited depth
(nm)
Nil
 ~ 60 - 70o
(12nm)
Lowest ld
< 1nm
~ 1.2nm
~ 1.8nm
 with lowest ld
throughout depth  ~ 0 -50o
 ~ 0 - 30o
 ~ 60 -70o
 ~ 0 - 20o
 ~ 60 -70o
 with best
dynamic range
 ~ 50o
 ~ 40o
 ~ 30o
Highest dynamic
range
6.8 x 103
8.9 x 103
2.3 x 104
Effect of Cs+ SIMS on surface transients
A.R. Chanbasha, A.T.S. Wee, Surf. Interface Anal. 39 (2007) 397-404
1.E+06
30
Intensity (cps)
1.E+05
Si-
Ip
59 2Si
1.E+04
1.E+03
98
1.E+02
SiGe-
1.E+01
1.E+00
0
50
100
150
Depth (nm)
Depth profile: Ep~320eV at θ~50o
200
1.E+06
30Si-
Intensity (cps)
a) 320eV
1.E+05
1.E+04
0
40
10
50
20
60
1.E+03
1.E+06
Intensity (cps)
b) 500eV
1.E+05
30
70
3 distinct profile trends:
1 (a) Abrupt rise before steady state
(Ep~320eV, 30-50o; Ep~500eV,30-40o;
Ep~1keV, 20-30o)
- progressive build-up of Cs
(b) Abrupt rise then gradual rise to steady
state (Ep~500eV, 0-20o; Ep~1keV, 0-10o)
1.E+04
2. Abrupt rise, shoulder before steady state
(Ep~320eV, 0-20o)
- indicative of onset of roughening
- only >50o (Kataoka et al. [2003])
- confirmed by AFM, SiO2/Si interface
1.E+03
1.E+07
c) 1keV
Intensity (cps)
profiles
1.E+06
1.E+05
1.E+04
1.E+03
0
2
4
6
8
Apparent Depth (nm)
3. Less abrupt rise, peak before steady state
(Ep~320eV, 60-70o; Ep~320eV, 50-70o;
10
Ep~1keV,40-70o)
Transient width
Transient Width (nm)
25
Minimum ztr:
Ep~320eV, θ~40o – 2.0nm
Ep~500eV, θ~ 40o – 1.4nm
Ep~1keV, θ~30o – 1.5nm
30Si(500eV)
20
15
30Si(320eV)
30Si(1KeV)
10
ztr < 2Rnorm
2Rnorm 1 keV
5
2Rnorm 500 eV
2Rnorm 320 eV
0
0
10
20
30 40 50 60
Angle of Incidence
70
80
90
Enhanced ztr: >50o
Reducing Ep not significant
in reducing ztr
Θ>50o not suitable for ultrashallow dopant profiling
a) 320eV
Relative Sputter Rate
Sputter rates with depth
1.8
0
40
1.6
10
50
20
60
30
70
1.4
1.2
1.0
0.8
0.6
1.6
Other angles – error ~15%
Relative Sputter Rate
Only at
can
average sputter rate be used.
Difference is ~3%
b) 500eV
1.4
1.2
1.0
0.8
0.6
1.6
Relative Sputter Rate
Ep~320eV,θ~0-10o
c) 1keV
1.4
1.2
1.0
0.8
0.6
0
20
40
60
80
Depth (nm)
100
120
Summary of results from this work using ultralow-energy Cs+ sputtering.
320eV
30Si-
profile with no peaks & no
shoulders)
θ
~ 30-50o
30Si-
profiles with shoulders
θ
~ 0 - 20o
30Si-
profiles with peak
θ
~ 60-70o
Enhanced transient width 11
θ
Range of
θ giving lowest ztr
~ 30-40o
1keV
θ~ 20-30o
θ~ 0-10o(gradual rise)
Nil
θ
~ 50-70o
Nil
Θ
~ 40-70o
θ
> 60o
Θ > 65o
~ 30o
θ
~ 30o
Θ ~ 20-30o
~ 50o (250eV)
θ
~ 55o
θ ~ 60o
θ
θ
θ
> 57o (250 eV)
Equilibrium signals maximum
intensity at
θc roughening (evaluated at
25μm) 27
500eV
θ
Lowest ztr
~ 30-50o
2.0 nm
θ
Sputter rate max. at
θ
~ 30-50o
1.4 nm
θ
~ 20-30o
1.5 nm
~ 50o
θ
~ 60o
θ
~ 60o
~ 0o, 70o
θ
~ 0o
θ
~ 0o
Sputter rate min. at
θ
Stable erosion rate (surface cf
depth) at
θ ~ 0-10o(i)
θ ~ 20-50o(ii)
θ ~ 40-50o
θ ~ 50-60o
~3%(i)
~ 15% (ii)
~15%
~15%
Difference in sputter rate between
near surface and throughout
depth for θ with stable
erosion rate
Depth resolution (FWHM)
5
b)
FWHM (nm)
4
y = -0.019x + 3.8
3
2
y = -0.019x + 3.2
y = -0.019x + 3.0
1
320 eV
500 eV
1 keV
0
0
10
20
30
40
50
Incident Angle
60
70
Linear relationship between the depth resolution in terms
of FWHM (dz) with θ when there is no surface roughening
Cs+ SIMS depth resolution parameters (FWHM and λd) dependence on
energy for the first delta-layer profile at θ ~ 0o.
Summary of results observed with ultralow-energy Cs+ sputtering
320 eV
500 eV
1 keV
Lowest FWHM
1.9nm
2.2nm
2.5nm
θ with lowest FWHM
throughout depth
(120 nm)
θ~
θ~
θ ~ 60o
(up to 80 nm)
50o
50o
θ ~ 60o
θ with low FWHM to a
FWHM ~ 2.6 nm
limited depth
(up to 23 nm)
θ ~ 60o
FWHM ~ 2.3 nm
(up to 12 nm)
θ ~ 50o
FWHM ~ 2.6 nm
(up to 103 nm)
θ with good depth
resolution
θ ~ 30-50o
(< 2.4 nm)
θ ~ 30-50o
(< 2.5 nm)
θ ~ 40-60o
(< 3.0 nm)
Lowest λd
~ 1.1 nm/e
~ 1.1 nm/e
~ 1.5 nm/e
with lowest
λd
throughout depth
θ ~ 50-70o
θ ~ 60 -70o
θ ~ 70o
θ ~ 50o
θ ~ 70o
3.0 x 103
2.8 x 103
θ
θ with best dynamic
range
θ ~ 60o
Highest dynamic range
1.1 x 103
Summary for low energy SIMS
• O2+:
– Minimum transient width achievable at normal and near normal
incidence
– Reducing Ep beyond 500eV does not result in significant reduction in ztr
• Cs+:
– Lowest ztr reported ~ 1.4-2nm
– Best depth resolution achievable over wider range of θ
• Optimum conditions for analysis
– O2+: Best working range with narrow transient and accurate depth
calibration: 250eV, 0-20o; 500eV,0-10o; ztr ~0.7nm
– Cs+: Best condition for high depth resolution and good dynamic range:
250eV, 40o
Scope
1. Enabling technologies for ultimate CMOS
scaling
2. Solutions to surface transient problem
3. Low energy SIMS optimal conditions
4. Oblique incidence SIMS
5. Beyond Si and III-V: Graphene?
6. Future of ultrashallow profiling
B- profiles using 500 eV SIMS impact energies at 46° with and
without oxygen flooding
Normalized matrix intensity
10-1
10-2
10-3
No Flooding
With Flooding
10-4
0
20
40
60
80
100
120
140
160
Sputter depth (nm)
Oxygen flooding improves depth resolution and
suppresses crater bottom roughening effects
180
200
Delta B profiles obtained using various SIMS impact energies at
46° with oxygen flooding at saturated pressure (1.6 × 10-6 torr)
Normalized B intensities
10-1
• Oxygen flooding
improves resolution
in 0.5-2.0 keV
incident energy
range.
• Resolution is best at
500 eV.
10-2
10-3
10-4
0
2.0 keV
1.5 keV
0.5 keV
20 40 60
80 100 120 140 160 180 200
Depth (nm)
Effect of Oxygen Flooding on Crater Surface Composition and Surface Roughening
in SIMS profiling using 1 keV O2+
7
10
6
10
5
30
Intensity of Si+ (counts per sec)
10
10
No
5.4
6.5
7.5
1.9
4
0
20
40
Flooding
-8
X 10 m bar
-8
X 10 m bar)
-8
X 10 m bar
-7
X 10 m bar
60
Sputter D epth (nm )
80
100
Ref: Ng CM, Wee ATS, Huan
CHA, See A, J VAC SCI
TECHNOL B 19: (3) 829-835
MAY-JUN 2001
• Intensity of 30Si+ as a
function of depth for
sputtering under various
flooding pressures.
• Reduction of surface
transient with increasing
flooding
• Shift of roughening transition
to shallower depths
Sample rotation with oxygen flooding
3.0
at depth ~ 30nm
2.5
at depth ~ 100nm
roughness/nm
2.0
1.5
1.0
0.5
0.0
1E-6
1E-5
1E-4
1E-3
0.01
Oxygen flooding has two competing
effects on the surface roughening,
i.e., enhancement of initiating
roughening and suppression of
roughening development.
At the intermediate pressure of ~
5.8E-5 Pa, the surface roughening
becomes most pronounced.
The
surface roughening is negligible
without flooding or with flooding at
the saturated pressure.
flooding pressure/Pa
Pressure/Pa
Z on/nm
Wtr/nm
4.40E-05
30.2
24.4
5.00E-05
16.8
16
6.00E-05
7.8
6.2
7.00E-05
5.8
4.4
7.50E-05
5.4
3.8
D. Gui et al, Appl. Surf. Sci. 255, 1433-1436 (2008)
7.70E-05
5
3.3
Effect of Oxygen Flooding on Surface Topography
(a) No flooding
rms = 0.3 nm
(b) Flooding at
intermediate pressure
(6.5  10-8 mbar)
rms = 2.5 nm
(c) Flooding at
saturated pressure
(1.9  10-7 mbar)
rms = 0.1 nm
2  2 mm2 AFM images
of the crater surface
after SIMS profiling with
(a) no oxygen inlet;
(b) intermediate pressure
(6.5  10 -8 mbar); and
(c) saturated pressure (1.9
 10-7 mbar) of oxygen
•
Effect of Oxygen Flooding on Surface Composition
(d)
(c)
Si
•
(4+ )+
Si
Si
3+
Si
Si
2+
1+
Si
o
Sat.pressure
(1.9  10-7 mbar)
4+
(a)
(b)
(c)
Interm. pressure
(6.5  10-8 mbar)
•
(b)
No Flooding
(a)
(d)
Virgin sample
Curve fitting for the XPS
spectra obtained for
virgin Si sample;
no oxygen inlet;
intermediate pressure (6.5 
10 -8 mbar);
saturated pressure (1.9  10 7 mbar) of oxygen.
(b), (c) and (d) were obtained
at a sputtered depth of about
100 nm. Only the Si 2p3/2
peak components are shown
here for clarity.
Shallow As profiled by CAMECA Wf
2keV As
500eV Cs+
O2 flooding
Using oxygen flooding in combination with low energy Cs+ sputtering, improves the
sensitivity of SIMS profiling and removes the variation of the ion yield at the native
oxide/silicon interface.
A. Merkulov et al. Appl. Surf. Sci. 231–232 (2004) 640–644
Conclusions for Oblique incidence SIMS
• Low primary ion energies (sub-keV) improves depth
resolution.
• Oxygen flooding and/or sample rotation is needed for oblique
incidence sub-keV SIMS profiling to suppress surface
roughening.
• Oxygen flooding needs to be performed at saturation
pressures whereby SiO2 (and not sub-oxides) forms to
suppress surface roughening.
Scope
1. Enabling technologies for ultimate CMOS
scaling
2. Solutions to surface transient problem
3. Low energy SIMS optimal conditions
4. Oblique incidence SIMS
5. Beyond Si and III-V: Graphene?
6. Future of ultrashallow profiling
Leading Strained Transistor Technologies
World’s First Transistor with
Silicon-Carbon Stressors
Reported in IEDM 2004
Body Thickness is ~18 nm
World’s First ThinBody Transistor
with SiliconCarbon Stressors
Electron Device
Letters 2007
World’s First Integration of
Silicon-Carbon Stressors with
Tensile SiN Liner
VLSI Symp. 2006
Yeo’s Nanoelectronics Group
Yeo’s Nanoelectronics Group
Yeo’s Nanoelectronics Group
Yeo’s Nanoelectronics Group
World’s First Nanowire Transistor with
Silicon-Carbon Stressors
IEDM 2006
Yeo’s Nanoelectronics Group
Si:C
Si
First Integration of SiliconCarbon Stressors in Transistor
with SiGe Channel
VLSI Symp. 2006
Si:C
Si:C
25 nm nanowire
Courtesy of YC Yeo
Taxonomy for Emerging Research Information Processing Devices
Ref: International Roadmap for Semiconductors (ITRS) 2007
Challenges of CMOS Technology
Intel's 45-nm high-k metal-gate process
(Intel® Core™ i7 processor )
Intel’s 32 nm Nehalm chip architecture
http://www.techlivez.com/2007/09/intel-reveals-worlds-first-32nm-chip-technology/
www.cycho.org/research/blog/
Scaling CMOS to and beyond the 16 nm technology generation:
“Develop new materials to replace silicon as an alternate channel to increase the saturation
velocity and maximum drain current in MOSFETs while minimizing leakage currents and
power dissipation for technology scaled to 16 nm and beyond. Candidate materials include
Ge, SiGe, III-V compound semiconductors, and graphene. Develop 1D (nanowire or
nanotube) structures to scale MOSFETs and CMOS gates beyond the 16 nm technology
generation.“
Ref: International Roadmap for Semiconductors (ITRS) 2007
Emerging Research Materials
Ref: International Roadmap for Semiconductors (ITRS) 2007
• Graphene may enable novel and complementary applications to carbon
nanotubes (CNT), its 1D counterpart. Graphene is receiving considerable
attention because it exhibits ambipolar carrier conduction, a carrier
mobility as high as ~ 2×106 cm2/V-sec, and a defect density of
~1×1010/cm2.
• … mobility … is practically independent of temperature, thus opening the
possibility of room temperature ballistic transport at the submicrometer
scale.
• Graphene on SiC can be patterned and etched by conventional planar
lithography techniques and has the best reported transport properties,
but processing temperatures, 1200–1400°C, are incompatible with CMOS
fabrication.
• Since the bandgap of nanoribbons varies inversely with the ribbon width,
it is possible to pattern and tune their electronic properties, such as
bandgap opening due to lateral size quantization, though dimensional
control.
Graphene-on-SiC FETs near DARPA targets
http://nanotechweb.org/cws/article/tech/39365
Technology update Jun 4, 2009
• HRL Laboratories has claimed a big leap forward in radio-frequency graphene transistors just
days after describing the first such devices in IEEE Electron Device Letters. On May 21, the
Malibu, California, research institution said that it had made devices from single-layer
graphene on 2 inch diameter SiC wafers with much-improved performance figures.
• “They have world-record field mobility of approximately 6000 cm2/Vs, which is six to eight
times higher than current state-of-the-art silicon n-MOSFETs,” said HRL senior scientist JeongSun Moon.
• The researcher also described the ratio of on-state current to off-state leakage current, Ion/Ioff
of 19 for the devices as “excellent”.
Multi-technique surface analytical approach
Single-layer graphene on SiC
STM:
4 nm
1 nm
multi-layer graphene
or HOPG
1 nm
G
Raman Intensity
1594
SiC
D 1520
1370
1000
2D
SiC
1710
2735
2-3 layer EG
2710
1365
single layer EG
1593
0
1200
1500
1800 2100 2400
-1
Wave Number /cm
2700
3000
Raman: Ni ZH et al., Phys. Rev. B 77 (2008)115416.
XPS: Chen. W, et. al. Surf. Sci, 596, 176 (2005)
Scope
1. Enabling technologies for ultimate CMOS
scaling
2. Solutions to surface transient problem
3. Low energy SIMS optimal conditions
4. Oblique incidence SIMS
5. Beyond Si and III-V: Graphene?
6. Future of ultrashallow profiling
Minimum low energy SIMS depth resolution?
W. Vandervorst, Applied Surface Science 255 (2008) 805–812
• Unlimited reduction of the primary ion energy is not possible as below the
threshold energy for sputtering, no target removal occurs anymore.
• O2: minimum value for sputtering lies around 30–40 eV
• Cs: the threshold energy for sputtering lies around 100–10 eV.
Cluster beams
W. Vandervorst, Applied Surface Science 255 (2008) 805–812
• Cluster beams do not seem to solve the depth resolution issues and suffer
from unexpectedly large decay length values when considering the low
energy per constituent atom.
• Formation of a deposit limits the reduction in primary beam energy
Future of ultra-shallow profiling?
• Ultra shallow SIMS
– “SIMS performance needs to be improved down to the 0.5 nm/dec level.
Meeting this target is extremely difficult and can only be approached by going
as low as 100 eV.” (Vandervorst, SIMS XVI 2007)
– But SIMS is still the technique of choice for the semiconductor industry as it is
relatively simple, and reproducibility rather than accuracy is needed
• 3D Atom probe
– sample preparation (needle shape specimen with a top radius 50 nm) typically
requiring extensive focused ion beam milling
• Low energy ion scattering (LEIS)
– For heavier atoms in lighter matrix
• Angle (& energy) resolved XPS
– Lower sensitivity, but ultra shallow doping levels often >1020 at/cm3
• Combination of complementary surface analysis techniques
– new materials to replace silicon (Ge, SiGe, III-Vs, graphene); matrix effect
issues with SIMS
XPS, UPS, AES
SIMS
LT-STM
VT-STM
Synchrotron PES, XAS
Thank You
Questions?
Semiconductor Challenges to SIMS
W. Vandervorst, Applied Surface Science 255 (2008) 805–812
• The development of the (sub-)32 nm technologies requires the formation
of very shallow dopant profiles by low energy (cluster) implantation and
diffusion-less (flash or laser) anneal leading to junction depths as small as
10 nm and with a steepness in the order of 1–2 nm/dec.
• Requirements on the SIMS depth resolution can be achieved by lowering
the primary beam energy to 250–500 eV.
Difficulty in adjusting incident angle
Generally speaking, magnetic SIMS has limitations in tuning the incident
angle. It is even more difficult for CAMECA Wf to adjust the incident angle
because the primary beam passes through split extraction field to reduce the
deflection of primary beam in shallow depth profiling.
Challenges of Si CMOS Technology
-Device scaling
Objective: increase packing density and switching speed
65nm technology
node
Gate oxide ~1-3nm
Lg
Gate
EOT
Source
SDE
SDE
Drain
xj
Lch
SIMS challenges:
1. Utra thin dielectric layer
2. Shallow dopant profiles,
junction depths
Lch decrease, electric field interaction
results in leakage from D-S when
transistor is off (SCE)
>Shallower junction depth ~ 13-30nm