Transcript Little Box Challenge - LED lighting, LEDs, power

Achieving High Power Density Using Cree
Silicon Carbide MOSFETs And Diodes
Cree’s Little Box Challenge Support Team
Wednesday, September 24th, 2014
© 2014 Cree, Inc. All rights reserved.
Cree® and the Cree logo are registered trademarks of Cree, Inc.
Agenda
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SiC vs. Si
LBC design consideration
Design considerations for SiC
Available tools
Cree product portfolio
Q&A
© 2014 Cree, Inc.
All rights reserved.
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© 2014 Cree, Inc.
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3
Advantages of SiC over Si
• Lower switching losses
• Higher switching frequencies
• High operating temperatures
• High thermal conductivity
© 2014 Cree, Inc.
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4
Agenda
•
•
•
•
•
•
SiC vs. Si
LBC design consideration
Design considerations for SiC
Available tools
Cree product portfolio
Q&A
© 2014 Cree, Inc.
All rights reserved.
5
Box-Level Specifications
Volume ≤ 40 in3
TCASE ≤ 60 °C (TAMB = 30 °C)
IIN
10 Ω
+
+
+
VIN
450 VDC
DC / AC
Inverter
-
VOUT
240 VRMS ±5 %
ZLOAD
2 kVA
Pf = 0.7 – 1
500 VA steps
-
η ≥ 95%
(CEC & Full Load)
Input Ripple @ 120 Hz
I IN _ Pk  Pk
 20 %
VIN _ Pk  Pk
 3%
VIN _ Avg
I IN _ Avg
 Drives Energy Storage Requirement
© 2014 Cree, Inc.
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Output THD and Noise
VTHD+N < 5%
ITHD+N < 5%
 Drives Output Filter Requirement
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Challenges from Our Perspective
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Energy storage required at 120 Hz
–
Large capacitors required with conventional topology
–
Energy storage size can be reduced through alternative topologies enabled by SiC
Thermal management system
–
Max case temperature rise of 30°C significantly limits allowable power dissipation in a natural
convection cooled system. Extremely high efficiency must be guaranteed to enable this.
• The reduced losses of SiC devices help enable this efficiency-driven approach.
–
Forced convection cooling allows higher density at the expense of added fan power consumption.
Must maintain 95% efficiency @ full-load.
• High temperature capability and low thermal resistance of SiC devices keeps your cooling
system small in this density-driven approach.
•
Output filter size is driven by output THD+N specs
–
Can be made smaller with increased switching frequency.
• Enabled by SiC devices’ low loss, high switching frequency capability.
© 2014 Cree, Inc.
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7
Topology Idea #1
Full-bridge Inverter with LC Output Filter
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Advantages
Simple power topology
Low parts count, low control complexity
Can use 500 V electrolytic caps (lifetime?)
High Fsw can shrink output filter  use SiC!
Challenges
• 1.3 mF DC Link Capacitance required @ 500V,
12 in3 using electrolytic , 1/3 of total volume
• Also need switching frequency bypass caps
with ~10 Arms ripple capacity @ Fsw,
achievable in 0.1 in3 with ceramic.
• Also need auxiliary LV control power supply
© 2014 Cree, Inc.
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8
Topology Idea #2
Advantages
• Flexibility to interface with energy
storage system at a different voltage,
possibly with higher energy density than
500 V electrolytic capacitors
• High utilization of energy storage
element; allows large voltage swing
• High switching frequency can keep
added DC/DC converter small  Use
SiC
Challenges
• High parts count and control complexity
• Some power processed three times,
lower overall efficiency expected
• Lower efficiency requires excellent
thermal design, likely forced-air
Full-bridge Inverter with LC Output Filter
and shunt-connected Energy Storage Interface
© 2014 Cree, Inc.
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• SiC addresses all of these challenges!
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Topology Idea #3
Boost Converter + Full-bridge Inverter with LC Output Filter
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Advantages
Smaller link capacitor by allowing large line frequency ripple  High density
• For example: Boost to 600+ VDC and allow 300 Vpk-pk ripple @ 120 Hz
Enables film + ceramic capacitors for higher reliability
Topology has been widely used and proven in the solar inverter industry
Easy to add auxiliary winding on boost inductor to derive LV control power supply
High switching frequency can shrink both boost inductor and output filter size
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Challenges
Requires 1200 V switches throughout  Use our 1200V MOSFETs and Schottky diodes
Higher parts count and control complexity
All power processed twice, so lower efficiency is expected
Higher power density and lower efficiency requires excellent thermal management
This approach is not possible without SiC
•
© 2014 Cree, Inc.
All rights reserved.
10
Agenda
• SiC vs. Si
• LBC design consideration
• Design considerations for SiC
– What is different?
• Available tools
• Cree product portfolio
• Q&A
© 2014 Cree, Inc.
All rights reserved.
11
Familiar shape, but very different
Donkey
1200V Si MOSFET
Arabian Horse
1200V SiC MOSFET
• Switching speed
• Power dissipation & thermal conductivity
• Breakdown voltage margin
• Gate drive characteristics
• Die size
© 2014 Cree, Inc.
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SiC versus Si MOSFET Comparison
1200V, SiC MOSFET
C2M Technology
C2M0080120D
Vds (V)
Id.cont @
Tc = 100°C (A)
Rdson (typ) @
Tj 25 / 150°C
1200V, Si MOSFET
HiPerFET
IXFX 20N120
650V, Si MOSFET
CoolMOS, C7
IPW65R065C7
1200V
1200V
650V
20
14.5
21
80 / 148 +85%
750 / 2150 +186%
58 / 138 +138%
• High breakdown voltage margin 10% versus 35%
• 14x lower conduction losses at 150˚C
• Rdson is more stable over temperature
© 2014 Cree, Inc.
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SiC versus Si MOSFET Comparison
1200V, SiC MOSFET
C2M Technology
C2M0080120D
1200V, Si MOSFET
HiPerFET
IXFX 20N120
650V, Si MOSFET
CoolMOS, C7
IPW65R065C7
-5 / +20
0 / 10
0 / 13
Qg (nC)
49.2
160
64
Turn ON time
(tdon+tf) (nS)
30.4
70
24
800V, Rg=0, Vg=20/0
600V, Rg=1, Vg=10/0
400V, Rg=5.3, Vg=13/0
36.8
95
86
800V, Rg=0, Vg=20/0
600V, Rg=1, Vg=10/0
400V, Rg=5.3, Vg=13/0
40 nS / 165 nC
300 nS / 1400 nC
800 nS / 10,000 nC
350 A/us, 800V
100 A/uS, 100V
60 A/uS, 400V
Vg (V) off / on
Turn OFF time
(tdoff+tr) (nS)
Body Diode
recovery Trr/Qrr
• Drive voltage Vg is different
• Although Vgs swing is wider, total gate charge is lower
• Superior body diode performance
© 2014 Cree, Inc.
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SiC makes economic sense TODAY !
Normalized to
SiC Price
© 2014 Cree, Inc.
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1200V, SiC MOSFET
C2M Technology
C2M0080120D
1200V, Si MOSFET
HiPerFET
IXFX 20N120
650V, Si MOSFET
CoolMOS, C7
IPW65R065C7
1
1
0.4
15
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Common Concerns
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Is there more ringing when using SiC MOSFETs?
Measurement techniques
Can Short circuit protection be implemented ?
Does it have an avalanche rating and is it better than Si devices ?
Any other special considerations when using SiC MOSFETs?
Rg.off
Ferrite Beads
Not Really – Take extra care to follow the
Rg.on
good
design practices for a high frequency
solid state power converter.
+20/-5V
Clamping
diodes
Solder probe tips
to measurement points
Cgs
© 2014 Cree, Inc.
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Good Design Practice for High Frequency Systems
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Minimize the loop area of the high frequency circuit.
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Close coupling of gate and gate return leads.
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Proper use of ground planes.
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Use of ferrite beads on gate lead.
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Kelvin source
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Use of Common Mode and differential mode filters.
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Cree recommended gate drivers
Ground Plane
Noisy
circuit
© 2014 Cree, Inc.
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Summary
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SiC MOSFETs outperform 650V and 1200V Si MOSFETs.
•
The value of SiC devices must be assessed in terms of benefits at a system
level and not at component level.
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Its easy to use SiC MOSFETs. They are not much different from using Si
MOSFETs or IGBTs.
•
Higher switching speed for SiC MOSFETs mean we must follow good design
practices when using SiC in any application.
•
SiC devices are now widely implemented in solar power inverters, EV
chargers and other DC/DC applications.
© 2014 Cree, Inc.
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Agenda
•
•
•
•
•
•
SiC vs. Si
LBC design consideration
Design considerations for SiC
Available tools
Cree product portfolio
Q&A
© 2014 Cree, Inc.
All rights reserved.
19
Available tools from Cree
© 2014 Cree, Inc.
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PSPICE
Models
SiC
Evaluation
Board
Reference
Designs
Application
Notes
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Available tools from Cree
C2MTM LTSPICE Models
• New Spice models available for C2MTM MOSFET family
• Accurate and Fast
• Models are available with or without package parasitics
• Models include thermal RC network
http://www.cree.com/Power/Tools-and-Support/MOSFET-model-request2
© 2014 Cree, Inc.
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21
Cree Spice Model
© 2014 Cree, Inc.
All rights reserved.
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Simulated data compared to measured data
IV data 99.7% accuracy at rated
operating conditions
© 2014 Cree, Inc.
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Switching Energy 96% accurate
across ID range
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Evaluation board for discrete components
– Avago Gate driver
– BNC Connector
– Ability to measure Vgs,
Vds and IDS
– High Voltage DC
Input and Caps
© 2014 Cree, Inc.
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Cree SiC Reference Designs
Universal Gate Driver Board
• SiC MOSFET gate driver board with isolation up
to 1700V. Available for purchase.
8kW ZVS Converter
• Zero-Voltage Switching LLC converter using SiC
MOSFETs
60W Auxiliary Power Supply
• 60W single-end HV flyback design based on Cree
1700V 1Ohm SiC MOSFET
10kW Boost Converter
• 100kHz interleaved boost converter with SiC
MOSFET and SiC Schottky Diodes
© 2014 Cree, Inc.
All rights reserved.
25
Cree Application Notes
• Application Notes and Articles
– CPWR-AN09: SiC double pulse test fixture
– CPWR-AN10: SiC MOSFET Isolated gate driver
– CPWR-AN12: Design Considerations: Effects of parasitic
Inductance
– CPWR-AN13: Design Considerations: Minimizing parasitic
Inductances
– CPWR-AN14: 60W Auxiliary Power Supply
© 2014 Cree, Inc.
All rights reserved.
26
Agenda
•
•
•
•
•
•
SiC vs. Si
LBC design consideration
Design considerations for SiC
Available tools
Cree product portfolio
Q&A
© 2014 Cree, Inc.
All rights reserved.
27
600V/650V Schottky Diodes
Product Families:
Characteristics:
Available package
options:
• CSD[-], C3D[-]
• CPW2[-], CPW3[-]
• Blocking voltage = 600V or 650V
• Forward current = 1A up to 20A
• Thru-hole: TO-220, Full-PAK, TO-247, Isolated TO-220
• Surface mount: DPAK (TO-252), D2PAK (TO-263), QFN
Forward Current
TO-220 TO-220
TO-252 TO-263
Rating (A)
Bare Die TO-220 FullPAK Isolated TO-247 DPAK D2PAK
1


1.7
2

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3
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4
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6
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**
**
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8

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
**

10



**

16

20

QFN

** Available soon!
© 2014 Cree, Inc.
All rights reserved.
28
1200V Schottky Diodes
Product Families:
• C4D[-]
• CPW4[-]
Characteristics:
• Blocking voltage = 1200V
• Forward current = 2A up to 40A
Available package
options:
• Thru-hole: TO-220, TO-247
• Surface mount: DPAK (TO-252)
© 2014 Cree, Inc.
All rights reserved.
Forward Current
Rating (A)
Bare Die
TO-220
2

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
5
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8
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
10
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15
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
20
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
TO-247
TO-252
DPAK

30

40

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MOSFETs
Product Families:
Characteristics:
• C2MTM
• Blocking voltage = 1200V or 1700V
• RDS(on) = from 1 down to 25m
Blocking
Voltage (V)
1200
1200
1200
1200
1200
1700
© 2014 Cree, Inc.
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RDS(on)
(m)
25
40
80
160
280
1000
DC Current
Rating (A)
90
60
32
18
10
5
Bare Die TO-247-3

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
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
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
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Cree SiC Devices for the Little Box Challenge
MOSFETs (VDS=1200V, TO-247)
• C2M160120D: RDS(on)=160m
• C2M080120D: RDS(on)=80m
Thru-hole Schottky (TO-220)
• C3D04060A: VRRM=600V, VF=4A
• C3D06060A: VRRM=600V, VF=6A
• C3D08060A: VRRM=600V, VF=8A
• C4D04120A: VRRM=1200V, VF=4A
Surface mount Schottky (DPAK & D2PAK)
• C3D04060E: VRRM=600V, VF=4A
• C3D06060G: VRRM=600V, VF=6A
• C3D08060G: VRRM=600V, VF=8A
• C4D04120E: VRRM=1200V, VF=4A
© 2014 Cree, Inc.
All rights reserved.
31
Summary
The Power of Silicon Carbide
• SiC power semiconductors are vastly superior to Si devices for
high voltage, high power density applications
• Demonstrated actual design examples and how they benefitted
from SiC
• Reviewed important design considerations
Cree is here to help
• Multiple design tools are available:
• Spice models
• Reference designs
• Apps Notes
• Large portfolio of SiC Schottky diodes and MOSFETs
• Samples are available for competition participants
© 2014 Cree, Inc.
All rights reserved.
32
SiC Technology is a Reality
•
All products shown today, as well as some of the designs, are commercially
available products from a wide range of distributors
© 2014 Cree, Inc.
All rights reserved.
33
Agenda
•
•
•
•
•
•
SiC vs. Si
LBC design consideration
Design considerations for SiC
Available tools
Cree product portfolio
Q&A
© 2014 Cree, Inc.
All rights reserved.
34
Questions and Answers
•
Q. Are there any 650V MOSFETs planned / Do you have plans for a surface
mount package?
•
A: For the LBC competition I would suggest participants focus on using our
existing 1200V C2M MOSFETs in TO-247 or bare die. These are
commercially released, qualified and easily available. We are focused on
providing users with new tools such as SPICE models and reference
designs to assist with the competition. Of course we are also exploring LV
and HV SiC MOSFETs in various packages but we have nothing we can
disclose at this time.
•
Q: Do you have any reliability data on your SiC MOSFETs?
•
A: YES, We have full qualification reports available on all of our released
C2M MOSFETs. In addition we have reliability reports on Gate Oxide, Body
Diode and Threshold stability we are willing to share with all participants.
You can send an email to Cree_LBC_support.com.
© 2014 Cree, Inc.
All rights reserved.
35
Questions and Answers
•
Q: What about 650V GAN? What advantages does SiC have over GAN?
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A: Cree is one of the largest producer of GaN devices for the RF power
market. When Cree decided to look for a mature technology to develop
power devices, we did consider both technologies and decided that SiC was
better suited for high-voltage power products and could cover a broader
market. Today we hear about new 600/650V GaN devices but they are
often hard to find commercially and thus difficult to make a reliable
comparison. But if you can find the devices and if they do work as
advertised then they are a viable option for the competition.
•
Q: What are the maximum allowed chip temperatures?
•
A: For our diodes the max rated junction temperature is 175C. For our C2M
MOSFETs the max Junction temp is 150C. We have been very
conservative in our max temp ratings for our devices to ensure customers
have rugged and reliable systems. We have demonstrated our diodes in
published papers are operate reliably at junction temperatures well above
200C. We have 3rd party partners that take our standard C2M MOSFET die
and put them into specialized packages and rate them above 200C. We
leave it to the end users to push the limits of the devices for the competition.
© 2014 Cree, Inc.
All rights reserved.
36
Questions and Answers
•
Q: For the gate driver, what will be the UVLO threshold level before the output
can be released to drive the SiC MOSFET?
•
A: UVLO for our module half bridge gate driver (CGD15HB62P) triggers when
the input supply voltage drops below 10.4V.
•
Q: How is it possible to increase driver's efficiency utilizing the voltages
suggested on datasheet? Are we going to have the need of high di/dt driver
system?
•
A: What we should note is that although the gate drive voltage swing is wider
(-5V to +20V) the gate capacitance is lower. Your driver efficiency on its own
should be very similar to other Si MOSFET drivers.
•
Q: What are the recommended ways for SiC MOSFET short circuit protection?
Is measuring VDS a good way to detect short circuit? If yes what will be the
VDS threshold to consider as short circuit?
•
A: We have implemented short circuit protection monitoring Vds. Same principle
as desat protection for IGBT. The exact threshold level will depend on the
particular SiC device you are trying to protect. But what we should note is that
when compared to IGBTs we have a lot less time to react to a short circuit (10us
versus <2us).
© 2014 Cree, Inc.
All rights reserved.
37
Questions and Answers
•
Q: What frequency is a limit for SiC? Do you have reference design with
500kHz switching freq.?
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A: There is not an inherent "frequency limit" for SiC MOSFETs or Diodes.
The lower turn-on and turn-off switching energies, combined with the low
device capacitances, allow our C2M MOSFET family to switch faster than
conventional Silicon MOSFETs. We do have an 8kW, ZVS LLC converter
reference design which switches up to 320 kHz
•
Q: Is a negative voltage is necessary to control the SiC?
•
A: No, a negative voltage is not required, the device will switch from 0 to
+18V or +20V, but having the -ve bias voltage reduces turn-off losses and
improves protection against dv/dt induced self turn on.
•
Q: Can you provide some recommendations on paralleling devices? or is it
the same as common Si ones?
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A: The new C2M SiC devices parallel very well. We have published a paper
on this topic at APEC 2014 by Dr. Gangyao Wang. We paralleled 4 of our
packaged discrete devices in this paper with recommendations.
© 2014 Cree, Inc.
All rights reserved.
38
Questions and Answers
•
Q: Besides the higher breakdown voltage, which other advantages do SiC
Schottky diodes have over Si Schottky diodes? Are they faster? Why?
•
A: One of the most significant advantages is that a commercial Si Schottky
diode is not currently available above 500V. The higher electric field
capability of SiC allows us to offer commercial Schottkys up to 1700V, and
we even have some R&D devices capable of 10kV. Our Schottkys also
employ an advanced structure that gives them exceptionally high surge
capability.
•
Q: Do you offer SiC inside power modules?
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A: Yes, we have several modules available with SiC MOSFETs and diodes,
from 20A modules to 300A modules.
•
Q: What are the materials issues (passive components) that need to be
solved in the Little Box Challenge?
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A: The top material needs we have identified are: high energy and power
density capacitors for the line-frequency energy storage, high-frequency
and low-loss magnetic core materials, and high performance thermal
interface materials to help with this challenging thermal design problem.
© 2014 Cree, Inc.
All rights reserved.
39
Questions and Answers
•
Q: Could you give a link or list the recommended gate drivers, please? Or are they easily
found on www.cree.com/MOSFETs?
•
A: These will be listed on our LBC Sample Request page.
•
Q: Do you have any power modules for motor control?
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A: Yes, our 45mm and 62mm modules that are commercially available today offer great
options for motor drives. They are available from 20A to 300A in 6-pack or half bridge
configurations.
•
Q: What do you think about use a multilevel topology for the inverter in the little box
challenge?
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A: Multilevel topologies are generally used in inverter applications when high-speed, lowloss power semiconductor technologies are not available at the voltages and currents
required for a two-level topology. Multiple devices are series-connected in order to achieve
the required blocking voltage and to meet output THD requirements by creating a stepped
sinusoidal output voltage. For this 240VAC output application, multilevel topologies are
required if you are considering using low-voltage power semiconductor devices. This adds
a lot of complexity and parts count vs. a two-level solution. The beauty of using SiC power
semiconductor devices in the inverter is that you can stay with a simpler two-level topology
to keep the topology and control complexity low, minimize parts count, and simply increase
switching frequency to minimize filter component size. The LBC support team has identified
a number of C2M MOSFETs and C4D Schottky diodes which are appropriate for this
simpler two-level approach.
© 2014 Cree, Inc.
All rights reserved.
40
Questions and Answers
•
Q: Commercially, which is the most common application that uses SiC MOSFET? PV inverter,
Motor drives etc?
•
A: The most successful markets for SiC MOSFETs thus far have been in solar, industrial power
supplies and battery chargers.
•
Q: How can I get a spice model for C2M0080120D?
•
A: You can request the spice model for any of our C2M MOSFETs on our MOSFET landing page
at www.cree.com/power
•
Q: What about zero voltage switching topologies ? Can they be used for LBC?
•
A: Yes, ZVS topologies can be used for the LBC. It is Cree’s understanding that Google will treat
your inverter as a black box and places no constraints on your topology or technology choices.
SiC MOSFETs are excellent candidates for zero voltage switching topologies for a few reasons.
Firstly, the C2M MOSFET family features extremely low output capacitance, which allows for ZVS
operation at high frequency in order to keep associated passive components small. Secondly,
ZVS operation essentially eliminates the turn-on switching loss and leaves only turn-off losses.
SiC MOSFETs feature extremely low turn-off losses. The net result is much improved efficiency
even at high switching frequencies.
•
Q: What do to you propose to reduce the high dV/dt of the turn on edge of SiC MOSFET apart
from changing Rg?
•
A: Probably the most important suggestion is to use different external gate resistors for the turn-on
and turn-off transients. This allows the designer to separately adjust the dV/dt during the turn-on
and turn-off transients. All of the other suggestions discussed in the webinar are also valid here:
use of ferrite beads on the PCB or on the device terminals, addition of a capacitor from gate to
source, or the use of an RC snubber from drain-to-source.
© 2014 Cree, Inc.
All rights reserved.
41
Questions and Answers
•
Q: Why is CREE recommending the 1200V 20 A 80mohm device instead of
the 1200V 90A 25ohm device for the LBC?
•
A: In our opinion, the 1200V 25mOhm device might be overkill for this
application, but you can certainly use any of our available devices
depending on your topology and strategy.
•
Q: What is the maximum current rating of body diode of 1200V SiC
MOSFET C2M technology?
•
A: Same rating as the MOSFET current rating. So, for example a 20A
MOSFET will also have a 20A body diode rating.
•
Q: When will you offer a higher current six pack above current 50A offering?
•
A: No plans at the moment, but our modules do parallel well for higher
power applications.
© 2014 Cree, Inc.
All rights reserved.
42
Questions and Answers
•
•
•
•
•
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Q: What is the surge capability of your SiC diodes?
A: The material properties of SiC described in the webinar give SiC diodes very
good surge capability. Our SiC Schottky diodes also employ a special structure
known as the Merged PiN Schottky (MPS), which enables exceptional surge
capability. We'll be publishing an article in the near future, describing the
features and advantages of MPS over standard Schottkys. In the interim, check
out Cree's datasheets for our Schottky diodes. You'll find the repetitive 10ms
forward surge is typically 5-7x the diode's current rating, and the non-repetitive
10microsecond forward surge capability is 50-75x the diode's current rating.
Q: Is including Ferrite bead the only way to minimize the gate ringing of SiC
MOSFET?
A: selecting the right Rg.on and Rg.off values, ferrite beads, tight layout of the
gate drive loop, small capacitance between gate and source are some of the
methods to reduce gate ringing.
Q: Do you have recommendation for derating margin of parameters for SiC
MOSFET?
A: The current rating is based on DC rating but in a switching application you
have the added losses generated by switching losses. These switching losses
are much higher for Si devices so the derating is lower SiC devices. We also
have better voltage margin between rated voltage and breakdown voltage.
© 2014 Cree, Inc.
All rights reserved.
43
Question and Answers
•
Q: Can you provide a recommendation on high density Energy storage elements?
•
A: Although Cree is not in the business of manufacturing energy storage systems, we did
discuss a few ideas to potentially better utilize today's aluminum electrolytic capacitor
technology. Topology Idea #2 would allow a designer to explore other energy storage
technologies such as various battery chemistries, supercapacitors, ultracapacitors, etc.
•
Q: How many Short Circuits could support a SiC MOSFET? Is there a limitation?
•
A: We have tested our over current circuit successfully for about 20 times in a row without
failures.
•
Q: What is the amount of reverse recovery charge of the body diode of C2M0080120D (not
including the diode reverse capacitance charge)?
•
A: This specification should be found in the device datasheet shortly. We are presently
updating the C2M datasheets with new body diode data.
•
Q: Do you plan to introduce a 1700V SiC MOSFET with higher current capability?
•
A: Yes, we plan to expand the 1700V C2M product family. Sign-up to our newsletter for
product release information.
•
Q: Who are the 3rd parties experimenting with the open die?
•
A: APEi, Cissoid and Micross are among some of the companies experimenting with our
die in advanced high-temperature packages.
© 2014 Cree, Inc.
All rights reserved.
44
Questions and Answers
•
Q: There is no documentation given for negative bias in the 1700V Aux
Power Supply reference design. Can you explain how it is achieved?
•
A: There are a few approaches for generating a gate driver negative bias
supply. The most generic (but expensive) method is to use a separate
isolated power supply. The 1700V reference design utilizes a Zener diode
and capacitor to create the negative bias. If a single isolated 24V power
supply is utilized, a 4V Zener and capacitor can be used to create a +20V / 4V total gate swing.
•
Q: Do you plan to introduce SiC MOSFET in ISOTOP package?
•
A: At the moment we have no plans for an ISOTOP package however we
have partners such as IXYS who have used our die in an SOT-227 isolated
package. Please contact IXYS for more information. Reference P/N
IXFN50N120SiC.
© 2014 Cree, Inc.
All rights reserved.
45