EE 587 SoC Design & Test

Partha Pande School of EECS Washington State University [email protected]

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Core & SoC Design Examples

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Design Flow

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IP Blocks in SoCs

 SoC jargon  Core  Intellectual Property (IP)  Virtual Component  Macro  …………… 4

Intellectual Property (IP) Blocks

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Available IP Cores

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IP Market Share

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VIPER – A Multiprocessor SoC

 Highly integrated SoC for digital TV  Digital Set-Top box  Viper receives, optionally decrypts, decodes, converts, and displays multiple media streams having different data formats .

 Besides MPEG-2 transport streams, the chip typically handles live video, audio, and various other stream types, in compressed or uncompressed formats.

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VIPER Architecture

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VIPER Architecture (cont’d)

 Two processor cores  standard 32-bit MIPS RISC core (PR3940) and a 32-bit very long instruction word (VLIW) TriMedia core (TM32)  The VLIW core handles Viper’s real-time multimedia processing tasks.

 PR3940 core is the second on-chip CPU to run the operating system and handle various control processing tasks.

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General Peripherals

 Enhanced IEEE 1394 link layer  Expansion bus interface  Drawing engines  Transport stream processor  Audio interfaces  Video-processing blocks 11

Complexity

 35 million transistors in 0.18 micron process  Synthesized in eight hours running on multiple CPUs  The design was partitioned into chiplets of 200k cells, with total nine chiplets  The chip was designed to be fully scan testable 12

Network Processing Platform

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INTEL IXP2400

 8 integrated programmable microengines  Integrated Intel XScale core  One DRAM and two SRAM interfaces  JTAG support  Additional Integrated hardware 14

Intel’s 80-core Chip

• Intel’s 80-core chip – In 65-nm technology with 80 single-precision, floating point cores delivers performance in excess of a teraflops while consuming less than 100 w.

– A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores.

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Overall Architecture

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SoB vs. SoC

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SoC Test

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Challenges in Testing a SoC

• One of the most critical challenges of this emerging discipline is manufacturing test.

• Core provider only delivers a description of the core design to the SOC designer.

• That is the IP of the vendor, who may provide only limited details of the design to the user.

• The user considers the core as a black-box.

• Accessibility to component peripherals 19

Conceptual Architecture of Core Test

• Three separate elements in the embedded core test infrastructure.

– Test pattern source and sink – Test Access Mechanism – Core test wrapper 20

Test Pattern Source & Sink

• The source generates the test stimuli and the sink compares the response to the expected response.

• Source and sink of a core can be implemented either off-chip, on-chip or as a combination of both • The choice for a certain type of source or sink is determined by – The type of circuitry in the core – The type of predefined tests that come with the core – Quality and cost considerations.

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Test Access Mechanism (TAM)

• It takes care of on-chip test pattern transport.

• The key components of any TAM are its width and length.

• The width refers to the TAM’s transport capacity.

• The length of a TAM is the physical distance it has to bridge between the source and core or core and sink .

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Implementation of TAM

• When implementing a TAM, we have the following options – A TAM can either reuse existing functionality to transport test patterns or be formed by dedicated test access hardware.

– A TAM can either go through other modules on the IC or pass around those other modules.

– One can either have an independent access mechanism per core, or share an access mechanism with multiple cores.

– A test access mechanism can either be a plain signal transport medium, or may contain certain intelligent test control functions.

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Core Test Wrapper

• Interface between the embedded core and its system chip environment.

• It connects the core terminals both to the rest of the IC, as well as to the TAM.

• It is implemented on chip .

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ARM’s AMBA System

• An example of reusing existing functionality as TAM.

• In this approach, the 32-bit system bus transfers test stimuli from IC pin to the core under test and test responses vice versa.

• Advantages of this approach – The low additional area cost – The relative simple test expansion • A disadvantage of the approach is that the fixed 32-bit bus does not allow to make trade-offs between area cost and test time 25

Connection of System Pins to Core Terminals

• Connect additional wires to the core’s terminals and multiplex those onto existing IC pins – testing of memories • The advantage of this approach is : the embedded core can be tested as if it were a stand alone device, the translation of core-level tests into IC-level tests is simple and straightforward.

• The disadvantage is : it is not scalable.

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Reuse of Boundary Scan

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What is scan ?

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Testability Measures

• •

Need approximate measure of:

–

Difficulty of setting internal circuit lines to 0 or 1 by setting primary circuit inputs

–

Difficulty of observing internal circuit lines by observing primary outputs Uses:

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Analysis of difficulty of testing internal circuit parts add special test hardware – redesign or

–

Guidance for algorithms computing test patterns – avoid using hard-to-control lines

– –

Estimation of fault coverage Estimation of test vector length

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Observability

• The

observability

of a particular circuit node is the degree to which we can observe that node at the output of an integrated circuit • Measure the output of a gate within a larger circuit to check whether it operates correctly • Limited number of nodes can be directly observed 30

Controllability

• The

controllability

of an internal circuit node within a chip is a measure of the ease of setting the node to a

1

or

0

metric • Degree of difficulty of testing a particular signal within a circuit • An easily controllable node would be directly settable via an input pad 31

Scan Design

PI1 PI2 OR SCANIN

COMBINATIONAL LOGIC

PO2 PO1 PO2 OR SCANOUT CK TC Multiplexer Flip-flop 32

Scan Design



In test mode, all flip-flops functionally form one or more shift registers



The inputs and outputs of these shift registers are made into PI/Pos



Using the test mode, all flip-flops can be set to any desired states



The states of the flip-flops are observed by shifting the contents of the scan register out

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Scan Design

– Circuit is designed using pre-specified design rules.

– Test structure (hardware) is added to the verified design: • Add a

test control

(TC) primary input.

• Replace flip-flops by

scan flip-flops

shift registers in the test mode.

(SFF) and connect to form one or more • Make input/output of each scan shift register controllable/observable from PI/PO.

– Use combinational ATPG to obtain tests for all testable faults in the combinational logic.

– Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. 34

Scan Design Rules

• Use only clocked D-type of flip-flops for all state variables.

• At least one PI pin must be available for test; more pins, if available, can be used.

• All clocks must be controlled from PIs.

• Clocks must not feed data inputs of flip-flops.

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D TC SD CK CK TC

Scan Flip-Flop (SFF)

Master latch Slave latch Logic overhead MUX D flip-flop Master open Slave open t Normal mode, D selected Scan mode, SD selected t

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Q Q

D SI

Scannable Flip-flop

SCAN PHI PHI_b PHI_b PHI PHI_b PHI 37

Bed-of-Nails Tester Concept

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Need for Standard

  Bed-of-nails printed circuit board tester We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance   Nails would hit components Reduced spacing between PCB wires  Nails would short the wires  PCB Tester must be replaced with built-in test delivery system -- JTAG does that   Need standard System Test Port and Bus Integrate components from different vendors  Test bus identical for various components  One chip has test hardware for other chips 39

Boundary Scan Architecture

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