Transcript Document
Agenda
DAY 1 1 Introduction 2 Verilog-A Modules 3 Simulating Variability – Design for Yield
Synopsys 60-I-032-BSG-005 © 2007 Synopsys, Inc. All Rights Reserved
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Unit Objectives
After completing this unit, you should be able to:
Use Verilog-A modules 2-
Introduction to Verilog-A
What is Verilog-A
Standard analog hardware description language The analog-only subset of Verilog-AMS Verilog-AMS LRM, version 2.2, released in November 2004
Verilog-A applications
Multi-level design simulation Compact models Analog test benches
Verilog-A in HSPICE
Compiled Verilog-A Solution Single kernel simulation
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Feature Overview (1/2)
Production since W-2005.03
Compiled-code Solution
High performance with golden accuracy
Supports up-to-date Verilog-A language features
Compatible with Verilog-AMS LRM 2.2
Provides industry standard compliant Verilog-A language support
Users can use existing Verilog-A code without any changes
Provides HSPICE Verilog-A device support with existing syntax
Verilog-A modules are instantiated in the same manner as HSPICE subcircuits
All major features available on HSPICE will be supported in Verilog-A based devices
Users do not lose any significant simulator functionality when simulating with Verilog-A based devices
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Feature Overview (2/2)
All major analysis types available on HSPICE are supported in Verilog-A based devices
DC analysis AC analysis (.AC, .LIN, .NET) Transient analysis (.TRAN, .FFT, .FOUR) Noise analysis Pole-Zero analysis Sweeping, Monte Carlo, Optimization Alter analysis
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Verilog-A Usage Overview
* Simple Verilog-A amplifier .hdl my_amp.va
vs 1 0 1 rs 1 0 1 x1 1 2 my_amp gain=10 rl 2 0 1 module my_amp(in, out); electrical in, out; parameter real gain = 1.0; analog begin V(out) <+ gain * V(in); end endmodule .print tran V(x1.in) I(x1.out) x1:gain
Verilog-A modules are loaded into the system via “ .hdl
” command
Modules are instantiated with the same syntax as HSPICE subcircuits
Verilog-A device data can be output using conventional output commands 2-
Loading Verilog-A Files (1/2)
Two ways to load Verilog-A files
.hdl
netlist command Follows the syntax of NanoSim
Examples: .hdl “my_amp.va” .hdl “va_res” $$ searching for va_res.va file
-hdl command line option Allows simulations to choose whether Verilog-A modules are used or not Verilog-A modules can be changed without netlist modification Each Verilog-A file used needs one –hdl option
Examples: hspice test.sp –hdl pll.va –vamodel –o test hspice input.sp –hdl my_amp.va –o va_test hspice pll.sp –hdl chrgp –hdl vco –o pll_test
A Verilog-A file is assumed to have the .va extension when only prefix is supplied 2-
Loading Verilog-A Files (2/2)
The .hdl
command may be placed anywhere in the top-level circuit
Can be placed in
.alter
blocks Cannot be inside subcircuit definition Cannot be inside if-else statement
The -hdl is the command line equivalent to the netlist .hdl command
-hdl has higher priority than .hdl netlist command
If a Verilog-A module has the same name as a previously loaded module, or the names differ in case only, the later one will be ignored
If a Verilog-A module has name conflict with any HSPICE built-in model name, the Verilog-A definition will be ignored
Built-in model name: R, C, D, L, N/PMOS, NPN, PNP, etc.
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Defining the Verilog-A Module Path
Two methods to define the Verilog-A module search path
-hdlpath command line option Example:
hspice amp.sp –hdlpath ~/vamodules –hdl amp.va
HSP_HDL_PATH environment variable Example:
setenv HSP_HDL_PATH ~/shared_libs/veriloga
The directory search order for Verilog-A files
Current working directory Path defined by –hdlpath Path defined by HSP_HDL_PATH
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Instantiation Syntax
Verilog-A devices are X devices in HSPICE netlist
Syntax X
Verilog-A devices may have zero or more nodes and, zero or more parameters Example: Xva_r plus minus va_r res=100
Verilog-A module may be instantiated directly or instantiated via an associated Verilog-A model card
Default HSPICE search order for cell definition for X devices
Subcircuit Definition Verilog-A Model Cards Verilog-A Module Definition
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Verilog-A Model Cards
Model card is a parameter sharing mechanism
When parameter sets are almost the same they can be shared among many instances Advantage to compact model
Syntax is the same for Verilog-A devices as for built-in devices
Verilog-A model syntax .model modelName modelType param=value modelType - Verilog-A module name, cannot conflict with built-in model types (e.g., R, C, D, etc.) modelName - model name reference used by the instance Example: .model my_bjt_va bjt_va rb=6.5 rc=6.3 re=0.15 2-
Instantiation Examples (1/2)
// Verilog-A module example module va_amp(in, out); electrical in,out; parameter real gain=1.0, fc=100e6; analog begin … endmodule
One Verilog-A module can have one or more optional associated model cards
Examples:
.model myamp_model va_amp gain=2 fc=200e6 .model myamp_model_2 va_amp gain=10
Any module parameter can be specified on its model cards or on the instance Instance parameters override model parameters
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Instantiation Examples (2/2)
Instantiations of Verilog A module ‘va_amp’ x1 n1 n2 myamp x2 n3 n4 myamp gain=2.0 x3 n5 n6 myamp2 fc=150e6 x4 n7 n8 va_amp
x1 inherits model ‘myamp’ parameters gain=2, fc=200e6
x2 inherits ‘fc=200e6’ from ‘myamp’ and overrides ‘gain’
x3 inherits parameter “gain=10” from model ‘myamp2’ and overrides parameter ‘fc’ which is an implicit parameter in ‘myamp2’
x4 directly instantiates the Verilog A module ‘va_amp’ 2-
Parameter Case Sensitivity
Verilog-A is case sensitive
HSPICE is case insensitive
Module parameters that differ by case only cannot be redefined in its netlist instantiations
Example: module my_amp(in, out); electrical in, out; parameter real g ain = 1.0; parameter real G ain = 1.0; analog V(out) <+ ( G ain+ g ain)*V(in); endmodule
If the user instantiates the module as: x1 n1 n2 my_amp G ain=1
The simulator cannot uniquely define which parameter is to be set
A warning message regarding the ambiguity is issued and the definition of the parameter is ignored
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Bus Support
Verilog-A supports the concept of bus (vector ports)
HSPICE does not
When instantiating a module which has vector ports, the individual bus lines need to be specified
The Verilog-A module will internally collapse the lines and connect them up to the vector port Example: module d2a(in, out); electrical [1:4] in; electrical out; analog … ** Instantiation of module d2a x1 in1 in2 in3 in4 o1
The lines in1 -> in4 are mapped to ports in[1] -> in[4] Make sure that the instantiation order matches the vector port order defined in the module
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Output Control (1/2)
Output for Verilog-A devices:
Direct port voltage access Direct port current probing Internal node voltage access Internal named branch probing Module parameter value Module variable value
V() and I() access functions
Port voltage and internal node voltages are accessed via the V() function Internal node access requires the full hierarchical name Port current and named branch currents are accessed via the I() function
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Output Control (2/2)
Reporting Convention for Currents
A positive branch current implies that current is flowing into the device terminal or internal branch
plus I(xva_1:plus) Xva_r minus I(xva_1:minus)
Module Parameter Output Syntax
Instance_name:parameter Example:
.print xva_r:reff 2-
Output Control Example (1/2)
Verilog Module // Verilog-A module module va_fnc(plus, minus); electrical plus, minus; electrical int1, int2; parameter real r1=0, r2=0; branch (int1, int2) br1; // creates an internal branch br1 between // internal nodes int1 and int2; child_module c1 (plus, int1); child_module c2 (minus, int2); … Endmodule
Verilog-A device in netlist x1 1 2 va_fnc r1=1 r2=2 2-
Output Control Example (2/2)
To print the current on Verilog-A device port name plus for the instance x1: .print I(x1.plus)
To print the Verilog-A module internal node named int1 for the instance x1: .print V(x1.int1)
In this module there is an internal branch name br1 declared then, the branch current can be probed as: .print I(x1.br1)
If the module va_fnc is hierarchical and has a child instance called c1 with an internal node c_int1 then the node c_int1 can be output as: .print V(x1.c1.c_int1)
Wildcarding can be use to output internal nodes, int1 and int2 for the child c1 in the instance x1: .print v(x1.c1.int*) 2-
Overriding Subcircuits with Verilog-A Modules
If both a subcircuit and a Verilog-A module have the same case insensitive name, by default, HSPICE uses the subcircuit definition
Vamodel option lets Verilog-A definition take preference
Supports cell-base definition only
Can be specified as a netlist option or a command line option
Netlist option syntax:
.option vamodel [=name] Examples:
.option vamodel=vco vamodel=chrgpump
– Instances of vco and chrgpump will use Verilog-A definition
.option vamodel
– All cell instantiations will use Verilog-A definition whenever it is available
Command line option: –vamodel hspice input.sp –hdl va_models –vamodel chrgpump –vamodel vco 2-
Disabling .option VAMODEL with .option SPMODEL
.option spmodel switches back to HSPICE definition
Supports cell-based definitions only Useful for .ALTER blocks
Netlist Syntax .option spmodel [=name]
Examples: Specific module
.option spmodel=vco
Assuming switched to a Verilog-A module in an earlier .alter block Instantiations of
vco
will use subckt definition again Global
.option spmodel
All cell instantiations will use subckt definitions
There is no equivalent command line option for spmodel 2-
Addition Information – vamodel and spmodel
Command line option -vamodel has preference over any netlist vamodel or spmodel options Example: hspice va_opt.sp –hdl va_models –vamodel my_cap
Every run uses the Verilog-A definition for cell my_cap
Specific vamodel and spmodel options have preference over global options Examples: * va_opt.spi
* all will use Verilog-A definition whenever available .option vamodel .alter 1 * all will use subckt definition whenever available .option spmodel .alter 2 .option vamodel=my_cap $$ my_cap will use Verilog-A .option spmodel $$ my_cap will still use Verilog-A … 2-
Stand-Alone Compiler
Verilog-A files can be compiled manually using the hsp-vacomp command
Input a Verilog-A file, compiler produces a Compiled Model Library (CML) file
A .cml file is a platform and version specific shared library .cml files can be directly loaded
Compiler Example:
% hsp-vacomp resistor.va
Produces
resistor.cml
in the same directory
Load Example: .hdl resistor.cml $$ load resistor.cml
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Verilog-A Examples
Examples of typical Verilog-A modules with HSPICE netlists are located at: $installdir/demo/hspice/veriloga/ 2-
Lab 2: Verilog-A Modules
45 minutes During this lab, you will: 1.
Use Verilog-A modules in a circuit 2.
3.
Simulate the circuit View the simulation results Netlist Setup Simulation CosmosScope 2-