Transcript Dynamic and Pass-Transistor Logic
Dynamic and Pass-Transistor Logic
Prof. Vojin G. Oklobdzija
References (used for creation of the presentation material):
1.
Masaki,
“ Deep-Submicron CMOS Warms Up to High-Speed Logic ”
, IEEE 2.
3.
Krambeck, C.M. Lee, H.S. Law,
“ High-Speed Compact Circuits with CMOS ”
, V.G. Oklobdzija, R.K. Montoye,
” “ Design-Performance Trade-Offs in CMOS-
1986.
References:
4.
5.
6.
7.
Goncalves, H.J. DeMan,
“ NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures ”
, IEEE Journal of Solid State Circuits, Vol. SC-18, No 3, June 1983.
L.G. Heller, et al,
“ Cascode Voltage Switch Logic: A Differential CMOS Logic Family ”
, in 1984 Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1984.
L.C.M.G. Pfennings, et al,
“ Differential Split-Level CMOS Logic for Subnanosecond Speeds ”
, IEEE Journal of Solid-State Circuits, Vol. SC-20, No 5, October 1985.
K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques:
Differential Cascode Voltage Switch Logic Versus Conventional
Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4, August 1987.
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 2
References:
Pass-Transistor Logic:
8.
9.
10.
11.
12.
S. Whitaker,
“ Pass-transistor networks optimize n-MOS logic ”
, Electronics, September 1983.
K. Yano, et al,
“ A 3.8-ns CMOS 16x16-b Multiplier Using Complementary Pass-Transistor Logic ”
, IEEE Journal of Solid State Circuits, Vol. 25, No 2, April 1990.
K. Yano, et al, Performance and Cost of Logic LSIs", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
“ Lean Integration: Achieving a Quantum Leap in
M. Suzuki, et al,
“ A 1.5ns 32b CMOS ALU in Double Pass Transistor Logic ”
, Journal of Solid-State Circuits, Vol. 28. No 11, November 1993.
N. Ohkubo, et al,
Pass-transistor Multiplexer
Integrated Circuits Conference, San Diego, California, May 1 4, 1994.
“ A 4.4-ns CMOS 54x54-b Multiplier Using ”
, Proceedings of the Custom Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 3
References:
13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value Logic For Low-Power CMOS,” Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995.
14. F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with
the Pass-Gate (DCVSPG) Logic Tree for High Performance
CMOS Digital Systems”, Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995 15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass-
Transistor Logic Based Multiply and Accumulate Circuit for
Multimedia Applications”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
16. T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco February 8, 1996.
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 4
Pass-Transistor Logic
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 5
B B
Pass-Transistor Logic
A
F
0 0 0
A
1 1
F B
1 1 0 A (a) B (b) B (a) XOR function implemented with pass-transistor circuit (b) Karnaough map showing derivation of the XOR function Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 6
X Y
Pass-Transistor Logic
A
F
A General topology of pass transistor function generator Karnaough map of 16 possible functions that can be realized X 0 0 1 1 0 0 1 1 B B B B B B B B Y 0 1 0 1 B
B
B
B
B
B
B
B
0 1 0 1
F
0 A
A
1 AB
A A A B
B B A B A B
A+B
A
B B A
A
B
B B
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Pass-Transistor Logic
A A B Function generator implemented with pass transistor logic P 0 B Fall 2004 P 1 P 2 P 3 Prof. V. G. Oklobdzija: High-Performance System Design F(A,B) 8
Pass-Transistor Logic
B=V dd B A=V dd +
V th
-
F max =
V dd
-V th
C out A (a) Threshold voltage drop at the output of the pass transistor gate V dd V dd +
V th
-
V th
V dd +
F max =
V dd
-V th
C out (b) Voltage drop does not exceed Vth when there are multiple transistors in the path Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 9
Pass-Transistor Logic
In=V dd +V dd A=V dd +
V th
-
F max =
V dd V dd +
V th
V dd ON C out C in V dd A=0V (a) (b) Elimination of the threshold voltage drop by: (a) pairing nMOS transistor with a pMOS (b) using a swing-restoring inverter Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 10
Complementary Pass-Transistor Logic (CPL)
Pass Variables
Inputs
Control Variables f f
Fall 2004 F F Prof. V. G. Oklobdzija: High-Performance System Design 11
B B A
Basic logic functions in CPL
B B A A B A A A A A B B B C C A B B A A C B C B B A B B A A B
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CPL Logic
A A A A B n1 n2 B B n3 n4 B C Q Qb C S S (a) (b) S S XOR gate Sum circuit CPL provides an efficient implementation of XOR function Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 13
CPL Inverter
Level Restoration Transistor
Input
Output Inverter
Output
Feedback Inverter
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A B
Double Pass-Transistor Logic (DPL):
V DD
AND/NAND
A B B A A B B A B A B A
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O O A B A B A B A O B O A B A B
XOR/XNOR Prof. V. G. Oklobdzija: High-Performance System Design
A B
15
B B
Double Pass-Transistor Logic (DPL):
A A A A B B n1 p2 n1 p2 p1 p1 n2 n2 C C O Q (a) Qb XOR O S S (b) One bit full-adder: Sum circuit Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 16
A A B B A A B B
Double Pass-Transistor Logic (DPL):
AND/NAND Vcc
DPL Full Adder
C C Vcc S
Fall 2004
Vcc S Multiplexer
The critical path traverses two transistors only
OR/NOR
Prof. V. G. Oklobdzija: High-Performance System Design
Buffer
(not counting the buffer) 17
Formal Method for CPL Logic Derivation
Markovic et al. 2000 ( a) Cover the Karnaugh-map with largest possible cubes (overlapping allowed) (b) Express the value of the function in each cube in terms of input signals (c) Assign one branch of transistor(s) to each of the cubes and connect all the branches to one common node, which is the output of NMOS pass-transistor network Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 18
Formal Method for P-T Logic Derivation
Complementary function can be implemented from the same circuit structure by applying complementarity principle:
Complementarity Principle:
Using the same circuit topology, with pass signals inverted, complementary logic function is constructed in CPL.
By applying duality principle, a dual function is synthesized:
Duality Principle:
Using the same circuit topology, with gate signals inverted, dual logic function is constructed.
Following pairs of basic functions are dual: AND-OR (and vice-versa) NAND-NOR (and vice-versa) XOR and XNOR are self-dual (dual to itself) Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 19
A B
Derivation of P-T Logic
AND A B NAND 0 0 0 B 1 0 A 1 0 L 1 A L 2 1 L 2 B L 1 B B A B OR 0 0 1 B 1 1 A 1 1 L 1 A L 2 0 L 2 B L 1 B B A B A 0 B 0 1 1 1 OR B B 1 1 L 1 A L 1 0 L 2 B L 2 AND NAND (OR) OR Copmplementarity: AND Fall 2004 NAND; Duality: AND Prof. V. G. Oklobdzija: High-Performance System Design OR 20
Derivation of CPL Logic
Complementarity: AND NAND A B 0 0 0 B 1 0 A 1 0 1 L 1 (a) L 2 B B A L 2 B L 1 AND (b) A NAND B B B A B A OR NOR (c) Duality: AND NAND OR NOR B Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 21
B B
Two-Input Function with balanced input load
B A B A B A A B A A B B A A NOR AND (a) NAND OR
C in
C drain
C gate
(b) Fall 2004
Each input A, B, or A, B has FO=2
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Derivation of CPL Logic
A B 0 0 0 B 1 1 A L 2 A L 1 A B B A 1 1 0 Fall 2004 L 1 L 2 XOR XNOR (a) (b) (a) XOR function Karnaugh map, (b) XOR/XNOR circuit Prof. V. G. Oklobdzija: High-Performance System Design 23 A
Synthesis of three-input CPL logic
A BC 00 0 0 01 C 11 0 0 A 1 0 L 3 0 (a) 1 B 0 10 0 L 1 L 2 A A B B A L 1 C L 2 B L 3 A C B AND NAND (b) (a) AND function Karnaugh map, (b) AND/NAND circuit Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 24
Circuit realization of 3-input AND/NAND function
A BC 00 0 0 01 C 11 0 0 A 1 0
C
3 0 (a) 1 B 10 0
C
1
C
2 0 A A B B
C
1 A C B
C
2 AND
C
3 (b) A C NAND B Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 25
Double Pass-Transistor Logic (DPL): Synthesis Rules
1. Two NMOS branches can not be overlapped covering logic 1s. Similarly, two PMOS branches can not be overlapped covering logic 0s.
2. Pass signals are expressed in terms of input signals or supply. Every input vector has to be covered with exactly two branches.
At any time, excluding transitions, exactly two transistor branches are active (any of the pairs NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are possible), i.e. they both provide output current.
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Double Pass-Transistor Logic (DPL): Synthesis Rules
Complementarity Principle: function in DPL is generated after the following modifications: Complementary logic •
Exchange PMOS and NMOS devices. Invert all pass and gate signals
Duality Principle: generated when: Dual logic function in DPL is •
PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged.
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A B 0 0 0 A 1 B 1 0 L 3 0 1 L 1 (a) L 2 L 4
DPL Synthesis:
A B L 4 B A L 2 A A L 3 B GND L 1 GND AND (b) A B B B A +V DD +V DD NAND (a) AND function Karnaugh map (b) AND/NAND circuit Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 28
DPL Synthesis: OR/NOR circuit
+V DD +V DD B A A B A B OR NOR A B A B B A GND GND Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 29
XOR/XNOR in DPL
A B (PMOS)
C
1 0 B 1 (PMOS)
C
2 A A A A B B B B 0 A 1 0 1 1 0
C
3 (NMOS)
C
4 (NMOS) A
C
1
C
4 A
C
2
C
3 XOR A A B B B (a) (b) Fall 2004 Circuit realization of 2-input XOR/XNOR function in DPL, with balanced input load Prof. V. G. Oklobdzija: High-Performance System Design B XNOR 30
DPL Synthesis:
A A B 0 B 1 B L 4 A L 2 B L 3 A B A B 0 0 0 A L 4 AND 1 0 1 A B A B L 1 L 2 L 3 L 1 GND GND +V DD (a) (b) AND function Karnaugh map AND/NAND circuit +V DD NAND
Complementarit
y Principle:
Exchange PMOS and NMOS devices. Invert all pass and gate signals AND
NAND
A A +V DD B B +V DD OR A A B B B A NOR Duality Principle:
GND signals are exchanged:
AND OR
PMOS and NMOS devices are exchanged, and VDD and
NAND NOR Fall 2004 B A GND GND Prof. V. G. Oklobdzija: High-Performance System Design 31
DVL Logic
Advantage of CPL and DPL were recognized in DVL which attempts to generalize pass-transistor networks and minimize the number of transistors and input loads.
Rules:
1.
Cover all input vectors that produce “0” at the output, with largest possible cubes (overlapping allowed) and represent those cubes with NMOS devices, with sources connected to GND 2.
Repeat step 1 for input vectors that produce “1” at the output and represent those cubes with PMOS devices, with sources connected to V dd 3.
Finish with mapping input vectors, not mapped in steps 1 and 2 (overlapping with cubes from steps 1 and 2 allowed) that produce”0” or “1” at the output. Represent those cubes with parallel NMOS (good pull-down) and PMOS (good pull-up) branches, with sources connected to one of the input signals
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Two input AND/NAND in DVL Logic
A B 0 0 0 B 1 0
C
3 A 1 0 1
C
1 (a)
C
2 A A B
C
3 B
C
2
C
1 AND A ( B*) A ( A*) B V dd B (b) V dd NAND Circuit realization of 2-input AND/NAND function in DVL Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 33
A
Two input OR/NOR in DVL Logic
B A A B OR NOR B A B V dd V dd Circuit realization of 2-input OR/NOR circuit in DVL XOR/XNOR realization is identical to that of DPL.
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Three input AND function in DVL Logic
A BC 00 0 0 01 C 11 0 0 10 0
C
1 A A C A 1 0
C
2 0 (a) 1 B 0
C
3 A
C
2 B
C
1 B
C
3 B
C
3 AND (b) Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 35
A
Three input OR/NOR in DVL
V dd C C A A A A B B B A B B B OR NOR
Circuit realization of 3-input OR/NOR functions in DVL
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Comparison
TABLE I. Realizations of 3-input function F=B’C+ABC’ Realization CMOS # of input signals 9 DVL (b) DVL (c) 9 9 Signal termination 10G 8G + 6S 7G + 3S Trans.
Count 10 8 7 Output load 4S 6S 4S Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 37
A BC 00 0 0 A 1 0 (a)
C
2 01 C 11 1 0 1 0 10 0 1 B V dd
C
1 A Fall 2004 A B B C
C
2 C
C
1 B C B C
Comparison
BC C A 00 01 11 10 0 1 0 0 0 A 1 0
C
1 (b)
C
2 1 0 B 1
C
3 A BC 00 0 0 A 1 0
C
1 (c) 01 C 11 1 0 1 0 10 0 1
C
2 B C A C B B B B F B C C
C
1
C
1
C
2
C
2
C
3
C
3 F B B F B C B C C C
C
3
C
3
C
2 C B C A A Realizations of 3-input function F=B’C+ABC’ (a) Standard CMOS, (b) DVL, (c) DVL F = B C + A B C Prof. V. G. Oklobdzija: High-Performance System Design 38
C
3
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Conclusion
General rules for synthesizing logic gates in three representative pass-transistor techniques were shown. An algorithmic way for generation of various circuit topologies (complementary and dual circuits) is discussed. Generation of circuits with balanced input loads is suitable for library based designs is possible if complementarity and commutative principles are applied. This lays the foundation for development of computer aided design (CAD) tools capable of generating fast and power-efficient pass-transistor logic.
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