Transcript Dynamic and Pass-Transistor Logic

Dynamic and
Pass-Transistor
Logic
Prof. Vojin G. Oklobdzija
References (used for creation of the presentation material):
1.
2.
3.
Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE
Circuits and Devices Magazine, November 1992.
Krambeck, C.M. Lee, H.S. Law, “High-Speed Compact Circuits with CMOS”,
IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982.
V.G. Oklobdzija, R.K. Montoye, “Design-Performance Trade-Offs in CMOSDomino Logic”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April
1986.
References:
4.
5.
6.
7.
Goncalves, H.J. DeMan, “NORA: A Racefree Dynamic CMOS
Technique for Pipelined Logic Structures”, IEEE Journal of SolidState Circuits, Vol. SC-18, No 3, June 1983.
L.G. Heller, et al, “Cascode Voltage Switch Logic: A Differential
CMOS Logic Family”, in 1984 Digest of Technical Papers, IEEE
International Solid-State Circuits Conference, February 1984.
L.C.M.G. Pfennings, et al, “Differential Split-Level CMOS Logic for
Subnanosecond Speeds”, IEEE Journal of Solid-State Circuits,
Vol. SC-20, No 5, October 1985.
K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques:
Differential Cascode Voltage Switch Logic Versus Conventional
Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4,
August 1987.
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Prof. V. G. Oklobdzija: High-Performance System Design
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References:
Pass-Transistor Logic:
8.
9.
10.
11.
12.
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S. Whitaker, “Pass-transistor networks optimize n-MOS
logic”, Electronics, September 1983.
K. Yano, et al, “A 3.8-ns CMOS 16x16-b Multiplier Using
Complementary Pass-Transistor Logic”, IEEE Journal of SolidState Circuits, Vol. 25, No 2, April 1990.
K. Yano, et al, “Lean Integration: Achieving a Quantum Leap in
Performance and Cost of Logic LSIs", Proceedings of the
Custom Integrated Circuits Conference, San Diego, California,
May 1-4, 1994.
M. Suzuki, et al, “A 1.5ns 32b CMOS ALU in Double PassTransistor Logic”, Journal of Solid-State Circuits, Vol. 28. No
11, November 1993.
N. Ohkubo, et al, “A 4.4-ns CMOS 54x54-b Multiplier Using
Pass-transistor Multiplexer”, Proceedings of the Custom
Integrated Circuits Conference, San Diego, California, May 14, 1994.
Prof. V. G. Oklobdzija: High-Performance System Design
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References:
13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value
Logic For Low-Power CMOS,” Proceedings of the 1995
International Symposium on VLSI Technology, Taipei, Taiwan,
May 31-June 2nd, 1995.
14. F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with
the Pass-Gate (DCVSPG) Logic Tree for High Performance
CMOS Digital Systems”, Proceedings of the 1993 International
Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995
15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass-
Transistor Logic Based Multiply and Accumulate Circuit for
Multimedia Applications”, Proceedings of the Custom Integrated
Circuits Conference, San Diego, California, May 1-4, 1994.
16. T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of
Technical Papers, 1996 IEEE International Solid-State Circuits
Conference, San Francisco February 8, 1996.
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Dynamic CMOS Logic
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(a) Dynamic CMOS Latch
(b) Dynamic CMOS Master-Slave Latch
Dynamic
Node
In
I1
I2
X
Out
In
I1
(a)
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I3
Y
Cx
Cx
Store
I2
X
Out
Cy
Clock
(b)
Prof. V. G. Oklobdzija: High-Performance System Design
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Dynamic Manchester Carry Chain
precharge
pi
p i 1
+ Vdd
+ Vdd
+ Vdd
+ Vdd
pi 2
pi3
C i3
Ci
Gi
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G i 1
Gi 2
Gi3
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Radiation induced charge
“1”
+
-
+
-
+ Cin
-
+
“0”
-
-
 -particle
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+
+
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(a) Accidental charge caused by capacitive or inductive coupling
between the signal lines Y and Z.
v(Z)
Z
“1”
Line1
Line2
MP1 (open)
X=0
charge
v(Y)
+++
MN1
MP1
Cin
”0"
ON
(a)
(b) Prevention by inserting and inverter between the affected line
and the pass-transistor switch
Z
MP1
Y
MN1
Inserted
invertor
Cin
(b)
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CMOS Domino Logic
+Vcc
fD
+Vcc
p-type transistor
network
f
N
N
f
f
n-type transistor
network
n-type transistor
network
f
Clk
GND
(a)
GND
(b)
CMOS logic block (a), Domino Logic (b)
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CMOS Domino Logic
Operation
Precharge phase
Evaluation phase
+Vcc
+Vcc
Q1
Q2
++
N
0
0
ON
+ ++
++
1
0
0
F
Inputs
Inputs
0
1
Clock
0
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Q3
F
N
1
1
f
1
Clock
f
Discharge
ON
Q4
OFF
ON
GND
GND
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CMOS Domino Logic Operation
+Vcc
+Vcc
Q2
10
+Vcc
Q2
10
Q2
N
1
10
1
f
1
f
1
Inputs
Q4
1
Clock
0
Inputs
1
Inputs
N
1
1
N
Inputs
f
1
10
+Vcc
f
N
1
1
1
Q2
Q4
1
GND
Q4
01
GND
Q4
GND
GND
Dominos
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CMOS Domino Logic: Charge ReDistribution
+Vcc
+Vcc
Q1
Q2
N + + +1
++
Charge
++
0
0
0
1
F
Charge
Re-distribution
f
0
Q3
Clock
GND
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++
F
Inputs
0
Clock
N
1
1
f
Inputs
0
Q4
GND
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Variations of CMOS Domino Logic:
NORA Logic
+Vcc
+Vcc
F1
Q4
Q5
Clock
1
GND
F1
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n-type
transistor
network
p-type
transistor
network
n-type
transistor
network
0
Q3
Q2
Q1
Clock
+Vcc
F2
Clock
Q6
0
GND
GND
F2
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F3
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CVS and DCVS Logic
IBM
(Heller et al. 1984)
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Cascode Voltage Switch Logic: CVS IBM
+Vcc
small keeper
transistor
f
N
n-type transistor
network
f
Input
Signals
Clock
Precharge
evaluation
GND
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DCVS Logic (IBM)
+Vcc
Q1
Q2
F
Diff.
inputs
F
Combinational
logic network
n- MOS
Diff.
inputs
GND
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DCVS Logic (IBM)
Vdd
Q
differential
inputs
N1
Vdd
N2
n-fet
trees
Q
Q
N1
differential
inputs
Clock
Q
N2
n-fet
trees
Clock
(a)
(b)
Differential Cascode Voltage Switch Logic:
(a) Static DCVLS (b) Dynamic DCVSL
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DCVS Logic vs CMOS
VDD
VDD
f
f
f
N1
differential
inputs
N2
n-MOS transistor
switching
trees
f
f
f
inputs
f
Shared
Transistors
DCVS Logic consisting of two
shared nMOS transistor
switching networks
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CMOS consisting of two
separate: nMOS and pMOS
transistor switching networks
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Transistor sharing in DCVS Logic:
Implementation of 3-input XOR function
Q
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Q
A
A
A
A
B
B
B
B
C
C
Q = a b c
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Switching Asymmetry in DCVSL
V DD
1
V DD
a
a
ON
A
B
C
V DD
1
0
++++
++++
1
+ A
ON
+
0
B
0
ON
b
+
A
OFF
+
1
OFF
a
0
C
B
C
c
a
ON b
+a
++
+
1
+ A
ON
1
0
B
0
ON b
++ 1 a
++
+ ++ +
A
OFF
+
1
OFF
b
c 0
0
C
OFF
B
A
B
C
ON
+
C
Vdd
c
a
This asymmetry causes
current spikes and
increased power
consumption !
b
a
c
Both paths ON
Fall 2004
time
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