Transcript Welcome to Samsung Electronics

Spin Transfer Torque Workshop
September 22, 2008, Tsukuba, Japan
Manufacturing Issues
in High Density STT-MRAM
JANG EUN LEE
Process Development Team, Memory Division
SAMSUNG ELECTRONICS Co., Ltd
2015-07-17
Contents
 STT-MRAM Application
 Process Integration
 Key Parameters for STT-MRAM Development
–
–
–
–
Reliability of MgO Tunnel Oxide
Switching Current Density
Read-write Margin
Thermal Stability
 STT-MRAM Roadmap
 Key Issues in STT-MRAM Manufacturing
 Conclusion
1
STT-MRAM Application
Mobile
Device
CPU
MRAM
SSD
. Working Memory
. SSD Interface
. Code Storage
. NAND Flash
. RRAM
 One chip solution : Device performance
Cost down
 Post DRAM application @ sub 30nm, 2012
 Embedded memory @ L22
2
Key Parameters for STT-MRAM
Development
1) Reliability of MgO
2) Switching current density (Jc)
For reliable operation during 1015
cycling test, Breakdown voltage
. Max. writing Voltage
. Max. reading Voltage
Key factor of STT-MRAM scaling
. Depending on reading margin
State of art Switching current
density : 1~2MA/cm2
STT-MRAM
Development
For large reading margin,
. Low RA & high Jc
. MR > 150%
Thermal instability due to
volume decrease at small cell
For data retention at 85C,
KuV/kBT > 6 0
Uniform cell size in sub-30nm
3) Thermal Stability
4) Reading Margin
3
Writing Current vs. Scalability
MTJ A/R =2
X
Y
Switching Current (uA)
1000
1.E+07
5.E+06
3.E+06
2.E+06
1.E+06
1-Cell Tr
2-Cell Tr
100
10
Ion (@ITRS roadmap)
1
0
20
40
60
80
MTJ width (nm)
4
100
Writing Current vs. Scalability
MTJ A/R =1
Switching Current (uA)
1000
X
Y
1.E+07
5.E+06
3.E+06
2.E+06
1.E+06
1-Cell Tr
2-Cell Tr
100
10
Ion (@ITRS roadmap)
1
0
20
40
60
80
MTJ width (nm)
5
100
Critical Switching Current Density (Jc)
Switching Current Density (A/cm
2
)
Cornell
100M
IBM
Cornell
AIST
Paris-sud
MSU
SpinTech
MSU
Cornell
10M
GRANDIS
SEC
Sony
1M
Freescale
TOSHIBA
HITACHI
Tohuku
SEC
GRANDIS
Metallic Spin valve
MgO
100k
2000
2002
2004
Year
6
2006
2008
Reading Margin
 Resistance distribution of large cell
Ron
Ref
Roff
: ΔR/σ(Rp) = 116.4 (400nm x 800nm)
 MgO tunnel barrier is very uniform
R/2
 Small size MTJ Patterning process
 Patterning process uniformity @30nm
. Target : 6 Unif. ~ 10%
 Need to increase MR ratio
: > 1000% Reading margin issues
Roff. max
Ron. max
R
 Assumption) Pattern Unif.(6)=10%, MTJ= 30x30㎚2, RA=20 Ω-㎛2 , Jc=2MA/cm2
MR(@0.3V)
Ron. max
Roff. max
Δi (㎂)
R/ 
100%
27.4
36.8
1.2
20
150%
27.4
46.0
2.3
25
200%
27.4
55.0
2.8
29
1000%
27.4
202.0
4.7
45
We need Strategies for Better Reading Margin
7
Key Issues in STT-MRAM Manufacturing
 MTJ Patterning Process
. Dry Etch (down to sub 30nm size)
. Corrosion Free Etch Process
. Damage Free Etch Process
M3
VIA2
M2
 Switching Voltage Distribution
. Etch damage control
. Thermal stability
VIA1
M1
 Low Temperature Process
MTJ
. Process margin < 350℃
BE
BEC
 Evaluation of MgO reliability
 Channel Engineering
. Fin-FET structure
P-Well (NMOS)
Core & Peri
Cell Array
8
Summary
 Key Parameters for STT-MRAM Development
1. Reliability of MgO Tunnel Oxide
- Low RA & High BV
- Reliability on High Jc
2. Writing current
- MTJ : Low Jc & switching voltage distribution
- High performance Tr : Fin-FET
3. Reading margin @ sub 30nm
- MTJ pattern uniformity
- Low RA & high Jc
4. Thermal stability : SAF FL, Perpendicular MTJ
 Key Issues in STT-MRAM Manufacturing
1. MTJ patterning technology : Corrosion/damage free
2. Switching voltage distribution
3. Process temperature margin
4. Evaluation of MgO reliability
9