Transcript No Slide Title

COPING WITH
INTERCONNECT
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Impact of Interconnect Parasitics
• Reduce Reliability
• Affect Performance
Classes of Parasitics
• Capacitive
• Resistive
• Inductive
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Nature of Interconnect
Local Interconnect
Global Interconnect
SLocal = STechnology
SGlobal = SDie
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
INTERCONNECT
Dealing with Capacitance
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Capacitance: The Parallel Plate Model
L
W
H
tox
SiO2
Substrate
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Typical Wiring Capacitance Values
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Fringing Capacitance
(a)
H
W - H/2
+
(b)
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Fringing Capacitance: Values
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
How to counter Clock Skew?
(from [Bakoglu89])
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Interwire Capacitance
Level2
Insulator
Level1
SiO2
Substrate
Creates Cross-talk
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Interwire Capacitance
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Impact of Interwire Capacitance
(from [Bakoglu89])
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Capacitance Crosstalk
VDD

CXY
X
CX
In1
Y
PDN
In2
5V
In3
OV

5x5 m Overlap: 0.35 V Interference
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
How to Battle Capacitive Crosstalk
• Avoid parallel wires
• Shielding
Shielding
wire
GND
VDD
Shielding
layer
GND
Substrate (GND)
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Driving Large Capacitances
tpHL = CL Vswing/2
Iav
VDD
Vin
Vout
CL
Digital Integrated Circuits
Interconnect
Transistor
Sizing
© Prentice Hall 1995
Using Cascaded Buffers
In
Out
Ci
u2
u
1
C1
u N-1
C2
CL
uopt = e
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
tp in function of u and x
u/ln(u)
60.0
40.0
x=10,000
x=1000
20.0
x=100
x=10
0.0
1.0
3.0
5.0
7.0
u
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Impact of Cascading Buffers
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Output Driver Design
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
How to Design Large Transistors
D(rain)
S
Multiple
Contacts
D
G
S(ource)
S
G(ate)
(a) small transistors in parallel
Digital Integrated Circuits
Interconnect
(b) circular transistors
© Prentice Hall 1995
Bonding Pad Design
Bonding Pad
GND
100 m
Out
VDD
Digital Integrated Circuits
In
GND
Interconnect
Out
© Prentice Hall 1995
Reducing the swing
tpHL = CL Vswing/2
Iav
• Reducing
the swing potentially yields linear
reduction in delay
• Also results in reduction in power dissipation
• Requires use of “sense amplifier” to restore signal level
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
INTERCONNECT
Dealing with Resistance
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Wire Resistance
R= L
HW
Sheet Resistance
Ro
L
H
R1
W
Digital Integrated Circuits
Interconnect
R2
© Prentice Hall 1995
Interconnect Resistance
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Dealing with Resistance
• Selective Technology Scaling
• Use Better Interconnect Materials
e.g. silicides, bypasses
• More Interconnect Layers
reduce average wire-length
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Polycide Gate Mosfet
Silicide
PolySilicon
SiO 2
n+
n+
p
Silicides: WSi2, TiSi 2, PtSi2 and TaSi
Conductivity: 8-10 times better than Poly
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Modern Interconnect
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
RI Introduced Noise
I
VDD
R’
pr e
VDD - V’
X
I
V
V
R
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Power and Ground Distribution
GND
VDD
Logic
Logic
VDD
VDD
GND
GND
(a) Finger-shaped network
Digital Integrated Circuits
(b) Network with multiple supply pins
Interconnect
© Prentice Hall 1995
Electromigration (1)
Limits dc-current to 1 mA/m
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Electromigration (2)
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
RC-Delay
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
RC-Models
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Reducing RC-delay
Repeater
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
The Ellmore Delay
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Penfield-Rubinstein-Horowitz
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
INTERCONNECT
Dealing with Inductance
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Inductive Effects in Integrated
Circuits
Coaxial
Cable
Digital Integrated Circuits
Triplate
Strip Line
MicroStrip
Interconnect
Wire above
Ground Plane
© Prentice Hall 1995
L di/dt
V DD
L
Vin
i(t)
Vout
CL
L
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
L di/dt: Simulation
5.0
vout
4.0
5V
Vout(V)
t
3.0
tfall = 4 nsec
2.0
tfall = 0.5 nsec
1.0
0.0
40mA
20mA
t
20
IL (mA)
iL
10
0
0.5
vL
t
VL (V)
0.2V
0.3
0.1
-0.1
-0.3
2
4
6
t (nsec)
8
10
Signals Waveforms for Output Driver connected To Bonding Pads
(a) vout; (b) i L and (c) v L.
The Results of an Actual Simulation are Shown on the Right Side.
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Choosing the Right Pin
Bonding Wire
Chip
L
Mounting
Cavity
L’
Lead Frame
Pin
Make Rise- and Fall Times as slow as possible
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Decoupling Capacitors
Bonding
Wire
Board
+
Wiring
SUPPLY
Cd
CHIP
Decoupling
Capacitor
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Packaging
Requirements
• Electrical: Low parasitics
• Mechanical: Reliable and Robust
• Thermal: Efficient Heat Removal
• Economical: Cheap
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Bonding Techniques
Wire Bonding
Substrate
Die
Pad
Lead Frame
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Tape-Automated Bonding (TAB)
Sprocket
hole
Film + Pattern
Solder Bump
Die
Test
pads
Lead
frame
Substrate
(b) Die attachment using solder bumps.
Polymer film
(a) Polymer Tape with imprinted
wiring pattern.
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Flip-Chip Bonding
Die
Solder bumps
Interconnect
layers
Substrate
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Package-to-Board Interconnect
(a) Through-Hole Mounting
Digital Integrated Circuits
(b) Surface Mount
Interconnect
© Prentice Hall 1995
Package Types
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Package Parameters
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995
Multi-Chip Modules
Digital Integrated Circuits
Interconnect
© Prentice Hall 1995