Transcript Slide 1

et438b-3/pptx
LECTURE NOTES PART 3
1
ET 438 b Digital Control and Data Acquisition
Digital-to-Analog Conversion
Digital-to-Analog Converter (DAC) Transfer Function
Infinite
resolution
line
FS
Analog Output Signal
(3/4)FS
(5/8)FS
(1/2)FS
DAC produces discrete voltage
values for each digital code
Maximum
Voltage Output,
Vomax
(3/8)FS
(1/4)FS
resolution  VLSB 
(1/8)FS
0
000 001 010 011 100 101 110 111
Digital Input Code
2
Vo max
2 n 1
Max output approaches
FS as n goes to infinity
Full scale
Digital
Code
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(7/8)FS
TYPE OF DIGITAL-TO-ANALOG CONVERTERS
Binary-Weighted Resistor DAC
LSB
In
I A  I1  I 2  I3.... I n
I1 
B(n-3)
B(n-2)
IF
I3
I2
B(n-1)
IA
R
V
V
V
V
, I2 
, I3 
, ... I n  n 1
R
2R
4R
(2 )R
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B0
Rules of Ideal OP AMPs Iin = 0,
Zin = infinity
Summing amplifier
with digitally
controlled inputs
 V 
V
 V 
 V 
I A  B(n  1)     B(n  2)  
  B(n  3)  
 ...  B0   n 1 
R
 2R 
 4R 
 (2 )R 
Formula for output V
V0   I F  R F
I1
MSB
Iin
B0, B(n-3), B(n-2), ....B(n-1) take on
values of 1 or 0 depending of the
digital output controlling switch
V0   R F i 1
n
B( n  i)  V
2 i 1 R
3
BINARY WEIGHTED DAC EXAMPLE
Example: For the binary-weighted resistor DAC below find the
output when the input word is 11012 V = 10 Vdc, Rf = R
n
B(n  i)  V
2i 1 R
n=4
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V0   R F i 1
B(4-1)=B3=1 MSB
B(4-2)=B2=1
B(4-3)=B1=0
B(4-4)=B0=1 LSB
B3
B=11012
B2
Since Rf = R
B1
B0
 B3  V B2  V B1 V B0  V 
Vo  R   11  21  31  41 
2 R 2 R 2 R 2 R
R 1 V 1 V 0  V 1 V 
Vo     0  1  2  3 
R  2
2
2
2 
110 110 0 10 110
Vo  1  0  1  2  3 
2
2
2 
 2
10
10

Vo  10   0    10  5  1.25  16.25
2
8

4
R-2R BINARY LADDER DAC
R-2R Ladder produces binary weighted current values from only 2
resistance values.
Vref = 10 Vdc
Req3
Req2
Req1
Virtual
Ground
Circuit Analysis
Currents through each 2R
value resistor directed to OP
AMP or ground by digital
switch
Find Req3 by assuming
all switches are closed to
ground
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R= 10k
2R = 20k
R eq1  20 k 20 k  10 k  20 k
R eq2  R eq1
20 k  10 k  20 k
R eq3  R eq2
20 k  10 k
R eq3  10 k
Network equivalent resistance is R
5
R-2R LADDER ANALYSIS (CONTINUED)
V=10 Vdc
Iin
R4
R2
10k
V1
I1
I
20k
I2
10k
I’
20k I3
Find Iin from Req3 and V
V3
R5
20k
20k
R6
R3
Iin 
V
10 V

 1.0 mA
R eq3 10 k
I4
V1 10 V

 0.5 mA I  Iin  I1  1 mA - 0.5 mA  0.5 mA
R1 20 k
I1 
V2  V1  I  R 2  V2  10  0.5 mA 10 k  10  5  5 V
I2 
V2
5V

 0.25 mA I'  I1  I 2  0.5 mA - 0.25mA  0.25mA
R 3 20 k
V3  V2  I'R 4  V3  5  0.25 mA 10 k  5  2.5  2.5 V
I3 
V3 2.5 V
V
2.5 V

 0.125mA I 4  3 
 0.125mA
R 5 20 k
R 6 20 k
Current Values
I1 = 0.5 mA MSB
I2 = 0.25 mA
I3 = 0.125 mA LSB
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R1
V2
Current values directed
to OP AMP summing
junction or ground. At
summing junction:
Vo =-Rf∙IT
6
Find the output voltage for the R-2R DAC shown below. The digital input is
1102. R=15k, 2R=30k and Rf=15k , Vref=5 Vdc
I2
I1
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R-2R EXAMPLE
Find currents I0, I1, I2 and
use formula V0 = - ITRf
I0
Req
IT
All other currents reduced by
factor of 2.
7
COMMERCIAL DACS: DAC0800 FAMILY
Devices used in practical designs use integrated R-2R networks
and transistor switching. They have TTL compatible inputs.
Iref 
Iref
4
Vref
Rref
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Design Equations
 D 
I0  Iref 

 256 
14
2
D = decimal
equivalent of
binary input
8-bit binary code converted to 256 levels
of I0. Full scale value set by reference
current. 1 bit change produces change of
1/256 in I0
Ifs 
Vref
Rref
 255 


 256 
Full scale
output
8
DAC0800 EXAMPLE
Use OP AMP to convert current to voltage. The reference voltage is
+10 V dc and the reference resistance is 5k. The value of Rf = 2.5k
Io
Vref 10 V

 2.0 mA
R ref 5 k
a.) convert binary
to decimal
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I ref 
11012  23 (1)  22 (1)  21 (0)  20 (1)
a.) Digital input 000011012
b.) Digital input 100011012
11012  8  4  1  13
D  13
Find I0
 13 
I0  (2.0 mA)
 0.1015625mA  101.5625A

256


 D 
I0  Iref 

 256 
Io enters so negative
V0  (I0 )  R f  (0.1015625mA)(2.5k)  0.253906V
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DAC0800 EXAMPLE (CONTINUED)
b.) Digital input 100011012
I ref 
Vref 10 V

 2.0 mA
R ref 5 k
Io
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I0
b.) convert binary to decimal
7
6
5
4
3
2
1
0
10001101
2  2 (1)  2 (0)  2 (0)  2 (0)  2 (1)  2 (1)  2 (0)  2 (1)
11012  128 8  4  1  141
D  141
 D 
 141
I0  I ref 
  (2.0)  
  1.1015626mA
256
256




Io enters so negative
I0  Iref  I0  2.0 1.1015625mA  0.8984375mA
V0  (I0 )  R f  (1.1015625mA)(2.5k)  2.753906V
10
ANALOG-TO-DIGITAL CONVERSION (ADC)
Converting continuous signals to digital values requires
3 steps
2
Hold analog sample while conversion is in
progress
3
Convert analog value to digital value (binary)
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1
Sample analog signal. Nyquist rate or above
Need a minimum of 2x highest frequency
Higher rates ease signal reconstruction
11
TYPES OF ANALOG-TO-DIGITAL CONVERTERS
Integrating
Successive
Approximation
• High Speed
in tracking
mode
• Slow
Conversion
times (Some
Sub-types)
• Noise
Sensitive
• Conversion
time
independent
of input value
• Most
commonly
used in DAQ
applications
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• High
Accuracy
• Low Speed
• Low Cost
• Not
commonly
used in DAQ
Tracking
(Counter Type)
12
TYPES OF ANALOG-TO-DIGITAL CONVERTERS
“Flash” or
Parallel
• One bit
Conversion
• High
Resolution
• Ratio of 1-to0 represent
input
• Uses digital
filtering
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• MultiComparators
• Highest
Speed
• High Cost
Delta/Sigma
13
COUNTER-TYPE ANALOG-TO-DIGITAL
CONVERTER OPERATION
V
Digital output
When V+ = V-
V+
A
+
V
VClock
AND
C
O
U
N
T
E
R
D
A
C
1.) Input a constant value. Requires a sample and hold circuit.
(Not Shown)
2.) AND gate passes clock signal when point A logic high
3.) Counter incremented by signal B
4.) DAC output increases as counter output increases
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-
B
14
COUNTER-TYPE ANALOG-TO-DIGITAL
CONVERTER OPERATION
Digital output
V+
A
+
V
VClock
AND
C
O
U
N
T
E
R
D
A
C
Tracking A/D
converters use
up/down counters
to minimize
conversion times
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-
B
Input V
5.) Counter stops when DAC V exceeds input V
Input
Value
DAC Output
Value
Time
Conversion time
depends on the
input level
15
SUCCESSIVE APPROXIMATION ADC
Procedure
1. Set MSB to 1
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Counter A/D converters conversion time proportional
to the input level. Improve conversion speed using a
binary search technique.
2. Test input, Vin, against DAC output, VDAC
3. If VDAC > Vin, reset bit to 0, else bit = 1 (VDAC < Vin)
4. Move to next bit and repeat steps 1 - 3
The input is converted to digital value in n steps, where n =
the number of bits in digital representation
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SUCCESSIVE APPROXIMATION ADCS
Successive Approx.
Register
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17
SUCCESSIVE APPROXIMATION ADC
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Example: An 8-bit successive approximation ADC has an input
voltage of 13.478 V. The ADC full scale input voltage is 20 V. Use
the successive approximation algorithm given previously to
determine the binary value. Assuming that each bit test takes a
single clock cycle, determine the maximum conversion time for the
ADC if it is clocked at 4.77 MHz.
18
Example Solution
19
Voltage
Weight
10.0
5.0
2.5
1.25
Bit
D7
D6 D5 D4
0.625
0.3125
0.15625
0.078125
D3
D2
D1
D0
Cycle
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
3
Set D4
1
0
1
0
0
0
0
0
4
Set D3
1
0
1
0
0
0
0
0
5
Set D2
Set D1
1
0
1
0
1
0
0
0
6
1
0
1
0
1
1
0
0
7
Set D0
1
0
1
0
1
1
0
0
8
1
1
1
1
1
1
1
1
0
0
Set D6
Set D5
1
2
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0
0
1
0
0
0
Set D7
1. 10<13.478 bit remains set
5. 10+2.5+0.625<13.478 bit remains set
2. 10+5>13.478 reset bit
6. 10+2.5+0.625+0.3125<13.478 bit remains set
3. 10+2.5<13.478 bit remains set
7. 10+2.5+0.625+0.3125+.15625>13.478 bit reset
4. 10+2.5+1.25>13.478 reset bit
8. 10+2.5+0.625+0.3125++0.078125>13.478
bit reset
Example Solution (Continued)
Summary Results
Final binary value: B=101011002
Determine conversion time
Define Tc as clock period = 1/fc
Tc 
Where fc = ADC Clock = 4.77 MHz
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Final voltage: 10+2.5+0.625+0.3125 = 13.4375 V
Quantization Error voltage: VQE=13.478 V-13.4375 V = 0.0405 V
or 40.5 mV
1
1
7


2
.
096

10
S  0.2096 S
6
f c 4.7710 Hz
All conversions take 8 clock cycles so maximum conversion time is 8∙Tc
Tcon = 8∙Tc = 8 ∙(0.2096 S) = 1.667 S Ans
20
Example Solution (Continued)
What is the highest frequency that the system can convert without
folding or aliasing. Assume that the sample and hold time is zero.
Define the maximum conversion rate frequency, fcon(max)
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f con (max) 
1
1

 596,250 Hz
Tcon 1.677106 S
Signals must be sampled at least twice per period (Nyquist rate)
2  f in  f con (max)
f in 
f con (max)
2

596,250 Hz
 298,125Hz
2
Ans
21
DIGITAL INPUT & OUTPUT SIGNALS
Digital input and output control and monitor external devices that have
only on/off levels
Boolean Logic form basis of numbering system and computer structure.
Boolean Logic Symbol
State
1
logic high
0
logic low
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Boolean Logic
Logical Groupings
Individual bits: 1 and 0’s
Groups of bits: 8-bits = byte
16-bits = 2 bytes = 1 word
All collections of bits are powers of 2
22
DIGITAL INPUT & OUTPUT SIGNALS
Addressing bits in a byte
6
5
4
3
2
1
0
1
1
0
0
0
1
1
0
Bit 7 = 1 Bit 5 = 0
Bit 6 = 1 Bit 4 = 0
Address location
Bit
Bit 3 = 0 Bit 1 = 1
Bit 2 = 1 Bit 0 = 0
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7
Weighted number system - conversion from binary to decimal
n = 1∙27+1∙26+0∙25+0∙24+0∙23+1∙22+1∙21+0∙20
n = 1 ∙ 128+1 ∙ 64+1 ∙ 4+1 ∙ 2 = 198
198 decimal equivalent of binary number
23
DIGITAL HARDWARE STANDARDS
Digital standards specify voltage levels of logic highs and logic
lows, current output and input levels. Makes chips from same
family compatible with each other
Transistor-Transistor Logic (TTL) 7400 74LS00 series devices
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Logic Standards
Nominal 5 V dc logic high and 0 V dc logic low
TTL chip I/O pin electrical characteristics
Source current: 400 A
Sink current: 1.6 mA (1 unit load)
Logic 1 threshold voltage : V≥2.4 V dc
Logic 0 threshold voltage V≤0.8 V dc
24
DIGITAL HARDWARE STANDARDS- SOURCE
AND SINK CURRENTS
What is sourcing and sinking of device currents?
Switch source of current
+5 V dc
Switch sink of current
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Determined by position of voltage source, the switching
device, and the load.
+5 V dc
I
Load
Load
I
Switch connects
voltage to load
Switch connects
load to ground
25
DIGITAL HARDWARE STANDARDS- SOURCE
AND SINK CURRENTS
Simple transistor sink and source representations
Vcc = + 5 Vdc
I
Switch model of gate
Vcc = + 5 V dc
ILL
RL
Rb
Vin
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IL
IL flows to
ground when
Vin = logic 1
IL
RL
Vo
Vin=5 V
Vo= 0 V
Vin = 5 V
Vin = 5 V for logic high and
0 V for logic low
5V
0V
When Vin = 5 Vdc Vo = 0 V
When Vin = 0 Vdc Vo = 5 V
Load will draw
current when
Vin = 5 V dc. Switch
(Transistor) must
sink load current
26
SOURCE AND SINK CURRENTS
Switch model of gate - current sourcing
Vcc = + 5 V dc
Circuit with transistor showing
current sourcing
IL
Load
Load
ILL
Vin
When Vin is 5 V load is de-activated
(switch closed)
When Vin is 0 V load draws current
from source
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Vin
Vo
ILL
Transistor Logic Inverter
27
SOURCE AND SINK CURRENTS
TTL Inverter symbol
TTL Inverters Sinking Current
Load
+5 Vdc
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ILL
Sourcing
current
R
D0
D1
D2
Output
Port
D3
D4
D5
D6
D7
Resistors used to limit current through gate.
TTL buffer limit:16 mA (10 unit loads)
28
DIGITAL INTERFACES
For high current output use discrete transistor or relay
(electromechanical or solid state)
+5 Vdc
AC
AC
TRIAC
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Solid State Relay
Electrical Isolation : 7500 V
LED Input: 3-30 Vdc
Ground
LED
Devices integrated on the same
chip. LED light output triggers
TRIAC that passes ac current.
Does not electrically disconnect
load from source – beware of
leakage currents
29
DIGITAL INTERFACES
Typical Application – Ac Motor starting
Motor Load
1/4 HP 120 Vac
+5 V dc
M
Grd
+5 V dc
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120 V
Vo = 0 V (grd), motor is on
Vo = 5 V motor is off
Output
Voltage
Vo
Input Voltage
From Port
Port output is inverse of solid-state
relay input
30
DIGITAL INTERFACES
Electromechanical Relays
+ 12 Vdc
Typical
To output
bit
Rb
Resistor, Rb
sized to allow
TTL level to
turn
on relay
+ 12 Vdc
Typical
To high current
load AC or DC
NPN
transistor
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Diode
voltage
spike
protector
Relay coil dc
resistance
transistor
load
To high power
loads AC or DC
LS7406 chip
Current limited
by the TTL
chip
Relay interface using open collector TTL inverter
31
DIGITAL INPUT INTERFACES
Interface should limit currents and voltage levels to TTL limits
Mechanical switch interfacing
+ 5 Vdc
5/2.2k=2.3 mA
2.2 k
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Size resistor to
limit current
below sink
limit
+ 5 Vdc
To
DAQ bus
Mechanical
switch
De-bounce
switch
Digital interface for digital port.
Switches momentary contact or toggle
32
DIGITAL INTERFACE: NON-TTL LEVELS
Use Optocoupler to isolate high voltages from TTL levels
+24 V dc
+ 5 Vdc
R
To TTL
input
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2.2 k
Typical
Switch closed - LED de-energized
Switch open - LED energized
TTL inverter
gate (7404 or 7414)
Transistor off - inverter input +5 Vdc output 0 V
Transistor on - inverter input 0 Vdc output 5 V
Optocouipler
Optocoupler – Integrated
LED and optical transistor
Energizing LED causes optical
transistor to conduct
33
INTERFACE EXAMPLE
+24 Vdc
+ 5 Vdc
2.2k
2.2k
R = 100
4N35
If
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Determine the logic levels and currents in the digital
interface circuit shown below. Assume that the optocoupler
diode has an on-state voltage drop of 1.4 V and the optical
transistor has an on-state collector-to-emitter drop of 0.4
V.
Ic
7404
To TTL
input
Logic
open switch = 0 = 0 V
close switch = 1 = 5 V
34
INTERFACE EXAMPLE SOLUTION
Device Specification 4N35
If = continuous forward current: 60 mA
Ic = continuous collector current: 150 mA
Source voltage isolation: 7500 V peak
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+24 Vdc
Compute If with switch open to see if it exceeds
the continuous rating
Write KVL around loop
-24 +(2.2k)(If) +100(If) +1.4 =0
2.2k
R = 100
2300 I f  24  1.4
If
+
-
VD =1.4 V
If 
24  1.4
 0.00983A  9.83mA
2300
Current is within specifications
35
INTERFACE EXAMPLE SOLUTION (CONTINUED)
With switch closed, LED is shorted out so If=0. Switch must be
open for optical transistor to conduct
+5 V
IL
IC
2.2k
IIL
+
Vce=0.4 V
-
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7404 Specifications
IOH = maximum source current from output: 400 A
IOL = maximum sink current into output: 16 mA
IIL = current flowing out of input when logic low V
level (0.4 V) is applied: 1.6 mA (1 unit load)
Assume optical transistor is in saturation
Find Ic and determine if it is below 150 mA
IC = IL + IIL
Find IL from KVL around collector-emitter loop
 5  (2.2k )(I L )  0.4  0
5  0.4
 2.1mA
2.2k
I C  2.1 mA  1.6 mA  3.7 mA
IL 
Below maximum
36
37
INTERFACE EXAMPLE SOLUTION (CONTINUED)
Determine the interface logic.
When optocoupler transistor conducts, the 7404 input is logic low, therefore the
inverter output is high. See table below
+24 Vdc
R = 100
Ic
2.2k
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2.2k
+ 5 Vdc
7404
4N35
If
To TTL
input
Switch
LED
Position
Transistor
7404
Input
7404
Output
open
on
on
Low
(0.4 V)
High
(4.6)
closed
off
off
High
(5 V)
Low
(0.4 V)
ELECTROMECHANICAL RELAY EXAMPLE
Size Rb such that Q1 will activate with a TTL input
+24Vdc
10 mH
Relay
coil
model
500 
Vs
Ib
+
Rb
+
Vbe
Q1
-
-
Vce
Transistor Parameters, Q1
(2N3904)
hFE = 200 (nominal)
Vce(sat) = 0.2 V
Vbe(sat) = 0.8 V
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Ic
Assume transistor is in saturation and
compute the value of Ic
Write a KVL equation around the
collector-emitter circuit
-24 +500(Ic)+VCE(sat) =0
-24+500(Ic)+0.2 =0
500I c  24  0.2
Ic 
24  0.2
 47.6 mA
500
38
ELECTROMECHANICAL RELAY EXAMPLE
(CONTINUED)
Relate the collector current, Ic, to the base current Ib using the dc
gain, hFE.
Ic
+24Vdc
Relay
coil
model
500 
Vs
Ib
+
Rb
+
Vbe
Q1
-
-
Vce
h FE 
Ic
 200
Ib
Dc gain drops in saturation. Use hFE/10
to account for this phenomena
et438b-3/pptx
10 mH
The parameter, hFE also known as b is:
h FE 200 I c


10
10 I b
Ic
20 
Ib
I c 47.6 mA
 Ib 

 2.38 mA
20
20
I b  2.38 mA
39
ELECTROMECHANICAL RELAY EXAMPLE
(CONTINUED)
Find value of Rb from a KVL equation around the base-emitter circuit
+24Vdc
10 mH
Relay
coil
model
500 
Vs
Ib
-Vs +Ib(Rb) +Vbe(sat) =0
4.8 V  0.8 V
Rb 
 1.68 k
2.38 mA
Ans
+
Rb
+
Vbe
Assume a TTL high level of 4.8 V
Remember Vbe(sat)=0.8 V
et438b-3/pptx
Ic
Q1
-
-
Vce
Note: this value is above the maximum
TTL source current of 400 A.
Drive Q1 from open-collector invertor
40
ELECTROMECHANICAL RELAY EXAMPLE
(CONTINUED)
Inductive voltage protection using freewheeling diodes
+24Vdc
+
10 mH
Cuting-off Q1 reduces Ic to zero
Coil voltage changes polarity due to
induction
Collapsing magnetic field
Relay
Coil model produces I
Vcoil
I
Rb
2N3904
Q1
et438b-3/pptx
Freewheeling
diode
500 
Diode D1 provides a path for
the current induced when
the transistor is switched off.
It also clamps the induced
voltage to the forward drop of
the diode. (0.7 V)
41
42
SIMULATION RESULTS-LTSPICE
Simulation without diode
Circuit simulated
et438b-3/pptx
Ic
I(L1)
50mA
40mA
30mA
20mA
10mA
0mA
-10mA
V(n001)
1.0KV
0.5KV
-0.1KV
0.0s
0.1s
0.2s
0.3s
0.4s
0.5s
0.6s
0.7s
0.8s
0.9s
Vce
1.0s
SIMULATION RESULTS-LTSPICE
Simulation with diode
et438b-3/pptx
Ic
I(L1)
50mA
Vce
23mA
-5mA
V(n001)
26V
13V
0V
0.0s
0.1s
0.2s
0.3s
0.4s
0.5s
0.6s
0.7s
0.8s
0.9s
1.0s
43
SOFTWARE CONTROL OF DIGITAL I/O
Individual bit of an output byte can be toggled by the
application of a binary mask number and the
appropriate bit-wise logic function.
et438b-3/pptx
These functions include: OR, AND, XOR
Procedure:
1.
2.
3.
4.
5.
)
)
)
)
)
Identify present port binary pattern
Determine desired port binary pattern
Select appropriate bitwise operator
Determine correct mask value
Apply bitwise operator to present pattern and mask to create
desired pattern.
44
SOFTWARE CONTROL EXAMPLE
Example: An 8 bit digital output port drives a group of 8
LEDs through TTL inverters.
et438b-3/pptx
Determine the binary
byte value that will cause
LEDs 0, 3, 5, 6 to light.
Convert this byte to a
decimal value.
45
SOFTWARE CONTROL EXAMPLE SOLUTION
+5 V dc
Answer
I
+5 V
Bit
0V
7
0
et438b-3/pptx
Port
To light the LEDs, port outputs
must be Logic 1 (5 Vdc) input to
the inverting buffer. This causes
the inverter output to go to a logic
0 (0 V dc) sinking current through
the inverter.
0
1
1
0
1
0
0
1
Convert to decimal
1 ∙ 26 + 1 ∙ 25 + 1 ∙ 23 + 1 ∙ 20 = 64 + 32 + 8 +1 = 105
46
SOFTWARE CONTROL EXAMPLE SOLUTION
Determine the binary mask value and logic function
that will toggle off LED 5 yet leave the other LEDs in
their original state.
0
5
1
0
0
1
0
0
1
Answer
et438b-3/pptx
New byte value
Use AND function and a mask value that has a logic low bit in bit location 5.
5
AND
0
1
1
0
1
0
0
1
original
0
1
0
0
1
0
0
1
mask
0
1
0
0
1
0
0
1
desired
47
SOFTWARE CONTROL EXAMPLE SOLUTION
Determine the decimal value of the mask value from above.
Mask 01001001 = 1∙26 + 1∙23 + 1 = 73
Answer
2
7
0
1
0
0
1
1
1
1
et438b-3/pptx
Now use a mask value and a logic function to turn on
LEDs 1 and 2 while leaving the others unchanged.
0
1
Desired byte value
Use the OR function and set the bits in positions 1 and 2 in the
mask to the high position. Make all the other bit values 0 to
complete the mask.
48
SOFTWARE CONTROL EXAMPLE SOLUTION
Toggle bits 1 and 2
1
0
0
0
1
0
0
0
1
0
1
0
0
1
original
0
0
1
1
0
mask
0
1
1
1
1
desired
et438b-3/pptx
OR
0
2
Set these
bits high
XOR function could also be used to toggle bits if a
different mask value is used. Use the XOR function
to turn all LEDs off.
49
SOFTWARE CONTROL EXAMPLE SOLUTION
Y  AB
Review of XOR logic
B
Y
0
0
0
0
1
1
1
0
1
1
1
0
Like bits produce logic 0
Unlike bits produce logic 1
et438b-3/pptx
A
Answer
Copy the original byte value and use it as the mask value.
Using the XOR bit-wise logic function will set all bits low.
Desired byte value
7
0
0
0
0
0
0
0
0
0
50
SOFTWARE CONTROL EXAMPLE SOLUTION
XOR Mask Result
7
0
1
0
1
0
0
0
0
0
0
1
1
1
1
original
0
1
1
1
1
mask
0
0
0
0
0
desired
et438b-3/pptx
XOR
0
Example Summary
1.) AND Function with 0 bit in mask resets output bit
2.) OR Function with 1 bit in mask sets output bit
3.) XOR Function with opposite bit value from original set output bit
XOR with same value as original value resets output bit
51