Transcript Empirical Modeling of Microwave Devices

Microtechnology and Nanoscience, MC2
Power amplifier efficiency
enhancement techniques
Christian Fager
Microwave Electronics Laboratory
Department of Microtechnology and Nanoscience, MC2
Chalmers University of Technology
2006-10-16
Microtechnology and Nanoscience, MC2
Outline
• Background
– Why is high efficiency important?
• Switched mode power amplifiers
– Why are SMPAs more efficient than traditional PAs?
• Device technologies
– Which devices are used to realize SMPAs?
• Transmitter architectures
– How can SMPAs be used to transmit modulated signals at high
efficiency?
• Summary
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Background
• Why high efficiency is important
– Increased power consumption
Battery cost
Heavier power supplies
Electrical power expenses
Environmental incentive
– Further multiplied by need
for extra cooling
– Deterioration of semiconductor
reliability
Constant 1 W output power
10
8
Power loss [W]
•
•
•
•
6
4
2
0
0
20
40
60
Efficiency [%]
80
100
• Example: Radio base stations
– Total energy consumed by base stations in Sweden: 1.2 - 2.1 TWh/yr
– Energi from of a Barsebäck size nuclear reactor: 4 TWh/yr...
• The final power amplifier handles the highest power levels
and dominates the total power consumption
– Power amplifier efficiency enhancement is very important!
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Dynamic input signal variations
• 3G base station: Transmitted WCDMA signal
Frequency domain
Time domain (sample)
40
40
RF signal power
RF signal power
20
0
-20
-40
-60
2125
2130
2135
2140
2145
Frequency [MHz]
2150
2155
30
20
10
0
50
51
52
53
Time [µs]
54
55
• The modulation creates dynamic signal power variations
10
Probability [%]
8
6
Peak power: 40.3 dBm
4
Average power: 30.0 dBm
2
Peak-to-average: 10.3 dB
0
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0
10
20
30
Output power [dBm]
40
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Traditional linear PA operation
• The peak output power is determined by its saturation
Pout [dBm], PAE [%], Prob. [%]
– PA efficiency is maximum close to saturation
– Operating it into compression results in severe distortion
30
Pout
PAE
Prob.
25
20
15
10
5
0
-25
-20
-15
-10
-5
Input power [dBm]
0
5
• The total PA efficiency is weighted by the signal input
power probability density function
– For this case: Peak PAE = 27%, total average PAE = 15%
• How can more efficient PAs be realized???
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Switched mode power amplifiers
Why are SMPAs more efficient than traditional PAs?
Microtechnology and Nanoscience, MC2
Traditional power amplifiers
• Transistor is used as variable current source
Measured vs. modelled Ids(Vds)
60
0.20
Voltage
Current
Dissipated power
50
0.15
40
Ids
Loadline
30
0.10
20
0.05
10
0
0.00
0
5
10
15
20
25
30
0
0.2
Vds
0.4
0.6
0.8
1
Time
• Typically biased in class AB operation, where linearity
and efficiency trade-off is most favorable
• Simultaneous voltage and current
– Dissipation across the device
– Limits practical efficiency to < 50%
• How can the voltage×current overlap be minimized?
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Switched mode power amplifiers (SMPA)
• Designed to use the transistor as a switch, rather than a
controlled current source as in a linear amplifier
– Example: Class E
Intrinsic load line
Intrinsic waveforms
0.4
100
80
10*Idsi1*Vdsi1
200*Idsi1
Vdsi1
Ids
0.3
Loadline
0.2
0.1
60
40
20
0
0.0
-20
0
20
40
60
Vds
80
95
0
100
200
300
400
500
600
700
time, psec
• The output network creates non-overlapping waveforms
• Dissipated power is low
– High efficiency is enabled
– Design of the device load network is very critical
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SMPA input power dependence
• High input power is required to make the transistor
switch properly
– At low power, SMPAs work like poorly designed traditional PA
– Low efficiency, high nonlinearity
Intrinsic load line
0.4
Draineff
Pin 15
0.2
Pin 10
0.1
Pin 5
0.0
18
80
16
60
14
40
12
20
10
8
0
0
20
40
60
Vds
80
95
Gain [dB]
Ids
0.3
100
0
5
10
15
20
25
Input power [dBm]
• Output power should not be modulated with the SMPA
input power
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General SMPA switching conditions
• Consider two simplified switch models (i.e. transistors)
A
B
PC , L oss 
1
2
 C Vc  f
2
PL , L oss 
1
2
 L  IL  f
2
• Most transistors are best described by model A
• Minimzation of losses at RF requires:
– Vc = 0 when switch closes at t = 0
• Zero voltage switching condition (ZVS)
– Even better: dVc/dt = 0
• Many ZVS SMPA classes have been presented...
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Class E
• Presented (patented by Sokal) in 1975
100
200*Idsi1
Vdsi1
80
60
40
20
0
0
100
200
300
400
500
600
700
time, psec
• Load network derived to provide ZVS and dVds/dt = 0
• Cds of active device may be considered part of C1
• Maximum frequency:
f m ax 
Pout
 C dsV dd
2
• Peak voltage: 3.6×Vdd
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Class F and inverse F (class F-1)
• Square-wave shaping of voltage or current waveforms
by termination of harmonics (ZVS)
Basic class F circuit
• Class F-1: Voltage and current waveforms interchanged
– Zn = {R for n = 1; ∞ for even n; 0 for odd n}
• Maximum frequency limited by the device parasitics
– Higher harmonics are "short circuited" inside the device
– Practically max 5 harmonics need to be considered
– Limits maximum efficiency to ~80%
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Class D / D-1
• Push-pull connection of two class F (F-1) PAs
– Balanced structure provides the loading conditions needed
– No need for harmonic filters
– Baluns are needed to provide balanced input and output for D-1
Class D (voltage mode)
Class D-1 (current mode)
4
4
Voltage, V 1
Current, I 1
3
3
2
2
1
1
0
Voltage, V 1
Current, I 1
0
0
0.2
0.4
0.6
0.8
1
0.2
0.4
0.6
0.8
1
Time
Time
• Difficult to implement at RF
• Cds cannot be absorbed
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0
• Demonstrated to 2 GHz
• More wideband than class F-1
• Twice output power
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Published SMPAs
• LDMOS technology
• f > 800 MHz
• Pout > 7 W
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Year
Class
f (GHz)
η (%)
Pout (W)
Gain (dB)
2002
Inverse-D
1
60
13
14
2003
E
1
73
7.9
10
2003
E/F
0.8
60
30
10
2005
Inverse-F
1
77.8
12.4
12
2005
Inverse-F
1.8
60
13
10
2005
Inverse-D
1.8
63
50
10
2006
E
1
76
8.1
15
2006
Inverse-D
1
71
20
15
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Example: Inverse class D circuit
M.Sc. thesis work by Hossein Nemati, 2006
10.5 cm
8.5 cm
Output balun
Input balun
MRF282
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Transmission
line as inductor
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Measured results
Low efficiency
High efficiency
• High peak efficiency, but only for high input power
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Device technologies
Which devices are used to realize SMPAs?
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Important SMPA device parameters
• Consider again the simplified switch/transistor model
• Important device parameters for SMPAs
– L: Package bond wire parasitics
– Ron: Electron mobility (1/Ids)
– C: Device output capacitance, Cds (Ids)
• Ron×Cds important figure of merit
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Device technologies used
• LDMOS
–
–
–
–
Dominating at f < 3GHz
High power applications
Base station amplifiers
Heating
• Main advantages
– Cheap (Si)
– Mature, reliable
• Competing technologies
– GaAs
– Wide bandgap
• SiC, GaN
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Basic LDMOS device physics
• Cross section of high power LDMOS device*
•
•
•
•
•
Vdbr : ~100 V
Id : ~150 mA/mm
Pout: ~ 1 W/mm
Cds: ~ 0.6 pF/mm
Ron: ~ 20 W·mm
• Drift region/substrate p-n junction reverse biased at Vds > 0
– Cds = depletion capacitance
• p-top inserted to reduce surface field towards gate
(RESURF)
– Increases breakdown voltage
* J. Olsson et al."1 W/mm RF Power Density at 3.2 GHz for a Dual-Layer RESURF LDMOS Transistor", IEEE EDL, Apr. 2002
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Wide bandgap (GaN) device technology
• Cross section of GaN device
•
•
•
•
•
Vdbr > 150 V
Id : >1 A/mm
Pout: > 5 W/mm
Cds: ~ 0.5 pF/mm
Ron: ~ 2 W·mm
• 2d electron gas layer
– High mobility, low on-resistance
• Very high breakdown field
– Very high power density (W/mm)
– Low capacitances for a given output power
– Low switch losses
• Efficiency > 80% reported at 2.14 GHz
– Overdriven class AB operation!
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Wide bandgap prospects
• All major LDMOS manufacturers are starting up GaN
activities
Nitronex GaN PA
• Problems to be solved
– Thermal handling
• Extreme material stress
– Material processing
• Traps
• Reliability
– Packaging
• Thermal matching
• Parasitic capacitances
Chalmers SiC PA
– Price
• Very expensive compared to Si
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Transmitter architectures
How can SMPAs be used to transmit modulated
signals at high efficiency?
Microtechnology and Nanoscience, MC2
• Traditional power amplifiers
– Output power is modulated by
changing the input power level
– High peak-to-average signals
lead to low average efficiency
Pout [dBm], PAE [%], Prob. [%]
Efficient modulation of SMPAs
30
Pout
PAE
Prob.
25
20
15
10
5
0
-25
-20
-15
-10
-5
Input power [dBm]
0
5
• Very high efficiency SMPAs
have been presented
– How shall the high efficiency be maintained for varying signal amplitudes?
• Special transmitter architectures
are considered
–
–
–
–
–
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Supply modulation
Polar architectures
Load modulation
Outphasing architectures
Digital architectures
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Supply modulation: Envelope tracking
• Class AB amplifier example
Measured vs. modelled Ids(Vds)
Measured vs. modelled Ids(Vds)
0.20
0.20
High power loadline
-> OK efficiency
High power loadline
-> OK efficiency
0.15
Ids
Ids
0.15
0.10
0.05
0.10
Reduction of VDS
0.05
Wasted VDS DC power!
0.00
0.00
0
5
10
15
20
25
30
0
5
Vds
Low power loadline
-> Poor efficiency
10
15
20
25
30
Vds
Low power loadline
-> High efficiency maintained
• Envelope tracking means to reduce VDS at low power
levels to avoid unnecessary dc consumption
– The input signal is not changed
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Envelope elimination and restoration (EER)
• Decomposition into separate amplitude and phase
signals
 I  t   jQ  t   e
jw R F t
 A t  e
j f  t   w RF t 
Supply voltage
• A(t): Baseband amplitude
RF input Switched mode
f(t): Baseband phase
RF output
PA
j(
f
(t)+
w
t)
e
: Unity amplitude signal
• Unity amplitude suitable to drive SMPA in saturation
– High efficiency can be maintained
• Amplitude signal can be applied to SMPA supply voltage
to control output power
– Pout  V dd
2
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Supply modulation of Class D-1
• Efficiency > 50% can be maintained for 10dB variation
in output power
– Vds modulated between 10 - 30 V
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EER (and Envelope tracking) properties
• Advantages
– Ideally 100% modulated efficiency
– Power loss is distributed between PA and supply
Envelope signal
• Main problems
– Envelope amplifier (drain DC supply)
requirements
– Time alignment between the supply
and RF paths (EER only)
Supply voltage
RF input
• Envelope signal properties
0
-50
-100
-40
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RF output
80
Envelope signal power
RF signal power
50
Switched mode
PA
-20
0
20
Frequency [MHz]
40
60
Bandwidth: > 30 MHz
Power: > 80% below 10 kHz
40
20
0
-20
-40
0
10
20
Frequency [MHz]
30
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Influence of time alignment mismatch
• Misalignment between amplitude and phase paths
– Leads to severe signal distorton
3
Amplitude
Phase
2
0.5
1.5
0
1
-0.5
0.5
-1
0
0.5
1
Time
1.5
Input signal
Output signal
1
2
-1.5
40
Amplitude
2.5
0
50
1.5
30
20
10
0
0.5
1
1.5
Time
2
2.5
3
0
Frequency
– Alignment requirements in the order of a few nsec.
• Hybrids between EER and ET is normally used
– A lower Vds limit is set
– Low output power is controlled by the input amplitude
– Reduces sensitivity to time alignment
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Envelope amplifier
• High efficiency envelope amplifier is required
–
–
–
–
Bandwidth: > 20 MHz for 5 MHz signal
Voltage range: 5 - 30 V
Current: > 1 A
Efficiency: >>50%
• Linear assisted switched mode amplifier topology
– Slow variations supplied by
switch (high efficiency)
– Fast variations supplied by
linear stage (low efficiency)
– Efficiency >75% published
• Problems
– Complicated circuit
– Limited voltage range
– Limited bandwidth
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Polar architecture heat advantage
[P. Draxler, IMS2006 workshop on memory effects in power amplifiers]
• Distribution of power loss
• Drastic reduction of loss (temperature) in the device
– Improved reliability
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Outphasing architecture
• Signal is splitted in two components with constant
amplitude but with phase difference
– Suitable for driving a SMPA
• Difficult to realize the combiner
– Output impedance of one PA affects the other through the combiner
– Difficult to reuse the power at backoff
– Efficiency at backoff usually not very high
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Load modulation architecture
• Variation of output power by dynamically tuning the
output network
Varactor voltage
Output
matching
network
RF input
Switched mode
PA
RF output
• Varactors typically used
– Breakdown voltage > 100V
– Low series resistance
• Simple and efficient electronics can be used for the control
– No need for high power dc converters etc.
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Schematic of 1 GHz class F-1 PA
• Based on high performance
inverse class-F PA
– LDMOS MRF282
– h = 77.8%
– Pout = 12.4W @ 1GHz
• Modified for the load
modulation technique by
adding a tuneable capacitor in
output network (C2)
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Experimental load modulation results
•
•
•
Straightforward power back-off
(dotted line)
Load modulation (solid line)
Load modulation combined with an
input power tuning (dashed line)
• 20% efficiency improvement when output power is controlled by
variable capacitor
• An output power range of 11 dB is obtained with efficiency over
40% (dashed line)
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Digital architectures
• Convert the RF input signal into a digital pulse-train
– Suitable to drive a switching transistor amplifier (class S)
RF output
RF input
• Very fast transistors are needed to minimize switch losses
– Very high current/capacitance ratio needed (GaN?)
• The class S PA and bandpass filter are already combined in
most SMPAs (e.g. class D)
• Very high digital modulator speed/accuracy is required!
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Digital signal converters
• Pulse width modulation
Carrier PWM
– RF PWM
• Pulse width and position modulation
– Carrier PWM
• Multiplication of PWM and RF signals
– Very high timing accuracy needed
• High clock frequency
• Bandpass D-S modulation
– Quantization noise shaping around center frequency
– Noise floor set by modulator order and clock frequency
Keyzer et al., "Digital generation of RF signals for wireless communications with band-pass delta-sigma modulation". Proc. MTT-S, 2001
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Digital arhitecture future prospects
• CMOS clock frequency roadmap
– Scaling -> microwave digital circuits available
• Reconfigurable PA systems
– The amount of nonlinearity is controlled
by digital parameters
– System can be reconfigured depending on requirements
– Bandwidth vs. distortion can be interchanged dynamically
• Reliability
– No aging or drift
– No need for tuning or tweaking of fabricated circuits
• Integration
– Microwave and digital circuit functions
can be integrated into the same chip
– Especially suited for hand held units
Asbeck et al., "Synergistic design of DSP and power amplifiers for wireless communications", IEEE Trans. MTT, Nov. 2001
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Summary
• SMPAs give higher peak efficiency than traditional PAs
– Load networks designed to prevent current/voltage overlap
– Several classes have been presented
• Recent developments in WBG technology (GaN)
– Very high output power and low capacitances makes it ideally
suited for high efficiency SMPA applications
– Huge industrial interest
• Efficient modulation of SMPAs
– Supply modulation, outphasing, load modulation all promising
– Digital architectures are attractive for the future, but require
extreme clock rates
• How to modulate SMPAs efficiently is still an open
question…
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