Transcript Clocking

Problem 1 – SI block diagram
1
Describe the function of each block of this
typical block diagram of an SI network.
Printed Wiring
Board
package
package
Data generator
Buffers
Data generator: Provides the input voltage source.
Transmit buffers:
Transmit package:
Printed wiring board:
Receive package:
Receiver:
Receiver
Problem 2 – HSPICE pulse
Given this pulse, write the HSPICE program
Data rate
1V
0
Pulse
width
tr
0
tf
period
Answer:
V1 ___ ___ ___ ___ ___ ____
+
___ ___ ___ ____
n+, n-, type, initial V, peak V, delay
rise, fall, pulse width, period
2
Problem 3 – HSPICE circuit
Given this HSPICE program, complete the circuit.
Rin
Edrive
Cout
Rout
Answer:
in
Rin
1G
Vss
in
out1
out1
out1
Vss 1G
Vss VOL=V(in)
Vss Tx_cterm
out Tx_rterm
3
Problem 4 – TL Field Solver
4
Given this partial HSPICE program for a TL Field Solver,
and this cross sectional view of the traces, fill in the CONDUCTOR settings:
(SHAPE=_______, MATERIAL=_________, ORIGIN=___________)
.MATERIAL brd_dielct2 DIELECTRIC ER=3.9 LOSSTANGENT=0.019
.MATERIAL brd_cu2
METAL
CONDUCTIVITY=4.2E+07
.SHAPE brd_trap2 POLYGON
+ VERTEX = ( 0 0 ‘0.5*mil’ ‘0.5*mil’
Answer:
‘4.5*mil’ ‘0.5*mil’ ‘5*mil’ 0 )
.MODEL StripLines
+W MODELTYPE=FieldSolver, LAYERSTACK=brd_sl_stk2 FSoptions=brd_opt2
+CONDUCTOR=(SHAPE=
?
MATERIAL=
?
ORIGIN=(‘
?
’, ‘
+CONDUCTOR=(SHAPE=
?
MATERIAL=
?
ORIGIN=(‘
?
’, ‘
+RLGCfile=StripLines.rlc
.END
y
Origin (of shape)
10.5 mil
-7.5 mil
Origin (of shape)
2.5 mil
10.5 mil
Origin (of coordinate system)
x
?
?
’))
’))
Problem 5 – Call subckt
5
Assign the appropriate node names to the subcircuit figures,
as shown by the call statements, in order to place the
subcircuits into the main circuit.
.SUBCKT PKG in1 in2 out1 out2 Vss
L1 in1 out1 1n
L2 in2 out2 1n
.SUBCKT BRD in1 in2 out1 out2 Vss
Wline1
in1 in2 Vss out1 out2 Vss
XPKG_Tx pkg1_v pkg1_a
+
pkg1_vo pkg1_ao 0
Xboard pkg1_vo pkg1_ao
+
pkg2_vo pkg2_ao 0
______
PKG
______
______
______
Subckt
BRD
Subckt Pkg
______
BRD
______
______
______
Problem 6 – PWL formulation
Locate a, b, c, d, and e on the pwl figure below (tr=tf)
*Bit pattern
.param bit0=1 bit1=0
a
b
c
d
e
Answer:
bit2=1 bit3=0
.SUBCKT Bitpattern data 0
VPWL
data 0 PWL
+
0
+ ‘(tr*bit0)+(1-bit0)*tf’
+
'1*datarate'
+ '1*datarate+(tr*bit1)+(1-bit1)*tf’
+
'2*datarate'
+ '2*datarate+(tr*bit2)+(1-bit2)*tf'
+
'3*datarate'
+ '3*datarate+(tr*bit3)+(1-bit3)*tf'
+
'4*datarate'
+ r TD=0n
bit3
bit0
bit0
bit1
bit1
bit2
bit2
bit3
bit3
1V
0V
a
0 tr
1*dr
2*dr
3*dr
4*dr
6