Transcript Document

An Algorithm for Optimal Decoupling
Capacitor Sizing and Placement for
Standard Cell Layouts
Haihua Su, Sani R. Nassif
IBM ARL
Sachin S. Sapatnekar
ECE Department
University of Minnesota
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Outline
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On-chip decap overview
Modeling and noise analysis
Problem formulation and Adjoint sensitivity analysis
Decap sizing and placement scheme
Experimental results
Conclusion
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On-chip Decoupling Capacitors
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Non-switching gate capacitance
Thin oxide capacitance
C 
w:
h:
tox:
ox:
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 ox
t ox
 w h
width of decap
height of decap
thickness of thin oxide
permittivity of SiO2
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Decoupling Capacitor Models
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1st order model
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2nd order model (non-idealities)
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Power Network Modeling
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Power Grid: resistive mesh
Cells: time-varying current sources
Decaps: 1st order or 2nd order decap model
Package: inductance + ideal constant voltage source
+
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Power Grid Noise Analysis
 Noise metric: shaded area
Vj
+
z(j)
Z = S z(j)
Waveform of node j on VDD grid
Reference: A. R. Conn, R. A. Haring and C. Visweswariah,
Noise Considerations in Circuit Optimization, ICCAD’98
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Formulation - Constrained Nonlinear
Programming Problem
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Minimize Z(wj), j = 1..Ndecap
Subject to Swk  (1-ri)Wchip, i = 1..Nrow
And 0  wj  wmax , j = 1..Ndecap
– ri is the occupancy ratio of row i
Cell
Decap
wj
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Solver – Sequential Quadratic
Programming (SQP)
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QPSOL - Quasi-Newton method to solve the problem
of multidimensional minimization of functions with
derivatives
Requirements
–
–
evaluation of the objective function and constraint functions
calculation of first-order derivatives
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Adjoint Sensitivity Analysis
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Original circuit
Gx(t )  Cx (t )  u(t )
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Vj(t)
+
Adjoint circuit
Gxˆ( )  Cxˆ( )  i( )
x(t) and xˆ ( )
i j(  )
– node voltages, source currents, inductor currents
u(t) – time-dependent sources
i() – current sources applied to all bad nodes
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Adjoint Sensitivity Analysis (cont’d)
 Convolve
to get sensitivities
T
Z
   C (T  t )vC (t )dt
C 0
T
Z
   R (T  t )iR (t )dt
R 0
Z is the noise metric for all the grid = S z(j)
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Adjoint Sensitivity Analysis (cont’d)

Fast convolution for piecewise linear waveforms
~O(N+M)
N linear segments
q
 p (a  bt)'[ g
 k (T  t )]dt
  pq b[ g  k (T  t )]dt
 b(q  p)[ g  kT  k (q  p) / 2]
p
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q
M linear segments
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Sensitivity w.r.t. Decaps
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Adjoint sensitivity w.r.t. Cnear, R and Cfar
Applying chain rule to find the sensitivity w.r.t. decap
width w:
Z
Z Cnear Z R
Z C far

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w Cnear w
R w C far w
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Scheme
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Analyze circuit and store waveforms
Compute Z
Setup current sources for adjoint circuit
Analyze adjoint circuit & store waveforms
Compute Z/Ci and Z/wi
Evaluate constraint function & gradients
Feed to QP solver to get the updated wi
According to the new wi , replace cells and decaps
one by one
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Decap Optimization Process
(one row for illustration)
 Start
from equal distribution of decaps:
 Iteration 1:
 Iteration
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Optimization Results
Vdd =1.8V, vdrop limit =10%Vdd, ri = 80%
Chip
Opt
Num
bad
nodes
1
Before
After
105
2
974
0.193
0.176
0.121
0.000
53
1964
0.9
2
Before
After
80
63
861
0.230
0.196
0.366
0.063
85
3288
15.2
3
Before
After
100
70
828
0.222
0.201
0.649
0.200
132
3664
12.5
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Num Vmax
of
(V)
nodes
Z
(Vns)
Num
of
rows
Num
of
dcps
CPU
time
(mins)
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VDD and GND Contour (chip2)
Vmax=0.190V
Vmax=0.191V
Z=0.366(V•ns)
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Vmax=0.230V
Vmax=0.196V
Z=0.063(V•ns)
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Optimal Placement (chip2)
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Noise Reduction Trend (chip2)
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Conclusion
 Proposed a scheme of decoupling capacitor sizing
and placement for standard-cell layouts
 Applied after placement and before signal routing
 Formulated into nonlinear programming problem
 Reduced transient noise
 Presented a fast piece-wise linear waveform
convolution for adjoint sensitivity analysis
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Thank you!
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