Transcript Slide 1
Analog to Digital in a Few Simple Steps A Guide to Designing with SAR ADCs Miro Oljaca Senior Applications Engineer Texas Instruments Inc Tucson, Arizona USA [email protected] SAR ADC’s Block Diagram Sample & Hold Amplifier Sampling Signal Equivalent Input Circuit SAR ADC Sample & Hold Amplifier VIN S1 S2 RS1 + CSH From the Data Sheet for ADS8326: - Sampling capacitor is 48pF - Sampling switch resistance is 50Ω VSH0 Sample and Conversion Process VIN S1 S2 RS1 VIN + CSH VSH0 S1 S2 RS1 + CSH VSH0 Sample and Conversion Timing Voltage Ripple on The Input of ADC Sampling Signal VIN S1 RS1 CSH Analog Input Signal Voltage Across Sampling Capacitor VCSH VIN S1 VIN 1/2 LSB RS1 VCSH(t) t=0 CSH VSH0 t0 tAQ Time t VCSH (t ) VCSH (t0 ) [VIN VCSH (t0 )] (1 e ) RS1 CSH Settling Time as a Function of Time Constant VIN VCSH (t AQ ) 12 LSB VCSH(tAQ) is voltage across the CSH, at the end of the sampling period tAQ is acquisition time, the time from the beginning of the sampling period (t0) to the end of the sampling period 1 FSR LSB N 1 2 2 (LSB = Least Significant Bit, FSR is the full-scale range of the N-Bit converter) t AQ k1 k1 ( N 1) ln(2) Time-Constant-Multiplier (k1) for SAR ADC Resolution k1 time-constant-multiplie N+1 1/2 LSB accuracy, 1/2 8 10 12 14 16 18 20 6.2 7.6 9.0 10.4 11.8 13.2 14.6 ADC *note – using worst case values: VIN = full-scale voltage or 2N, VSH0 = 0V SAR ADC With Input RC Filter SAR ADC VCSH RF VIN S1 S2 RS1 + CF RF CF CSH t AQ ( N 1) ln(2) VSH0 ADC Input With Proper RC Filter Start Acquisition End Acquisition ADC Input With Wrong RC Filter Start Acquisition End Acquisition Op Amp Driving RC Filter - + RO RF VOA CF Modified Open-Loop Voltage Gain 140 120 Voltage Gain (dB) 100 fPX, GPX 80 60 fZX, G ZX -40dB/Dec 40 -20dB/Dec fU 20 -20dB/Dec 0 fC -20 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M Added Pole and Zero 1 2 ( RO RF ) C F Frequency of added pole f PX Frequency of added zero f ZX Gain of added pole GPX Gain of added zero GZX 1 2 RF C F f PX 20 log f U f ZX GPX 40 log f PX Good Design Guideline fC 1 2 f ZX fU 1 2 fC 1 4 fU or f C 12 fU f ZX 12 f C or f ZX GZX 6dB f ZX 14 fU GZX 6dB f PX 101 f ZX RO RF 9 Final Circuit SAR ADC OP AMP VCSH - RO RF VIN S1 S2 RS1 + + CF CSH VSH0 Minimum Acquisition Time and Op Amp’s GBW • • Calculate time-constant multiplier Determine minimum time-constant • Calculate frequency of added zero • Find Unity Gain Bandwidth k ( N 1) ln(2) f ZX t AQ k 1 2 GBW 4 f ZX Minimum Acquisition Time for Different Op Amps INA155 INA128 INA331 OPA340 OPA363 OPA2613 OPA627 OPA381 OPA727 OPA228 OPA350 OPAy365 OPA2889 OPA211 THS4281 OPA358 Medium Speed, Precision INA High Precision, 120dB CMRR High Bandwidth, Single Supply CMOS, 0.0007% THD+N 1.8V, High CMRR, SHDN Dual VFB, Low Noise Ultra-Low THD+N, Wide BW Precision High-Speed Amp CMOS, e-trim™, Low Noise Precision, Low Noise, G ≥ 5 Precision ADC Driver High-Speed, Zero-Crossover Dual, Low Power, VFB 36V, Bipolar Precision Very Low Power RRIO CMOS, 3V Operation, SC70 GBW (MHz) fZ (MHz) τ (ns) 12 Bit tAQ (ns) 0.55 1.3 5.0 5.5 7.0 12.5 16.0 18.0 20.0 33.0 38.0 50.0 75.0 80.0 80.0 80.0 0.14 0.33 1.25 1.38 1.75 3.13 4.00 4.50 5.00 8.25 9.50 12.50 18.75 20.00 20.00 20.00 1,157 490 127 116 91 51 40 35 32 19 17 13 8 8 8 8 5,672 2,400 624 567 446 250 195 173 156 95 82 62 42 39 39 39 16 Bit tAQ (ns) 8,881 3,757 977 888 698 391 305 271 244 148 129 98 65 61 61 61 Not Good Design Guideline f C f ZX or GZX 0dB Stability Problem After selecting ADC and OpAmp • • • Determine CF 20 CSH CF 60 CSH Calculate RF 1 RF 2 CF f ZX Verify value RF RO RF 9 1 2 ( RF RO ) CF • Calculate frequency of added pole f PX • Keep added pole and zero less then decade a part f PX 101 f ZX Design by Example For ADS8326 we have tAQ=750ns, CSH=48pF and N=16. k ( N 1) ln(2) (16 1) ln(2) 11.78 1 f ZX 2 3 4 t AQ 750ns 63.65ns k 11.78 1 1 2.5MHz 2 2 63.65ns GBW 4 f ZX 4 2.5MHz 10MHz 20 CSH CF 60 CSH 20 48 pF CF 60 48 pF 960pF CF 2.9nF CF 1.2nF 1 1 RF 53 2 CF f ZX 2 1.2nF 2.5MHz ADC and DAC Functions ADC : VIN CODE N 2 CODE VIN VREF VREF CODE VOUT DAC : VOUT VREF VREF CODE N 2 Noise and ENOB of ADC Signal-to-Noise Ratio and Distortion SNR 10 SINAD(dB) 20log 10 10 Effective Number of Bits ENOB SINAD 1.76dB 6.02 ENOB f (SNR, THD) THD 10 Noise Sources in SAR ADCs • • • • • • Wideband ADC internal circuits noise Noise due to aperture jitter Quantization noise Transition or DNL noise Analog input buffer circuit noise Reference input voltage noise Measuring Reference Input Noise REF5040 VIN ≈ 0V or VIN ≈ FSR REFIN CS - VOUT ADS8326 + CLK SDO Noise Contribution 50 ADC + REF Noise 45 40 REF Noise Noise [uVrms] 35 30 25 20 ADC Internal Noise 15 10 5 0 0 0.5 1 1.5 2 2.5 Input Voltage [V] 3 3.5 4 4.5 Quantization of Reference Noise • Low noise analog input of 0.09V – Source of noise is ADC’s internal noise. – Measured noise is 27µVRMS or 179µVPP • Low noise analog input of 4.02V – Source of noise is ADC’s internal noise and reference input noise. – Measured noise is 43µVRMS or 287µVPP Sources of the Noise in REF50xx 1.2V VOUT + + Noise Source RMS Low Pass Filter Shapes the Output Noise Spectrum 1/f Region Source: Art Kay; OpAmp Noise 2006 Broadband Region Low pass filter REF50xx Noise Test Circuit Variable +5V CIN 10F NC 1 8 NC VIN 2 7 NC TEMP 3 6 VOUT GND 4 5 TRIM REF5040 +4.096V COUT 1F - 50F Capacitor Equivalent Circuit ESL ESR IR C ESR ESL IR C Capacitance Equivalent Series Resistance Equivalent Series Inductance Insulation Resistance Capacitive Load with ESR VCC 1 fP 2 ( RO ESR) CL ++- RO ESR CL 1 fZ 2 ESR CL Measured Noise for different BW and LP Filters Measurement Bandwith 30kHz 80kHz LP-3P LP-3P Noise 22kHz LP-5P >500kHz Units GND 1µF 0.8 1 1.8 4.9 µVRMS 37.8 41.7 53.7 9,017 µVRMS 2.2µF (cer) 41.7 46.2 55.1 60.8 µVRMS 10µF 33.4 33.4 35.2 38.5 µVRMS 10µF (cer) 37.1 37.2 37.8 39.1 µVRMS 20µF (cer) 33.1 33.1 33.2 34.5 µVRMS 47µF 23.2 23.8 24.1 26.5 µVRMS The capacitor on the output of REF50xx together with internal components will create Low Pass filters. Filtering Internal Bandgap Reference 1.2V 10k VOUT + + TRIM 1k Measured Noise with Added Bandgap Filter Noise 22kHz LP-5P Measurement Bandwith 30kHz 80kHz LP-3P LP-3P >500kHz Units GND 2.2µF (cer) 0.8 1 1.8 4.6 µVRMS 42.5 47.2 61.2 68.3 µVRMS 2.2µF+1µF 17.5 19.4 22.6 24.5 µVRMS 10µF 34.4 35.6 37.7 44.5 µVRMS 10µF+1µF 14.1 14.4 14.9 16.4 µVRMS 20µF (cer) 34.8 34.9 35.1 35.2 µVRMS 20µF+1µF 14.4 14.4 14.7 15.1 µVRMS Adding 1µF capacitor on the TRIM pin will reduce noise ~2.5x REF5040 Output with 10μF and <10mΩ ESR Capacitor BW=80kHz noise=16.5μVRMS BW=65kHz noise=138μVPP Added RC filter on the Output 5V 1.2V 10k + + ESR REF5040 10uF 10uF Adding RC filter reduce noise from xx to xx REF5040 Output with added RC Filter BW=80kHz noise=2.2μVRMS BW=65kHz noise=15μVPP SAR ADC Capacitive Conversion Network Comparator ADS83xx + Capacitive Conversion Network C VIN+ S0 C C/21 C/22 C/23 C/2N S1 S2 S3 SN C/2N VREF Scaling REF Input With Proper Buffer Start Conversion End Conversion REF Input With Wrong Buffer Start Conversion End Conversion Voltage-reference circuit with added buffer and output filter 5V OPA350 5V 1.2V 10k + ESR + + ESR 10uF 10uF REF5040 10uF BW=80kHz noise=4.5μVRMS BW=65kHz noise=42μVPP Design by Example 1. Use REF5040 and 10μF with 0.5Ω<ESR<1.5Ω (Vn=39μVRMS/261μVPP) 2. Add 1μF on the TRIM pin (Vn=16μVRMS/138μVPP) 3. Use additional RC Filter (10kΩ/10μF) (Vn=2.2μVRMS/15μVPP) 4. Buffer output with OPA350 and 10μF with 0.2Ω<ESR (Vn=4.5μVRMS/42μVPP) References 1) Green, Tim, “Operational Amplifier Stability, Part 6 of 15: Capacitance-Load Stability: RISO, High Gain & CF, Noise Gain,” Analog Zone, 2005. 2) Miro Oljaca, and Baker Bonnie, “Start with the right op amp when driving SAR ADCs,” EDN, October 16, 2008, 3) Downs, Rick, and Miro Oljaca, “Designing SAR ADC Drive Circuitry, Part I: A Detailed Look at SAR ADC Operation,” Analog Zone, 2005. 4) Downs, Rick, and Miro Oljaca, “Designing SAR ADC Drive Circuitry, Part II: Input Behavior of SAR ADCs,” Analog Zone, 2005. 5) Downs, Rick, and Miro Oljaca, “Designing SAR ADC Drive Circuitry, Part III: Designing The Optimal Input Drive Circuit For SAR ADCs,” Analog Zone, 2007. 6) Baker, Bonnie, and Miro Oljaca, “External components improve SAR-ADC accuracy,” EDN, June 7, 2007, 7) Miroslav Oljaca, “Understand the Limits of Your ADC Input Circuit Before Starting Conversions,” Analog Zone, 2004. References Cont. 8) Art Kay, “Analysis and Measurement of Intrinsic Noise in Op Amp Circuits Part 1 to 8”, Analog Zone / En-Genius, 2006-2008 9) Oljaca, M., Klein, W., “Converter voltage reference performance improvement secrets”, Instrumentation & Measurement Magazine, IEEE, Volume: 12 Issue: 5 October 2009, Page(s): 21-27, 10) Bonnie Baker, and Miro Oljaca, "How the voltage reference affects ADC performance, Part 3 of 3", Analog Applications Journal, Texas Instruments, Q4Y09, 2009 11) Miro Oljaca, and Bonnie Baker, "How the Voltage Reference Affects your Performance: Part 2 of 3", Analog Applications Journal, Texas Instruments, Q3Y09, July 2009 12) Bonnie Baker, and Miro Oljaca, “How the Voltage-reference affects Your Performance: Part 1 of 3”,, Analog Applications Journal, Texas Instruments, Q2Y09, 2009 13) Miro Oljaca, “Converter Voltage Reference Performance Improvement Secrets” Embedded Systems Conference, Silicon Valley, 2008 Questions? Thanks for Your Interest in From Analog to Digital: Design In a Few Simple Steps Miro Oljaca Senior Applications Engineer Texas Instruments Inc Tucson, Arizona USA [email protected]