Transcript FUNDAMENTALS OF HDL (10EC45)

FUNDAMENTALS OF HDL
(10EC45)
7/16/2015
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PART - A
UNIT - 1
Introduction: Why HDL? , A Brief History of HDL, Structure of HDL Module, Operators, Data
types, Types of Descriptions, simulation and synthesis, Brief comparison of VHDL and
Verilog.
7 Hours
UNIT - 2
Data –Flow Descriptions: Highlights of Data-Flow Descriptions, Structure of Data-Flow
Description, Data Type – Vectors.
6 Hours
UNIT - 3
Behavioral Descriptions: Behavioral Description highlights, structure of HDL behavioral
Description, The VHDL variable –Assignment Statement, sequential statements.
6 Hours
UNIT - 4
Structural Descriptions: Highlights of structural Description, Organization of the structural
Descriptions, Binding, state Machines, Generate, Generic, and Parameter statements.
7 Hours
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PART-B
UNIT - 5
Procedures, Tasks, and Functions: Highlights of Procedures, tasks, and Functions,
Procedures and tasks, Functions.
Advanced
HDL
Descriptions:
File
Processing,
Examples
of
File
Processing
7 Hours
UNIT - 6
Mixed –Type Descriptions: Why Mixed-Type Description? VHDL User- Defined Types,
VHDL Packages, Mixed-Type Description examples
6 Hours
UNIT - 7
Mixed –Language Descriptions: Highlights of Mixed-Language Description, How to
invoke One language from the Other, Mixed-language Description Examples,
Limitations of Mixed-Language Description.
7 Hours
UNIT - 8
Synthesis Basics: Highlights of Synthesis, Synthesis information from Entity and
Module,
Mapping
Process
and
Always
in
the
Hardware
Domain.
6 Hours
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HDL Programming (VHDL and Verilog)- Nazeih M.Botros- John Weily India
Pvt. Ltd. 2008.
REFERENCE BOOKS:
1. Fundamentals of HDL – Cyril P.R. Pearson/Sanguin 2010.
2. VHDL -Douglas perry-Tata McGraw-Hill
3. A Verilog HDL Primer- J.Bhaskar – BS Publications
4. Circuit Design with VHDL-Volnei A.Pedroni-PHI
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VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
VERILOG CODE
module gates(a, op_not);
ENTITY GATES IS
reg op_not;
always @ (a , b)
begin
PORT ( A : IN STD_LOGIC;
OP_NOT : OUT STD_LOGIC);
op_not= ~a;
END GATES;
ARCHITECTURE BEHAVIORAL OF
GATES IS
BEGIN
OP_NOT <= NOT A;
END BEHAVIORAL;
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input a;
output op_not;
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end
endmodule
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• What about technology ……?
• Where are you now …..?
• What will next …..?
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Specifications
High-level
Description
Behavioral
VHDL, Verilog
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Functional
Description
High-level
Description
Specifications
Physical
Design
Placed
& Routed
Design
Packaging
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Gate-level
Design
Fabrication
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Functional
Description
Synthesis
Technology
Mapping
Logic
Description
X=(AB*CD)+
(A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
Why HDL?
ASICs FPGAs
Schematic versus Program
History of HDL
VHDL
VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
IEEE standard 1076-1993.
December 1995, Verilog HDL became IEEE Std. 1364-1995
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Structure of HDL Module
Start with VHDL; Verilog is discussed later
entity illustrate is
port (I1, I2 : in bit; O1, O2 : out bit);
end;
architecture dtfl_ex of illustrate is
Begin
O1 <= I1 xor I2; -- statement 1
O2 <= I1 and I2; -- statement 2
--Blank lines are allowed
end dtfl_ex;
VHDL Ports
VHDL PORTS
In, out, buffer, inout, linkage
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