Transcript UNIT-2-Data-Flow-description - KIT

UNIT 2: Data Flow description
OBJECTIVES
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•Understand
the concept of data flow description
•Identify the basic statements and components of data flow
•Review and understand the fundamentals of some digital
logic systems such as half adder, 2x1 multiplexer, 2x2 combinational array
multiplier, 2-bit comparator, D-latch, ripple-carry adder, and carry-lookahead Adder.
2.1 Highlights of Data Flow Description
• Data flow description simulates the system by showing how the signal flows
from the input of the system to its output. The Boolean function of the
output or the logical structure of the system shows such signal flow.
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• Signal assignment statements are concurrent. At any simulation time, all signal
assignment statements that have an event are executed concurrently.
2.2 Structure of Data Flow Description
Listing 2.1 Example of HDL Data Flow Description.
architecture dtfl_ex of system is
begin
O1 <= I1 and I2; -- statement 1.
O2 <= I1 xor I2; -- statement 2.
--Statements 1 and 2 are signal assignment statements
end dtfl_ex;
HDL Programming Fundamentals
entity system is
port (I1, I2 : in bit; O1, O2 : out bit);
end;
2.2.1 Signal Declaration and Assignment Statements
signal s1, s2: bit;
a
s1
b
c
d
s2
2.2.2 Concurrent Signal Assignment Statement
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y
See slide 4
All statements that have event (s) on the right hand side
are executed concurrently
event
event
event
event
I2
event
I1
event
event
event
10 ns
Calculate
0 and 1 =0
Assign 0
Calculate
0 and 1 =0
Assign 0
O1 <= I1 and I2;
Calculate
1 and 1 =1
Assign 1
Calculate
1 and 1 =1
O1 <= I1 and I2 after 10 ns;
Can you do the same for O2?
Assign 1
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O1
2.2.3 Constant Declaration and Assignment Statements
Constant period: time := 100 ns;
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Example 2.1 Data Flow Description of a Half Adder
Listing 2.2
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2.2.4 Assigning Delay Time to Signal Assignment Statement
S1 <= sel and b after 10ns; ………(VHDL)
assign #10 S1 = sel & b …………(Verilog).
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The 10 in Verilog code is 10
screen units
Example 2.2 2x1 Multiplexer with active low enable
Gbar
H
L
L
Output
Y
L
A
B
Y = (G and A and SEL ) or (G and B and SEL); G is the invert of Gbar
A
S4
Y
B
SEL
Gbar
S2
S3
S1
S5
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Input
SEL
X
L
H
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2x1 is
port (A,B,SEL, Gbar: in std_logic;
Y: out std_logic);
end mux2x1;
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architecture MUX_DF of mux2x1 is
signal S1, S2, S3,S4, S5 : std_logic;
Constant dly : time := 7 ns; -- replace all 7 ns with dly.
Begin
-- Assume 7 nano seconds propagation delay
-for all and, or, and not.
st1: Y <= S4 or S5 after 7 ns;
st2: S4 <= A and S2 and S1 after 7 ns;
st3: S5 <= B and S3 and S1 after 7 ns;
st4: S2 <= not SEL after 7 ns;
st5: S3 <= not S2 after 7 ns;
st6: S1 <= not Gbar after 7 ns;
end MUX_DF;
2.3 Data Type-Vectors
signal a:bit_vector (3 downto 0)……….VHDL
signal a:bit_vector (0 to 3)……….VHDL
wire [0:3] a………….Verilog
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wire [3:0] a………….Verilog
Example 2.3 2x2 Unsigned combinational array multiplier
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Example 2.3 2x2 Unsigned combinational array multiplier
0111
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Downto versus to
library IEEE;
If P = 7, downto
use IEEE.STD_LOGIC_1164.ALL;
to
1110
entity mult_arry is
port(a,b: in std_logic_vector(1 downto 0);
P: out std_logic_vector (3 downto 0));
end mult_arry;
architecture MULT_DF of mult_arry is
begin
--For simplicity propagation delay times are not considered
-- in this example.
P(0) <= a(0) and b(0);
P(1) <= (a(0) and b(1)) xor (a(1) and b(0));
P(2) <= (a(1) and b(1)) xor ((a(0) and b(1)) and (a(1) and b(0)));
P(3) <= (a(1) and b(1)) and ((a(0) and b(1))and (a(1) and b(0)));
end MULT_DF;
Example 2.4 D-Latch
_
Q = EQ + ED
Q current state
0
1
x
x
Next state
Q+
0
1
0
1
_
Qbar = Q
D
D
E
E
Q
Q
Latch-level sensitive. When E=1, Q = D
otherwise Q retains its previous value
Flip-flop, edge sensitive. When edge of E, Q=D
otherwise Q retains its previous value
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E
0
0
1
1
Inputs
D
x
x
0
1
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_
Qbar = Q
_
Q = EQ + ED
architecture DL_DtFl of D_Latch is
constant Delay_EorD: Time:= 9 ns;
constant Delay_inv : Time := 1 ns;
begin
--Assume 9 nsec propagation delay time between E or D and Qbar; and 1 nsec
-- between Qbar and Q.
Qbar <=(D and E) nor (not E and Q)after Delay_EorD;
Q <= not Qbar after Delay_inv;
end DL_DtFl;
HDL Programming Fundamentals
Example 2.4 D-latch
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_Latch is
port (D, E: in std_logic;
Q, Qbar: buffer std_logic);
-- Q and Qbar are declared as buffer because they act as both input and
--output, they appear on the right and left hand side of signal assignment
--statements. inout or linkage could have been used instead of buffer.
end D_Latch;
D
9
nsec
Q
1 nsec
Qbar
_
Above waveform is for Q = EQ + ED ,
_
Qbar = Q
HDL Programming Fundamentals
E
Compare between latch and Flip-Flop. What would be the waveform for FF?
In Class Practice
2.2 Write a data-flow description (both VHDL and Verilog) of a system that has three 1-bit inputs a(1), a (2), and a (3), and
one 1-bit output b. a(1) is the least significant bit. b is 1 only when {a(1)a(2)a(3)}= 1,3, 6 or 7 (all in decimal),
otherwise 0. Derive a minimized Boolean function of the system and write the data flow description. Simulate the system
and verify it is working as designed. What is the function of this system?
a(1)
Output
b
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
b  a(3)a(1)  a(3)a(2)
a(1)
0
2X1
The system is 2x1 multiplexer
a(2)
a(3)
1
MUX
b
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Input
a(3)
a(2)
--Program for prob 2.2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity probl2_2 is
port ( a : in std_logic_vector (3 downto 1); b: out std_logic);
architecture dataflow of probl2_2 is
begin
b <= ((not a(3)) and a(1)) or (a(3) and a(2));
end dataflow ;
--bit could have been used instead of std_logic.
HDL Programming Fundamentals
end probl2_2;
--Since no delay time is specified we wrote one Boolean equation of the system; if
--delay time is required, we have to use intermediate signals to describe the invert
-- of a3, the “and”, and the “or”
Verilog
1.3.2
Structure of Verilog Module
Verilog is case
Sensitive
A≠a
ADDR ≠ ADDr
1.3.2.1 Verilog Ports
input: the port is an input port only, the port is read.
output: the port is an output port. The port, in contrast to VHDL output port,
may appear in both sides of the assignment statement.
inout: the port can be used as both input and output. The inout port is
representing a bidirectional buss.
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module half_adder (I1,I2, O1, O2);
input I1;
input I2;
output O1;
output O2;
//Blank lines are allowed
assign O1 = I1 ^ I2; //statement 1
assign O2 = I1 & I2; // statement 2
endmodule
Verilog Counterpart
module
assign
&, |, ^, ~
wire
#
input, output, inout
[]
module mux2x1(A,B,SEL,Gbar,Y);
input A,B,SEL,Gbar;
output Y;
wire S1,S2,S3,S4,S5;
/* Assume 7 time units delay for all and, or, not. In Verilog we can not use specific time
units such as nano seconds, the delay here is expressed in simulation screen units. */
assign #7 Y = S4 | S5; // st1.
assign #7 S4 = A & S2 & S1; // st2
assign #7 S5 = B & S3 & S1; //st3
assign #7 S2 = ~ SEL; //st4
assign #7 S3 = ~ S2; //st5
assign #7 S1 = ~ Gbar; // st6
endmodule
As in VHDL, all signal assignment statements
(st1-st6) that have an event in the right hand
side are executed concurrently. Execution is
done, as in VHDL, in two phases: Calculate
and Assign
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VHDL Commands or Components
entity
<=
and, or, xor, not
signal
after
in, out, inout
()
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b) Verilog 2x2 unsigned comb. Array multiplier (Listing 2.4)
module mult_arry(a,b,P);
input [1:0] a,b;
output [3:0] P;
/*For simplicity, propagation delay times are not considered in this
example.*/
assign P[0] = a[0] & b[0];
assign P[1] = (a[0] & b[1]) ^ (a[1] & b[0]);
assign P[2] = (a[1] & b[1]) ^ ((a[0] & b[1]) & (a[1] & b[0]));
assign P[3] = (a[1] & b[1]) & ((a[0] & b[1])& (a[1] & b[0]));
endmodule
In Class Practice
2.2 Write a data-flow description (both VHDL and Verilog) of a system that has three 1-bit inputs a(1), a (2), and a (3),
and one 1-bit output b. a(1) is the least significant bit. b is 1 only when {a(1)a(2)a(3)}= 1,3, 6 or 7 (all in decimal),
otherwise 0. Derive a minimized Boolean function of the system and write the data flow description. Simulate the
system and verify it is working as designed. USE VERILOG
HDL Programming Fundamentals
module prob2_2(a,b);
input [3:1]a;
output b;
assign b= (~a[3] & a[1]) | (a[3] & a[2]);
endmodule
Example 2.5 2-bit Magnitude Comparator
Listing 2.6 Both VHDL and Verilog
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Case Study 2.1 Adders
Listing 2.7
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Ripple Carry Adder
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Look-ahead Adder
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2.4 Summary
entity
<=
and, or, xor, not
signal
after
in, out, inout
Verilog Counterpart
module
assign
&, |, ^, ~
wire
#
input, output, inout
HDL Programming Fundamentals
VHDL Commands or Components