Transcript Xilinx Template (light) rev

Architecture Wizard and I/O Planning
Xilinx Training
Objectives
After completing this module, you will be able to:
List at least two uses for the Architecture Wizard
Identify two features of the I/O Planner
Create quality pin assignments for Xilinx FPGAs
Architecture Wizard Contains Several Wizards
Use the command Project >
New Source
– Select IP (CORE Generator &
Architecture Wizard)
– Enter File name and click Next
– Select components by function
or name
Wizards available for
clocking, RocketIO™ serial
transceivers, and memory
interfaces
Clocking Wizard Helps You Define the DCM
Main window
– Select Clocking
Features
– Specify input clock
• Input Clock
frequency
• Input Jitter
Specify Output Settings
Specify output clock settings
Specify I/O and Feedback
 Select optional inputs / outputs and feedback
DCM Attributes
 Specify DCM attributes
Attributes are Written into the HDL Files by Default
Launching the I/O Planner from the Project
Navigator
Assign package pins
before or after synthesis
– Pins can be assigned before
synthesis to test pin
assignments
• Make sure assignments follow
the I/O Banking Rules
• Avoid ground bounce problems
with Simultaneous Switching
Output (SSO) analysis
• Make sure assignments are
appropriate for signals going
to/from dedicated hardware
Pin assignments are stored in
your design’s UCF
The I/O Planner is a Pin Assignment Editor Within
the PlanAhead Tool
The PlanAhead™ software is automatically installed with the
ISE® software and it includes the I/O Planner at no extra cost
The I/O Planner allows you to assign package pins before
synthesis or implementation
– This requires rules based I/O assignments
• DRC provides guidance for pin assignments connecting to dedicated
FPGA logic (memory controllers, GTs, or differential pairs, for example)
– Semi or fully automatic pin assignment capabilities
• Xilinx recommends that you place timing-critical ports before allowing
automatic pin assignment of the remaining pins
– Supports grouping related pins to simplify I/O interface management
I/O Planner GUI
Key Features
The I/O Planner allows you to view both the die and the package
views so that you can understand the I/O bank relationship with
your logic
Package View
The colored areas
between the pins
displays the I/O
Banks
Show Differential
Pairs
Global Clock pins
Vcc
GND
No connect
Using the Package Viewer
The Package Pin Viewer has a very
detailed list
– Uses both colors and symbols
Display includes
– Pin name (signal name, if assigned)
– Pin number (E6, if unassigned)
– Pin type (I/O)
– Differential pair type (N)
– Bank number (0)
Pin Type: IO_L21N_0, Bank Number: 0
Key Features
Final pin assignments can be exported in a CSV format (PCB
schematic symbol), HDL, or UCF
Cross highlighting of pins, I/O banks, package pins, and device
resources is supported throughout
Importing existing pin assignments is supported
– So if you are having a problem, it is not too late for help from the I/O
Planner
SSN analysis allows you to find I/O banks where you may be
close to creating a ground bounce problem
– This feature is customizable for your board
Other Features
SSN Results
Viewing Pin Compatibility
 The original chosen package of choice was  Modified package view after pin
compatibility is applied with XC5VLX110XC5VLX330-FF1760
FF1760
– To make it pin compatible simply right-click
in the package viewer
I/O Layout Guidelines
Control Signals
Data Buses
Data Buses
 Control signals enter in the
center column
 Data pins are placed in the
remaining columns
Data Flow
 Data flow is horizontal
 Can sometimes be
vertical, but not
common
 Clock regions tend to
group logic
Data Bus Layout
Follow bit ordering
MSB
Disperse simultaneous switching
outputs
– Helps avoid ground bounce
– Insert other unrelated bits in
between binary encoded output
pins
LSB
Interleaved Bus Layout
Arithmetic functions involving
two or more buses will benefit
from interleaved pin
constraints
– For example
• C <= A + B; or C <= A * B;
– Both buses follow bit ordering
B(3)
A(3)
B(2)
A(2)
B(1)
A(1)
B(0)
A(0)
Summary
The Architecture Wizard consists of several wizards, including
– Clocking Wizard
– RocketIO Wizard
– Memory Interface Generator
These wizards make it easy for you to optimize your design to
the dedicated resources in your FPGA
The I/O Planner makes it easy for you to make good pin
assignments that enhance your system speed and help you
avoid common mistakes
– Avoid ground bounce
– Follow I/O banking rules
– Comprehensive DRC
Where Can I Learn More?
Architecture Wizard
– More Info buttons in dialog boxes
Xilinx online documents
– www.support.xilinx.com
• Spartan-6 FPGA User guide
• Virtex-6 FPGA User guide
PlanAhead User Guide
– From the I/O Planner: Help > User Guide > PlanAhead User Guide
Where Can I Learn More?
Xilinx Education Services courses
– www.xilinx.com/training
• Xilinx tools and architecture courses
• Hardware description language courses
• Basic FPGA architecture and other topics
Trademark Information
Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on,
or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded,
displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or
otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of
privacy and publicity, and communications regulations and statutes.
Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,
copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no
obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the
accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH
YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE,
WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS,
IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH
YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF
FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT
THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU
WITHOUT THESE LIMITATIONS OF LIABILITY.
The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe
controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons
systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You
represent that use of the Design in such High-Risk Applications is fully at your risk.
© 2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All
other trademarks are the property of their respective owners.