ECNG 1014: Digital Electronics Lecture 5: Introduction to VHDL

This presentation can be used for non-commercial purposes as long as this note and the copyright footers are not removed © Lucien Ngalamou – All rights reserved

Definition of an HDL



Def: A high level programming language used to model hardware.



special hardware related constructs



digital (now) and analog (near future)



models used for documentation, simulation, synthesis, and test generation



have been extended to the system design level

(c) Lucien Ngalamou 2

An HDL is NOT a Software Programming Language

(c) Lucien Ngalamou 3

Language Semantics



Semantic: what is the meaning of a language construct?



HDLs have different semantics for different applications:



Simulation



Synthesis



Test



In this course we will be concerned with simulation and synthesis semantics.

(c) Lucien Ngalamou 4

VHDL

 VHDL = VHSIC Hardware Description Language  VHSIC = Very High Speed Integrated Circuit Program 

DOD began development in 1983

 

design exchange among VHSIC contractors document parts with long functional life



IEEE Standardization

  

Standardization process began in 1985 IEEE Standard 1076 in 1987 Updated in 1993 and 2002



In this note we will use subset of language features that are legal in all versions.

(c) Lucien Ngalamou 5

Significance of VHDL



VHDL provides a text based approach to structured hardware modeling and design.



Analogous to high level software languages such as PASCAL, C, C++, and JAVA.



An important tool in managing the complexity of VLSI systems.

(c) Lucien Ngalamou 6

Why Use VHDL?



Reason #1: it allows textual design representation



Reason #2: Ability to model at different levels of abstraction



Abstraction can be expressed in the following two domains:

 

Structural domain. A domain in which a component is described in terms of an interconnection of more primitive components.

Behavioral domain. A domain in which a component is described by defining its input/output response.



Abstraction Hierarchy. A set of interrelated representation levels that allow a system to be represented in varying amounts of detail.

(c) Lucien Ngalamou 7

(c) Lucien Ngalamou

Abstraction Levels

SYSTEM CHIP REGISTER GATE CIRCUIT SILICON 8

Level of Detail System Chip Register Gate Circuit Layout/Silicon

(c) Lucien Ngalamou

Design abstraction Hierarchy

Behavioral Domain Representation Performance specification (English) Algorithm Dataflow Boolean Equation Structural Domain Primitive Computer, disk, unit, radar Microprocessor, RAM, UART, parallel port Register, ALU, Counter, MUX, ROM And, Or, Xor, FF Differential equations Transistor, R, L, C Equations of electron and hole motion Geometric shapes

9

SILICON LEVEL

(c) Lucien Ngalamou 10

CIRCUIT LEVEL

G S V + D P V in G D N S Inverter (c) Lucien Ngalamou V out 11

GATE LEVEL

S Q (c) Lucien Ngalamou R S R Flip Flop Q Q Q 12

REGISTER LEVEL

REG CLK A (c) Lucien Ngalamou Select MUX REG INC CLK B 13

(c) Lucien Ngalamou µ P

CHIP LEVEL

8 RAM Par.

Port USART Int.

Con.

8 8 14

SYSTEM LEVEL

IMU A/B Computer RADAR C/D (c) Lucien Ngalamou 15



VHDL Provides total modeling capability at the gate level, register level, and chip level.



It can also be used in many applications at the:



system level



circuit level



Switch level (gate-circuit hybrid)

(c) Lucien Ngalamou 16

Reason #3: Design Decomposition

VHDL supports very naturally the Design Decomposition process.

Structural Decomposition behavioral model (c) Lucien Ngalamou 17

Reason #4: Design Validation

•VHDL can be used to validate design at a high level, thus detecting errors early in the design process.

•Important, because finding errors later is expensive (c) Lucien Ngalamou 18

VHDL Tool Suites



Xilinx ISE or Quartus from Altera:

 

Text Editor (VHDL Program), Schematic Editor, State Machine Editor



VHDL Compiler is responsible for parsing the VHDL program, finding syntax errors, and figuring out what the program really “says”.



Synthesizer (synthesis tool) targets the design to a specific hardware technology, such as a PLD, CPLD, FPGA, or ASIC.

Simulator

(c) Lucien Ngalamou 19



Basic elements of a VHDL Model

Package Declaration ENTITY (interface description) PACKAGE BODY (often used functions, constants, components, ….) ARCHITECTURE (functionality) CONFIGURATION (connection entity  architecture) (c) Lucien Ngalamou 20



Two concepts are often used in modeling digital circuits with VHDL:



The external view reflected in the entity declaration which represents an interface description. The important part of this interface description consists of signals over which different modules communicate with one another.



The internal view is described in the architecture body. The architecture can be expressed according to two major approaches:

  structural description which serves as a base for the hierarchical design, behavioral description (algorithm, sequential and concurrent).

(c) Lucien Ngalamou 21



Being able to investigate different architectural alternatives permits the development of systems to be done in an efficient top-down manner.



If the architecture body consists of a structural description, the binding of architectures and entities of the instantiated submodules, the so-called components is done using configuration statements.



The package contains declarations of frequently used data types, components, functions, etc. It consists of a package declaration and a package body.

(c) Lucien Ngalamou 22



Entity declaration

A This correspond to the information given by the symbols in traditional methods based on drawing schematics sum B Cin Full Adder carry Figure: Interface of a full-adder module Signals which are used for communication with the surrounding modules are called ports.

(c) Lucien Ngalamou 23

Example of Entity Entity fulladder - (after a double minus sign (-) the rest of the line is treated as a comment) - - Interface description of FULLADDER Port (A, B, Cin: in bit ; Sum, Carry: out bit ) ; End fulladder ;

(c) Lucien Ngalamou 24



This module has five ports. A port is used for interface purpose. It is characterized by its direction (mode) and the type of data it carries .



We can identify three different modes: (read and write) in (read only), out (write only), and buffer



The type can be: a bit , bit-vector , integer , etc…



Syntax: : entity entity_name is

      

[ generics ] [ ports ] [declarations (types, constants, signals) [definitions (functions, procedures)] [ begin -- normally not used statements] End [entity_name];

(c) Lucien Ngalamou 25

Architecture



The internal body of digital system is described by its architecture.



Syntax: architecture architecture_name of entity_name is [arch_declarative_part] begin [arch_statement_part] end [architecture_name];

(c) Lucien Ngalamou 26



Models of description



Structural description (connection of different components)



Behavioral description (algorithmic or testbench, concurrent, and sequential)

(c) Lucien Ngalamou 27

Fig. Hierarchical Circuit Design All the modeling styles share the same organization of the architecture.

Syntax: architecture architecture_name of entity_name [arch_declarative_part] begin keywords [architecture_part] end [architecture_name]; (c) Lucien Ngalamou 28

Architecture: Concurrent Behavioral Description

 

This kind of description specifies a dataflow through the entity based on concurrent signal assignment statements.

Example 1: architecture Concurrent of fulladder is

begin sum <= A xor B xor Cin after 5 ns; Carry <= (A and B) or (B and Cin) or (A and Cin) after 3 ns; end concurrent; • • The symbol <= indicates the signal assignment. signal in the expression on the right side changes.

(c) Lucien Ngalamou 29

Architecture: Sequential Behavioral Description 

Sequential behavioral descriptions are based on processes.



A process is constantly switching between the two states: the execution phase in which the process is active and the statements within this process is executed and the suspended state.



A process becomes active by an event on at least one signal belonging to the sensitivity list.



Syntax: [proc_label:] process (sensitivity list) [process_declarativ_part] begin [sequential-statement_part] end process [proce_label];

(c) Lucien Ngalamou 30



With wait statements (the process is executed until it reaches a wait statement)



Syntax: [proc_label:] Process [proc_declaratiV_part] Begin [seqential_statements] Wait ……; -- at least one wait statement [sequential_statements] End process [proc_lab];

(c) Lucien Ngalamou 31

(c) Lucien Ngalamou Example: architecture SEQUENTIAL of FULLADDER is begin process (A, B, C) variable TEMP : integer; variable SUM_CODE : bit_vector(0 to 3) := "0101"; variable CARRY_CODE : bit_vector(0 to 3) := "0011"; begin if A = '1' then TEMP := 1; else TEMP := 0; end if; if B = '1' then TEMP := TEMP + 1; end if; if C = '1' then TEMP := TEMP + 1; end if; - variable TEMP now holds the number of ones SUM <= SUM_CODE(TEMP); CARRY <= CARRY_CODE(TEMP); end process; end SEQUENTIAL; 32

Example: architecture SEQUENTIAL of DFF is begin process (CLK, NR) begin if (NR = '0') then - Reset: assigning "000...00" to the - parameterized output signal Q Q <= (others => '0'); elsif (CLK'event and CLK = '1') then Q <= D; end if; end process; end SEQUENTIAL; (c) Lucien Ngalamou 33

STRUCTURAL DESCRIPTION: Case of the fulladder 1-bit Full Adder Half Adder (2) (c) Lucien Ngalamou OR 34

Cin A B I1 I2 (c) Lucien Ngalamou S S1 I2 C I1 C1 S C C2 X Y Sum o Carry 35

Design Library

Structural Model

(c) Lucien Ngalamou

Half Adder Model Or Model

36

Structural Description 1: Use of Components

use work.all; architecture STRUCTUAL of fulladder is signal S1, C1, C2: BIT; component HA port (I1, I2: in bit; S, C: out bit); begin end component; component Ora end component; -- component instantiations INST_HA1: HA port map(I1=>A, I2=>B, S=>S1, C=>C1); INST_HA2: HA port map(I1=>Cin, I2=>S1, S=>Sum, C=> C2); INST_OR: ORa port map(X=>C1, Y=>C2, 0=>Carry); (c) Lucien Ngalamou port (X, Y: in bit; O: out bit); end STRUCTURAL; 37

Structural Description 2: Use of entity

use work.all; architecture STRUCTUAL of fulladder is signal S1, C1, C2: BIT := ‘0’; -- pointer to library models for all: HA use entity HA(BEHAVIOR); for all: ORa use entity ORa (BEHAVIOR); -- component instantiations begin C1: HA port map(I1=>A, I2=>B, S=>S1, C=>C1); C2: HA port map(I1=>Cin, I2=>S1, S=>Sum, C=> C2); C3: ORa port map(X=>C1, Y=>C2, 0=>Carry); end STRUCTURAL; (c) Lucien Ngalamou 38

Design Library Components

entity HA is port(I1, I2: in BIT; S, C: out BIT); end HA; architecture BEHAVIOR of HA is Begin begin S <= I1 exor I2; C <= I1 and I2; end BEHAVIOR; entity ORa is port(X, Y: in BIT; O: out BIT); end ORa; architecture BEHAVIOR of ORa is O <= X or Y; end BEHAVIOR; (c) Lucien Ngalamou 39

Configuration



The concept of configuration in VHDL allows an entity to have multiple associated architectures.



The role of the configuration is to define a unique system description from the various design units.

(c) Lucien Ngalamou 40



Configuration Specifications - specify the bindings between a component instance in a structural architecture and a library model.



Configuration specifications can be in the structural architecture itself or in a configuration declaration.



Configuration Declaration (Body) - A separate analyzable entity which holds all the component bindings for a structural architecture.

(c) Lucien Ngalamou 41

Bindings (c) Lucien Ngalamou

Model Bindings

42

Steps in VHDL Modeling

A Design Entity Interface Description Arch 2 Arch 1 A

1 0 1

ONES COUNTER Arch 3

1 0

C

43

1 2 entity ONES_CNT is port (A: in BIT_VECTOR(2 downto 0); C: out BIT_VECTOR(1 downto 0)); ------ Truth Table: ---------------------------------- ---|A2 A1 A0 | C1 C0 | ------------------------------- -- |0 0 0 | 0 0 | -- |0 0 1 | 0 1 | -- |0 1 0 | 0 1 | -- |0 1 1 | 1 0 | -- |1 0 0 | 0 1 | -- |1 0 1 | 1 0 | -- |1 1 0 | 1 0 | -- |1 1 1 | 1 1 | ---------------------------------- end ONES_CNT; (c) Lucien Ngalamou 1 44 2

1 2 3 architecture ALGORITHMIC of ONES_CNT is begin process(A) variable NUM: INTEGER range 0 to 3; begin NUM := 0; for I in 0 to 2 loop if A(I) = '1' then NUM := NUM + 1; end if; end loop; case NUM is when 0 => C <= "00"; when 1 => C <= "01"; when 2 => C <= "10"; when 3 => C <= "11"; end case; end process; end ALGORITHMIC; (c) Lucien Ngalamou 1 2 45 3

Kmap Design

Truth Table:

---------------------------------- |A2 A1 A0 | C1 C0 | ------------------------------- |0 0 0 | 0 0 | |0 0 1 | 0 1 | |0 1 0 | 0 1 | |0 1 1 | 1 0 | |1 0 0 | 0 1 | |1 0 1 | 1 0 | |1 1 0 | 1 0 | |1 1 1 | 1 1 | ---------------------------------- (c) Lucien Ngalamou 46

K - Maps for the Ones Counter

A1 A0 A2 | 00 01 11 10 | 0 1 1 1 1 1 C1 A1 A0 A2 | 00 01 11 10 | 0 1 1 1 1 1 C0 C1 = A1A0 + A2A0 + A2A1 C0 = A2A1’A0’ + A2’A1’A0 + A2A1A0 + A2’A1A0’ (c) Lucien Ngalamou 47

1 2 architecture DATA_FLOW of ONES_CNT is begin C(1) <= (A(1) and A(0)) or (A(2) and A(0)) or (A(2) and A(1)); C(0) <= (A(2) and not A(1) and not A(0)) or (not A(2) and not A(1)and A(0)) or (A(2) and A(1) and A(0)) or (not A(2) and A(1) and not A(0)); end DATA_FLOW; 1 2 (c) Lucien Ngalamou 48

architecture MACRO of ONES_CNT is begin C(1) <= MAJ3(A); C(0) <= OPAR3(A); end MACRO;

Must be previously declared

(c) Lucien Ngalamou 49

Structural Decomposition For Ones Counter

(c) Lucien Ngalamou Structural design hierarchy for the ones counter.

50

Structural Model

(c) Lucien Ngalamou

Design Library AND2 MODEL OR2 MODEL AND3 MODEL OR4 MODEL INV MODEL

51

structural model (c) Lucien Ngalamou 52

AND2 Description entity AND2 is port (I1,I2: in BIT; O: out BIT); end AND2; architecture BEHAVIOR of AND2 is begin O <= I1 and I2; end BEHAVIOR;

(c) Lucien Ngalamou 53

OR3 Description entity OR3 is port (I1,I2,I3:in BIT; O: out BIT); end OR3; architecture BEHAVIOR of OR3 is begin O <= I1 or I2 or I3; end BEHAVIOR

; (c) Lucien Ngalamou 54

(c) Lucien Ngalamou

A properly labeled schematic

55

1 2 3 entity MAJ3 is port (X: in BIT_VECTOR(2 downto 0); Z: out BIT); end MAJ3; architecture AND_OR of MAJ3 is component AND2 -- unbound

MAJ3

port (I1,I2: in BIT; O: out BIT); end component; component OR3 -- unbound port (I1,I2,I3: in BIT; O: out BIT); end component; signal A1,A2,A3: BIT; begin G1: AND2 port map (X(0),X(1),A1); G2: AND2 port map (X(0),X(2),A2); G3: AND2 port map (X(1),X(2),A3); G4: OR3 port map (A1,A2,A3,Z); end AND_OR;

Structural Model (Unbound)

2 3 1 (c) Lucien Ngalamou 56

Configuration: case of behavioral descriptions



The only information which the configuration has to include is the choice of one architecture for the given entity.



Syntax: configuration configuration_name of entity_name is

for architecture_name End for; End configuration_name (c) Lucien Ngalamou 57



Example:

confi CFG_ONE of fulladder is

For CONCURRENT End for; End CFG_ONE; Configuration CFG_TWO of fulladder is For SEQUENTIAL End for; End CFG_ONE;

(c) Lucien Ngalamou 58

Configuration: case of structural descriptions

If the configuration binds a structural description to an entity then further information about the instantiated components is required. Due to the fact that the name of a component in the

component declaration

needs not be the same as the entity name of the instantiated component, their binding must be done by the configuration. Furthermore, the binding of the component's entity and architecture must be established by the configuration (c) Lucien Ngalamou 59

Example: configuration THREE of FULLADDER is for STRUCTURAL for INST_HA1, INST_HA2: HA use entity WORK.HALFADDER(CONCURRENT); end for; for INST_XOR: XOR use entity WORK.XOR2D1(CONCURRENT); end for; end for; end THREE; (c) Lucien Ngalamou 60

 In general, a configuration declaration belonging to an architecture with instantiated components is of the form:  Syntax: configuration

configuration_name

for

architecture_name

of

entity_name

is for

label

|others|all:

comp_name

use entity [

lib_name

.]

comp_entity_name

(

comp_arch_name

) | use configuration [

lib_name

.]

comp_configuration_name

[generic map (...)] [port map (...)] ; end for; ... end for; end

configuration_name

; (c) Lucien Ngalamou 61