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ECNG 1014: Digital Electronics Lecture 3: Technology

Topics



Introduction



Basic Operational Characteristics and Parameters of Integrated Circuits



CMOS Technology



Overview of TTL Technology



Some Practical Considerations

1. Introduction



Technology = Mean and physical implementation of real digital circuits whose behaviors are dictated by digital laws (combinational or sequential)



To understand some of the issues related to the technology, a number of questions must be answered such as:

   

What type of electronic basic element (passive or active) can be used to implement a simple gate as an “inverter”?

How efficient is an implementation in terms of power and speed?

What is the level of integration?

How to characterize a digital electronic device?



We are fortunate that these questions were answered properly in the past by many physicists. We will present their outcomes in term of technology.

2. Basic Operational Characteristics and Parameters



Digital components are called “Integrated circuits”. They are implemented using transistors.



In Digital electronics, transistors are always configured to work in switching modes.



The type of transistor being used defines the technology:



TTL (transistor-transistor-logic) for bipolar transistors



CMOS (complementary MOS) for MOSFET transistors



MOSFET = metal-oxide semiconductor field-effect transistor



The following figure show an IC packages that contains “nand” gates.

Figure 1: IC Package containing Nand Gates.

( from Floyd’s Text)

2.1. Logic Levels



The concept of logic levels is used to represent logic variables in digital electronic circuits.



There are four different logic-level specifications:

   

V IL (Voltage input Low) V IH (Voltage input high) V OL (Voltage output low) V OH (Voltage output high)



Figures 2 and 3 show clearly that these two technology don’t support all the ranges of voltages.



If and input falls into the restricted region the behavior of the circuit is unpredictable, therefore its output doesn’t represent a valuable information.

Figure 2: Inputs and output logic levels for CMOS (c) Lucien Ngalamou

( from Floyd’s Text)

 Figure 3: Input and output Logic levels for TTL (c) Lucien Ngalamou

( from Floyd’s Text)

2.2 Noise



Noise is unwanted voltage that is included in electrical circuits and can present a threat to a proper operation of the circuit.



Sources of noise are: power supply, cross talk (coupling), interference, offset, etc.



Examples of noise:



Thermal noise

 

Electromagnetic noise Power-line voltage fluctuation noise



In order not to be adversely affected by noise, a logic circuit must have a certain amount of noise immunity .



Examples of electromagnetic noise due to coupling:

 

capacitive coupling

 v(t)

voltage change on one wire can influence signal on the neighboring wire



cross talk inductive coupling

i(t) 

current change on one wire can influence signal on the neighboring wire

 For robust circuits, we want the “0” and “1” intervals to be a s large as possible DD V DD V OH min

Noise Margin High Noise Margin Low

V OL max NM H = V OHmin V IHmin NM L = V ILmax - V OLmax

"1"

V IH min V IL max

Undefined Region

Gnd

Gate Output "0"

Gnd

Gate Input

2.3 Noise Immunity



Noise immunity

expresses the ability of the system to process and transmit information correctly in the presence of noise



For good noise immunity, the signal swing (i.e., the difference between V OH and V OL ) and the noise margin have to be large enough to overpower the impact of fixed sources of noise

2.4 Static Gate Behavior



Steady-state parameters of a gate –

static behavior

– tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances.



Digital circuits perform operations on Boolean variables x



{0,1}



A logical variable is associated with a

nominal voltage level

each logic state for 1



V OH and 0



V OL

= complement V(x) V(y) V OH = ! (V OL ) V OL = ! (V OH ) 

Difference between V OH

swing

V sw

and V OL is the logic or

signal

2.5 DC Operation

Voltage Transfer Characteristics (VTC)

 Plot of output voltage as a function of the input voltage V(x) V(y) V(y) V OH = f (V IL ) f V(y)=V(x) V M

Switching Threshold

V OL = f (V IH ) V IL V IH V(x) (c) Lucien Ngalamou 15

2.6. Mapping Logic Levels to the Voltage Domain

 The regions of acceptable high and low voltages are delimited by V IH and V IL that represent the points on the VTC curve where the gain = -1

"1"

V OH V IH

Undefined Region

"0"

V IL V OL V(y) V OH V OL Slope = -1 Slope = -1 V IL V IH V(x) (c) Lucien Ngalamou 16

2.7. Logic Levels: Practical Scenario



The two sets of levels are motivated by these scenarios

Valid input Vcc R TH V OHMIN R line V IHMIN V drop I R IN Valid output Scenario 1: Source outputs logic high at lowest threshold, V OHMIN SINK SOURCE Valid input Vcc R THL V OLMAX R line V ILMAX R IN Valid output Scenario 2: Source outputs logic low at highest threshold, V OLMAX I SINK (c) Lucien Ngalamou SOURCE 17

DC Loading



The output high and low limits are exceeded only if a device output is heavily loaded. Logic device loading is specified by

 

maximum current Fanout := max. number of similar devices that can be connected to a load without exceeding high and low state current limits

Current Specs

IOHMAX IOLMAX IIHMAX IILMAX Max source current for which VOH



VOHMIN (valid output high) Max sink current for which VOL



VOLMAX (valid output low) Max input current for VIH



VIHMIN (valid input high) Max input current for which VIL



VILMAX (valid input low)

Valid input Valid input Vo > V OHMIN Vo < V OLMAX

DC Loading: Current specs

Io < IOHMAX Io < I OLMAX I IHMAX1 I IHMAXn n I ILMAX1 1 1 

Scenario 1: Output high connected to more than one sink. The current outputted by the source increases with the number of sinks.

I o =



I inj = nI in (for n similar sinks)



Scenario 2: Output low connected to more than one sink. Note that the current now flows into the output terminal (logic source becomes a current sink). Again current increases with the number of logic sinks. I o =



I inj = nI in (for n similar sinks)

I ILMAXn n (c) Lucien Ngalamou 19

DC Loading: Fanout



Each gate input requires a certain amount of current to maintain it in the LOW state or in the HIGH state.

 

I IL and I IH These are specified by the manufacturer.

Fanout calculation

–Low state fanout, n low so that V o < V Flow OLMAX := maximum number of similar gates that can be driven –High state fanout, n high so that V o > V Fhigh OHMIN := maximum number of similar gates that can be driven –Need to do current loading calculation for non-gate loads (LEDs, termination resistors, etc.)

n Flow

   

I OL



max

driver IL driven

  

Fanout,

n F



min



n Flow

,

n Fhigh



n Fhigh

   

I OH



max

IH d river d riven

   (c) Lucien Ngalamou 20

2.9 AC Loading

  

All gate outputs have associated parasitic capacitances due to external wiring (including their gate pins) as well as internal semiconductor storage effects (junction capacitances). In addition there are parasitic capacitances associated with each gate input. Typically the capacitance component due to IC pins is of the order of 10-15pF. The final transistor which drives the gate output acts as an electronically controlled switch with a pull-up to Vcc.

Vcc Parasitic capacitance, Cp R Vo Switch closed: Vo = 0 Switch opens: with

charges to Vcc 

LH =RCp

Switch closes: with 

HL =rCp.

discharges through contact resistance,

, Contact resistance, r (c) Lucien Ngalamou 21

2.10 The Ideal Inverter



The ideal gate should have

   

infinite gain in the transition region a gate threshold located in the middle of the logic swing high and low noise margins equal to half the swing input and output impedances of infinity and zero, resp.

V out

g = -

 R i =  R o = 0 Fanout =  NM H = NM L = VDD/2 V in (c) Lucien Ngalamou 22

input waveform

V in V out

output waveform (c) Lucien Ngalamou

Delay Definitions

V in V out

50%

t pHL t f

50%

t pLH

Propagation delay

t p = (t pHL + t pLH )/2 t

90% signal slopes 10%

t t r

2.12 Modeling Propagation Delay



Model circuit as first-order RC network

R v out (t) = (1 – e –t/  )V where  = RC v out C v in Time to reach 50% point is t = ln(2)  = 0.69

 Time to reach 90% point is t = ln(9)  = 2.2

 

Matches the delay of an inverter gate

2.13 Power and Energy Dissipation



Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates

  

supply line sizing (determined by peak power ) P peak = V dd i peak battery lifetime (determined by average power dissipation ) p(t) = v(t)i(t) = V dd i(t) P avg = 1/T



p(t) dt = V dd /T



packaging and cooling requirements i dd (t) dt



Two important components: static and dynamic



Propagation delay and the power consumption of a gate are related



Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors

 

the faster the energy transfer (higher power dissipation) the faster the gate For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant



Power-delay product (PDP) event – energy consumed by the gate per switching



An ideal gate is one that is fast and consumes little energy, so the ultimate quality metric is



Energy-delay product (EDP)

3. CMOS Technology



The basic building blocks in CMOS logic circuits are MOSFET Transistors .



MOSFET transistors are further broken down into depletion type and enhancement type .



The terms depletion and enhancement define their basic mode of operation.

MOS Transistors (c) Lucien Ngalamou 29

Depletion-type MOSFET



The basic construction of an n-channel MOS is provided below:



Electronic Devices and Circuit Theory:9/e

Robert Boylestad

Figure 3.1. n-Channel depletion-type MOSFET

Basic Operation and Characteristics



Gate-to-source voltage = 0 (figure 3.2)



Results :



Attraction for the positive potential at the drain by the free electrons of the n-channel.



A current (I DSS ) is established between the drain and the source (figure 3.3.).

Electronic Devices and Circuit Theory:9/e

Robert Boylestad

Figure 3.2: n-channel depletion-type MOSFET with V GS an applied V DD = 0 and

Electronic Devices and Circuit Theory:9/e

Robert Boylestad

Figure 3.3: Drain and transfer characteristics for an n channel depletion-type MOSFET

Electronic Devices and Circuit Theory:9/e

Robert Boylestad

Figure 3.4: Reduction in free carries in channel due to a negative potential at the gate terminal



By applying a negative potential at the gate (V GS < 0), the electrons are pressured toward the p-type region substrate (charge repel) and the holes are attracted from the p-type substrate (opposite charge attraction) as shown in figure 3.4.



Depending on the magnitude of V GS , a level of recombination between electrons and holes will occur that will reduce the number of free electrons in the n-channel available for conduction.



The more VGS is negative, the higher the rate of recombination.



The resulting level of drain current is therefore reduced with increasing negative bias for VGS. The pinch-off level (V GS yields ID = 0.

= V P )



Positive values of VGS will draw additional electrons from p-type substrate, resulting in an increase of the drain current.



As the gate-source voltage continue to increase in the positive direction, Fig.3.3 reveals that the drain current will increase at a rapid rate.

P-channel depletion-type MOSFET



Its behavior and characteristics are reverse to those of an –channel MOSFET. Electronic Devices and Circuit Theory:9/e

Robert Boylestad

Figure 3.5: p-channel depletion-type MOSFET with I DSS

ad V P = + 6V = - 6 mA

Symbols

Electronic Devices and Circuit Theory:9/e

Robert Boylestad Fig. 3.6. Graphic symbols for (a) n-channel depletion-type MOSFETs and (b) p-channel depletion-type MOSFETs.

2N3797 Motorola n-channel depletion-type MOSFET.

Electronic Devices and Circuit Theory:9/e

Robert Boylestad (c) Lucien Ngalamou 39

Enhancement-type MOSFET



Inexistence of channels between the drain and the source.



V GS will allow or disallow the formation of a channel.

Electronic Devices and Circuit Theory:9/e

Robert Boylestad Fig. 3.7. n-Channel enhancement-type MOSFET.

Basic Operation and Charcteristics



V GS = 0 => no current (no channel)



As V GS increases in magnitude, the concentration of electrons near the SiO 2 surface increases until eventually the induced n-type region can support a measurable flow of current between the drain and the source.



The level of V GS that results in a significant increase in the current id called the threshold voltage V T or V GS(Th) .

Electronic Devices and Circuit Theory:9/e

Robert Boylestad (c) Lucien Ngalamou Fig. 3.8. Channel formation in the n-channel enhancement type MOSFET.



As V GS is increased beyond the threshold level, the density of free careers in the channel will increase, resulting in an increased level of a drain current.



If V GS is hold constant and increase the level of V DS , the drain current will eventually reach a saturation level. The levelling off of I D is due to a pinching-off process.

Electronic Devices and Circuit Theory:9/e

Robert Boylestad Fig. 3.9. Change in channel and depletion region with increasing level of VDS for a fixed value of VGS.

Electronic Devices and Circuit Theory:9/e

Robert Boylestad (c) Lucien Ngalamou

Symbols

Electronic Devices and Circuit Theory:9/e

Robert Boylestad (c) Lucien Ngalamou

Summary Table

Gate Source Drain Substrate (Body)

(a) NMOS transistor

V G V S V D

(b) Simplified symbol for an NMOS transistor NMOS transistor 47

Gate Drain Substrate (Body) V DD

(a) PMOS transistor

Source V G V S V D

(b) Simplified symbol for an PMOS transistor PMOS transistor 48

( from MIT’s Open Web Course)

Defining the CMOS Technology



Static complementary CMOS - except during switching, output connected to either V DD or GND via a low-resistance path

 

high noise margins

 

full rail to rail swing V OH and V OL are at V DD and GND, respectively low output impedance, high input impedance

  

no steady state path between V DD and GND ( no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions)



Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes



simpler, faster gates



increased sensitivity to noise

CMOS Circuit Topology

 Pull-up network (PUN) and pull-down network (PDN) V DD PMOS transistors only In 1 In 2 PUN pull-up: make a connection from V DD when F(In 1 ,In 2 ,…In N ) = 1 to F In N F(In 1 ,In 2 ,…In N ) In 1 In 2 In N PDN pull-down: make a connection from F to GND when F(In 1 ,In 2 ,…In N ) = 0 NMOS transistors only (c) Lucien Ngalamou PUN and PDN are dual logic networks 56

b) Dual PUN and PDN



PUN and PDN are dual networks



DeMorgan’s theorems

 

(A + B)’ = A’.B’ (A.B)’ = A’ + B’



a parallel connection of transistors in the PUN corresponds to a series connection of the PDN



Complementary gate is naturally inverting (NAND, NOR, NOT)



Number of transistors for an N-input logic gate is 2N

CMOS Complements (c) Lucien Ngalamou 58

Examples of CMOS Gates

V DD = 5V Vi 0(L) 5(H) Q1 OFF ON Q2 ON Vo 5(H) OFF 0(L) Q2 p-channel Vo Q1 n-channel

CMOS inverter

CMOS NAND



Use 2n transistors for n-input gate



p-channel in parallel, n-channel in series



Add output inverter to convert to AND

CMOS NOR



Like NAND -- 2n transistors for n-input gate



p-channel series, n-channels in parallel ( from Wakerly’s Text)

NAND vs NOR



For a given silicon area, PMOS transistors are have higher ON resistance than NMOS transistors => Output High voltage is lower due to series connection in NOR. ( from Wakerly’s Text)

NOR NAND •NAND output LOW voltage is not as badly compromised  Result: NAND gates are preferred in CMOS.

CMOS characteristics

 Essentially no DC current flow into MOS gate terminal 

Gate has capacitance, C which MUST be charged then discharged for switching

 Required power is C

PD V 2

f ; where f is switching frequency, C

dissipation capacitance is the power

 Very little (0(nA)) current in output chain, except during switching when both transistors

are partially on



More power required when signal rise times are small since transistors are on longer



Symmetric output structure ==> equally strong drive (I OH , I OL ) in LOW and HIGH states

Power dissipation in PCs increase with clock frequency 2.

There is a lot of research on low voltage logic devices (5V, now 3.3V common) 64

CMOS families and typical specifications

  

V OHMIN =V DD -0.1V, V IHMIN =0.7V

cc , V ILMAX =0.3V

DD , V OLMAX =0.1V



V DD



18V (original 4000 family), 2V



V DD Input source and leakage currents: <1





6V (newer HC family)



Output current: typically 4mA but can be as high as 24mA



Families: original 4000 family (slower, lower power dissip.)

 

74FAMnnn: FAM = family type, nnn=function number – faster



54FAMnnn: same as 74FAMnnn but for military apps.

 

FAM : HC (High Speed CMOS), HCT (HC TTL compatible), VHC/VHCT (Very High speed), FCT/FCT-T(Fast CMOS TTL compatible/ with TTL V OH ) Egs: 74HC04 – hex inverter. I OLMAX =20



A, I OHMAX =-20



NB: Special handling precautions hold as CMOS can be damaged by very a small electrostatic discharge

Synthesis

Transcript Synthesis

ECNG 1014: Digital Electronics Lecture 3: Technology

Topics

1. Introduction

2. Basic Operational Characteristics and Parameters

2.1. Logic Levels

2.2 Noise

2.3 Noise Immunity

2.4 Static Gate Behavior

2.5 DC Operation

2.6. Mapping Logic Levels to the Voltage Domain

2.7. Logic Levels: Practical Scenario

DC Loading

DC Loading: Current specs

DC Loading: Fanout

Fanout,

min

,

2.9 AC Loading

2.10 The Ideal Inverter

Delay Definitions

2.12 Modeling Propagation Delay

2.13 Power and Energy Dissipation

3. CMOS Technology

Depletion-type MOSFET

Basic Operation and Characteristics

P-channel depletion-type MOSFET

Symbols

Enhancement-type MOSFET

Basic Operation and Charcteristics

Symbols

Defining the CMOS Technology

CMOS Circuit Topology

b) Dual PUN and PDN

Examples of CMOS Gates

CMOS inverter

CMOS NAND

CMOS NOR

NAND vs NOR

CMOS characteristics

Directory