Transcript Reading and writing to data memory

Reading and Writing to
Data Memory

rs
Lw rt Imm(rs)
Imm
5
Register
file
16
Sign extend
32
Offset
Base address
+
Data address to data memory
Computer Engineering LoadStoreInstr page 1
Offset
Lw
rs
rt 4(rs)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Computer Engineering LoadStoreInstr page 2
Reading and Writing to
Data Memory

Lb rt Imm(rs)
Address (32 bits)
Data (8 bits)
Data memory
Sign extension
Lbu: Zero extend
There are also Lh and Lhu
Computer Engineering LoadStoreInstr page 3
Reading and Writing to
Data Memory

Sw rt Imm(rs)
Sh rt Imm(rs)
Sb rt Imm(rs)

Remember: Alignment for Sw and Sh


Computer Engineering LoadStoreInstr page 4
Read and Write From/ to the Data
Memory





Lw
Lh
Lhu
Lb
Lbu
rt Imm(rs)
rt Imm(rs)
rt Imm(rs)
rt Imm(rs)
rt Imm(rs)
Sw
Sh
rt Imm(rs)
rt Imm(rs)
Sb
rt Imm(rs)
Computer Engineering LoadStoreInstr page 5
Zero ext.
Branch
logic
0
A
ALU
4
B
+
Sgn/Ze
extend
31
+
Lw rt Imm(rs)
Computer Engineering LoadStoreInstr page 6
Zero ext.
Branch
logic
0
A
ALU
4
B
+
Sgn/Ze
extend
31
+
Lw rt Imm(rs)
Computer Engineering LoadStoreInstr page 7
Zero ext.
Branch
logic
0
A
ALU
4
B
+
Sgn/Ze
extend
31
Lw rt Imm(rs)
+
Read Data
Computer Engineering LoadStoreInstr page 8
Zero ext.
Branch
logic
0
A
ALU
4
B
+
Sgn/Ze
extend
31
+
Lw rt Imm(rs)
… next instr
Computer Engineering LoadStoreInstr page 9
Zero ext.
Branch
logic
0
A
ALU
4
B
+
Sgn/Ze
extend
31
+
Sw rt Imm(rs)
Computer Engineering LoadStoreInstr page 10
Zero ext.
Branch
logic
0
A
ALU
4
B
+
Sgn/Ze
extend
31
Sw rt Imm(rs)
+
Write Data
Computer Engineering LoadStoreInstr page 11