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Wojciech Dulinski
[email protected]
BNL/IReS/LEPSI STAR Video Conference, 5.02.2004
MIMOSA9 tracker test chip submission
Goals: design optimization for STAR microvertex application
1. Exploration of (new) fabrication process
2. Test of a new readout architecture
Status:
submitted 26 of January 04
expected in April 04
tests (including beam tests) in May-July 04
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Wojciech Dulinski
[email protected]
BNL/IReS/LEPSI STAR Video Conference, 5.02.2004
AMS 0.35 µm CMOS OPTO process
- Advanced mixed-signal polycide gate CMOS:
4 metal, 2 poly, high-resistive poly, 3.3V and 5V gates
- Optimized N-well diode leakage current:
<45 pA/mm2 (cm2???) @27 °C
- 20 µm epi substrate
(samples on non-epi high resistivity substrate also available)
- Availability in multiproject submissions in 2004, with a
reasonable pricing
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Wojciech Dulinski
[email protected]
BNL/IReS/LEPSI STAR Video Conference, 5.02.2004
MIMOSA9: 4 “standard” arrays for tracking performance study
and 5 test arrays with a new readout scheme (analog CDS on pixel)
Test arrays (on pixel CDS)
Dimensions: 4.1x4.3 mm2
Array#1
Array#2
Array#0
Array#3
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Wojciech Dulinski
[email protected]
BNL/IReS/LEPSI STAR Video Conference, 5.02.2004
Mimosa9: arrays for tracking study
vdd
vdd
reset
select
output
3 transistor
pixel cell
gnd
Type
Dimension
Pitch
N-well diode
size
Array#0
SB
64x64
20µm
4.3x3.4, 6x6
Array#1
3T
32x32
40µm
3.4x3.4*, 6x6
Array#2
SB
32x32
30µm
4.3x3.4, 5x5
Array#3
SB
32x32
40µm
4.3x3.4, 6x6
vdd
* “thin oxide diode”
vdd
select
POLY
output
N++
N-WELL
gnd
M1 plate
N++
P-WELL
P++
LOCOS
Self-biased
pixel cell
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Wojciech Dulinski
[email protected]
BNL/IReS/LEPSI STAR Video Conference, 5.02.2004
Analog CDS on pixel: possible way to limit the integration time,
effective use of a trigger)
S1
vbias
AVDD
Read1
pwr_on
output1
S2
Cs1
x(5-10)
AVDD
Read2
output2
Cs2
gnd
- Slow integration clock (1MHz  640 µs integration
time): low dissipation, comfortable stabilisation
time of the on-pixel amplifier after Power_On
- Readout of all pixels after trigger only: no need for
perfect internal readout chain compensation
- External compensation, global correction (common
mode) possible: limited risk for experimental
“unknown” factors
- Lower signal amplitude dispersion: less power,
smaller digitisation precision required (~8bits)
output1
output2
BUF
Out
Five different pixel arrays tested on Mimosa9 (array size 22x4 pixels for a pitch of 30µm)
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