Transcript Fractal Formosa

Fractal Technologies
45nm example2 library
Validation With Crossfire™
7/16/2015
Fractal Technologies
Confidential
Formats checked
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Formats of example2 library checked:
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Spice
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Verilog
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NLDM : 19 full databases
CCS : 14 full databases (ff, sf, fs, ss, and tt missing)
ECSM: 19 full databases
Every LEF has full technology
PLIB: 9 technology variants
GDSII
Cadence CDB: layout, schematic, symbol views
Milky Way
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7/16/2015
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LEF: 9 technology variants
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Component
Entities
Liberty
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2 files, 10 flavors
With/without pwr pins, TETRAMAX, NTC, RECREM
VHDL:
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Lpe_worst
spice
Colors used in this report:
• Black lines describe checks
• Green refers to checks passed successfully
• Red indicates checks that failed, potential library errors
Additional formats supported
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Documentation (html or pdf)
OpenAccess
Other ASCII based formats
SLIB
FastScan, atpg
Logicvision
CEL+FRAM
FRAM-only (FRAM supplied twice)
Quality in Design Formats
2
Cell-presence
•
Created cell lists used for presence checks:
– Schematics: 812 cells (Cells with a function, incl. TAPCELL)
– EXTRA: 15 cells (Functional cells, separately provided)
– FILLS: 13 cells (Filler cells)
– DCAPS: 20 cells (Decoupling cells)
– ISO: 8 cells
– LH Level Shifters: 8 cells
– HL Level Shifters: 4 cells
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Remarks:
– Technology defined in both std and EXTRA LEF file
– Milky Way FRAM views provided twice
– CCS misses 5 characterization corners (ff, sf, tt, ss and fs) present in
NLDM and ECSM
– ECSM corners in different locations (timing_power_noise and
signal_storm)
7/16/2015
Quality in Design Formats
3
Cell Presence Layout Databases
Schematics
Extra
Dcaps
Fills
LH-lvl-shift
HL-lvl-shift
Iso-cells
lef-xlm (9 databases)
812/812
15/15
20/20
13/13
8/8
4/4
8/8
plib-xlm (9 databases)
812/812
0/15
20/20
13/13
8/8
4/4
8/8
mw-CEL-cell_frame
812/812
0/15
20/20
13/13
8/8
4/4
8/8
mw-FRAM-cell_frame
812/812
0/15
20/20
13/13
8/8
4/4
8/8
mw-FRAM-frame_only
812/812
0/15
20/20
13/13
8/8
4/4
8/8
gdsii
812/812
15/15
20/20
13/13
8/8
4/4
8/8
cdb-layout
488/812
0/15
17/20
13/13
0/8
0/4
8/8
cdb-schematic
487/812
0/15
17/20
5/13
0/8
0/4
8/8
cdb-symbol
487/812
0/15
17/20
0/13
0/8
0/4
8/8
plib-xlm (9 databases)
812/812
0/15
20/20
13/13
8/8
4/4
8/8
CDB details, file transfer problem?
• Dcap cells missing: CAP16B DCAP32B DCAP64B
• Schematic: has only GFILL cells, no FILL* -> GFILL cells have no symbol!
• All views: cells from AN2 to LNSN, all cells from LNSN to OR4 are missing
• Layout: has LNSN cell but does not exist anywhere else
7/16/2015
Quality in Design Formats
4
Cell Presence Netlist and Behavior
Schematics
Extra
Dcaps
Fills
LH-lvl-shift
HL-lvl-shift
Iso-cells
Lpe_worst
93/812
0/15
0/20
0/13
0/8
0/4
0/8
spice
812/812
0/15
20/20
5/13
8/8
4/4
8/8
verilog
811/812
15/15
20/20
0/13
8/8
4/4
8/8
verilog-pwr
811/812
15/15
20/20
0/13
8/8
4/4
8/8
tetramax
811/812
15/15
20/20
0/13
8/8
4/4
8/8
All other Verilog flavours (10)
811/812
15/15
20/20
0/13
8/8
4/4
8/8
VHDL component + entity
811/812
15/15
20/20
0/13
8/8
4/4
8/8
Details:
• lpe-worst: file transfer problem? No .ends last subcircuit
• spice: only GFILL cells, no FILL cells
• Verilog, VHDL: no tapcell
7/16/2015
Quality in Design Formats
5
Cell Presence NLDM
Schematics
Extra
Dcaps
Fills
LH-lvl-shift
HL-lvl-shift
Iso-cells
nldm-bc
812/812
15/15
20/20
0/13
8/8
4/4
8/8
nldm-bc99
812/812
15/15
20/20
0/13
8/8
4/4
8/8
nldm-bc1.21-99
0/812
0/15
0/20
0/13
0/8
4/4
0/8
nldm-bc0.99-121
0/812
0/15
0/20
0/13
8/8
0/4
0/8
Lt, ml, tc, wc, wcl, wcz
812/812
15/15
20/20
0/13
8/8
4/4
8/8
nldm-tt
812/812
15/15
20/20
0/13
0/8
0/4
0/8
nldm-sf
812/812
15/15
20/20
0/13
0/8
0/4
0/8
nldm-ss
812/812
15/15
20/20
0/13
0/8
0/4
0/8
nldm-fs
812/812
15/15
20/20
0/13
0/8
0/4
0/8
nldm-ff
812/812
15/15
20/20
0/13
0/8
0/4
0/8
Structure of NDLM characterization corners
bc
bc 1.21-0.99
bc 0.99-0.99
bc 1.21-1.21
bc-EXTRA
7/16/2015
bc 0.99
bc 0.99 -1.21
Quality in Design Formats
bc-0.99 EXTRA
6
Cell Presence CCS & ECSM
• CCS corners identical to NLDM:
– -lt*, -ml*, -tc*, -wc*, -wcl*, -wcz*
• Missing CCS corners:
– tt, sf, fs, ss, and ff
• ECSM corners identical to NLDM:
– -lt*, -ml*, -tc*, -wc*, -wcl*, -wcz*, -tt*, -sf*, -fs*, -ss*, -ff*
• ECSM files are not in one place:
– Tt, sf, ss, fs and ff corners inside timing_power_noise
– All other ecsm files in signal_storm
7/16/2015
Quality in Design Formats
7
Hierarchy consistency
• All databases contain master cells for all instances:
– Cadence CDB, Milky Way, gdsII, spice, verilog, VHDL
• Exceptions:
– CDB schematic: ipin, opin, iopin, nch, pch, ndio symbol
views missing
7/16/2015
Quality in Design Formats
8
Terminals & Pins (1)
• Are the same pins defined in all formats?
– Golden Reference used: verilog
• Check passed all formats (except gdsII)
• CDB layout view has
BIDIRECTIONAL pins
instead of input/output
Example lib 2
Crossfire error visualization
7/16/2015
Quality in Design Formats
9
Terminals & Pins (2)
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Most pins are drawn in M1
– Applies to CDB, Milky Way, LEF, PLIB
– Exceptions having pins in M2:
NR2, DFCNQD1,
AI21, D3D2, ND2D4,
D2D3, D2D2, MUX2ND,
MUX2ND, MUX2D1, DFQD1,
DFCNQD
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Extra VDDL pin for LH level shifters
– No VDDH pin for HL level shifters?
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Antenna symbol/schematic has no VDD pin
– All other symbol views have additional VDD/VSS pins
Labels present in M1TXT or M2TXT
– Applies to CDB, MilkyWay CEL, and gdsII
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7/16/2015
Quality in Design Formats
10
Layout vs. layout
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Checks identity between polygons: layout-vs-layout or
abstract-vs-layout
– Performs Boolean mask XOR operations
– Detailed check example: Abstract vs Layout
• “11 0” in GDSII <= “M1” LEF
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GDSII M1, M2, VIA equals
– LEF
– PLIB
– MilkyWay cell-frame FRAM
– MilkyWay frame-only FRAM
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GDSII all layers equals:
– CDB-layout
– MilkyWay cell-frame CEL
7/16/2015
Interview showing PLIB, LEF, GDSII, CDB and MilkyWay
Quality in Design Formats
11
Abutment
• All cells checked for self-symmetry and left/right abutment
(alignment on cell-boundary) with reference cell (INVD):
• Check passed GDSII, all layers
• Example: Poly abutment error on
multi-pitch level-shifter LH cells
– Only, poly not e.g. nwell
7/16/2015
Quality in Design Formats
12
Routability (1)
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Checks if signal-pins can be routed to cellboundary
– Uses fast internal maze router
– Users select layers (e.g. M1 only) or special
rules (e.g. double-via’s on outputs of high-drive
cells)
– Technology settings (rules, vias, pitch) read
from LEF technology
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Results
– All cells are compatible for height and pitch
– Total checked 3951 pins, 880 cells
– 2666 routable in M1, 67% above average
(55%)
7/16/2015
Quality in Design Formats
13
Routability (2)
• Only 1 pin is only routable only in M3:
– Cell DFCNQD1, pin D
7/16/2015
Quality in Design Formats
14
Functional Equivalence
• Verified functional equivalence between Verilog, SPICE,
VHDL and Liberty
– Checks equivalence of Boolean expressions from different
databases
– For (schematics) & SPICE, expressions are automatically
extracted.
• Spice vs nldm: ok
• Verilog vs nldm: ok
• Tetramax vs Verilog: ok
7/16/2015
Crossfire feedback showing equations extracted from SPICE
Quality in Design Formats
15
Characterization
• Cross-checks arc-presence between Liberty, VHDL and
Verilog
• Sanity checks on characterized delay and power
numbers
• All NLDM delays increase with increasing output
capacitance
• SDF expressions equal Liberty when expressions
• Arc conditions are consistent (no redundant or conflicting
conditions)
7/16/2015
Quality in Design Formats
16
CCS Characterization (1)
• Many cells do not have a
single peak current (tc
corner)
Cell AN2, output_current_fall A2->Z
• Current curves generally
have a “correction current”
at the tail (tc corner)
Cell DFCND, output_current_rise CP->Q
7/16/2015
Quality in Design Formats
17
CCS Characterization (2)
• 86 Cells exhibit peak-current anomalies (tc corner)
– E.g. Cell AN3, rise current A3Z
– Curve for slew 0.02, cap=0.1739 has 50 samples instead of 10
Cell AN2, CCS peak currents
Cell AN2, CCS current curve
7/16/2015
Quality in Design Formats
18
CCS Characterization (3)
• More examples of CCS peak current anomalies (tc corner)
Cell NR4, CCS output_current_rise A4 -> ZN
7/16/2015
Cell MUX2, CCS output_current_rise S -> ZN
Quality in Design Formats
19
CCS Characterization (4)
• Tristate buffer cells use different capacitance values for
CCS and NLDM, e.g. :
– tc corner, cell BUFTD, cell_rise: I  Z
– CCS indices: [0.00164, 0.008240, 0.021430, 0.047820,
0.10060, 0.20610, 0.41720]
– NLDM indices: [0.0065720, 0.013170, 0.026360, 0.052750,
0.1055, 0.21110, 0.42220]
• CCS delays for tc corner are identical to NLDM delays
– 2%/0.01 tolerance values
7/16/2015
Quality in Design Formats
20
ECSM Characterization
• Many ECSM-curves have large deviations (20-300%) between ECSM
and NLDM delay values, e.g.:
– TC corner, cell AOI22D1, cell_fall: A1  ZN, index (1,1)
(cap=0.00045pf, slew=0.004)
– 33% deviation of delay value (0.01285 vs 0.0169)
Cell AOI22, CCS-NLDM deviation
Cell AOI22, clip from ECSM tc corner
7/16/2015
Quality in Design FormatsCell AN2, no CCS-NLDM deviation, typical
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Characterization Comparison
• Histogram plot of
cell-rise delays
– bc, tc and wc
corners
– Delay cells
excluded
7/16/2015
Quality in Design Formats
22
Conclusions
• Summary of inconsistencies detected:
– Structure
Technology defined in both std and EXTRA LEF file
Milky Way FRAM views provided twice
CCS misses 5 characterization corners (ff, sf, tt, ss and fs)
ECSM corners in different locations
– Presence
Missing EXTRA cells in MilkyWay, PLIB, spice
Level shifters missing from tt, sf, fs, ss, and ff
Incomplete CDB and lpe databases
– Characterization
CCS peak current anomalies in 86 cells
CCS capacitance values different for BUFT cells
ECSM vs NLDM mismatches
7/16/2015
Quality in Design Formats
23