Transcript OWS Business Review - IEEE Dallas Power Electronics Society

Digitally Controlled Power Supplies
Introduction and design considerations
David Figoli
Shamim Choudhury
Digital Power Systems
Texas Instruments
Houston
TEXAS INSTRUMENTS
Agenda




Technology Overview
Hardware
Software
Control Theory
TEXAS INSTRUMENTS
Scope of Digital Power Control
Telecom infrastructure
Base stations
Servers
Routers
Workstations
400KHz ~ 1MHz
Industrial






100KHz ~ 200KHz
85 ~ 265
VAC
F
I
L
T
E
R
DC/DC
POL
DC/DC
POL
200KHz ~ 500KHz
IBC
DC / DC
PFC
“Equipment”
Mother boards
48 VDC
6~14
VDC
DC/DC
POL
TEXAS INSTRUMENTS
Full Digital control system
0110101100
1011011101
0010100111
• Resolution
• Topology support
• “speed”
Digital
Controller
DAC
ADC
• MIPS “engine”
• “C” (HLL) Efficiency
• Data size (e.g. 16/32 bits?)
“Plant”
• Resolution
• Linearity / Accuracy
• Speed (sampling rate)
TEXAS INSTRUMENTS
Time sampled systems
Digital Controller

+
A-D
Control
Law
D-A
Ref
y(t)
y(n)
x(t)
Continuous
time signal
sample
period
T
x(n)
y(n)
y(t)
x(n)
x(t)
Discrete
time signal
TEXAS INSTRUMENTS
Time Division Multiplexing – TDM
(1/2)
y(n)
TSAMPLE
x(n)
Processor
Control Code
Control Code
Control
TEXAS INSTRUMENTS
Time Division Multiplexing – TDM
y(n)
(2/2)
TSAMPLE
x(n)
Processor 1
Control Code (C1)
Control Code
Control
Processor 2
Control Code (C2)
Control Code
Control
Processor 3
Control Code (C3)
Control Code
Control
Single CPU
C1
C2
C3
C1
C2
C3
C1
C2
C3
TEXAS INSTRUMENTS
F280x - Digital Controller engine
Code security
64Kw Flash +
Emulated EE
F280x
10Kw
RAM
EPWM x 6
4Kw
Boot
ROM
6 timers  6 phases
12 PWMs  12 x Vout
4 of 12  HiRes PWM
APWM x 4
XINTF
Memory Bus
100 MIPs C28xTM 32-bit DSP
32x32-bit
Multiplier
RMW
Atomic
ALU
32-bit
Timers (3)
Real-Time
JTAG
Peripheral Bus
Interrupt Management
ADC (12b)
GPIO
12 bit @ 12.5 MSPs
SCI x 2
CAN x 2
SPI x 4
32-bit
Register
File
4 timers  4 phases
4 PWMs  4 x Vout
PMBus
I2C
TEXAS INSTRUMENTS
PWM resources – F2808
Ext (optional)
SyncI
HR-PWM-1A
10 timebases
EPWM1
SyncO
EPWM-1B
SyncI
HR-PWM-2A
SyncI
APWM1
EPWM2
SyncO
EPWM-2B
SyncO
SyncI
HR-PWM-3A
SyncI
APWM2
EPWM3
SyncO
EPWM-3B
SyncO
SyncI
HR-PWM-4A
SyncI
APWM3
EPWM4
SyncO
EPWM-4B
SyncO
SyncI
EPWM-5A
SyncI
APWM2
EPWM5
SyncO
EPWM-5B
SyncO
SyncI
EPWM-6A
Future
expansion
APWM1
 10 independent freq.
 10 phase Interleaved
( 36o phase offset )
16 independent duty
APWM2
 16 Vout rails
 10 independent freq.
 4 with HiRes PWM
APWM3
Combinations
APWM4




1x6phase / 4xSingle
2x3phase / 4xSingle
3x3phase / 1xSingle
3x3phase / 7xSingle*
EPWM6
SyncO
Ext (optional)
EPWM-6B
Note: F2809 will have 6 HRPWM
TEXAS INSTRUMENTS
Example: AC/DC – Rectifier Control
VAC
IPRI
VRECT
VBOOST
VOUT
CT
F
I
L
T
E
R
APWM1
IPFC
1000W
F280x DSP based
2 phase interleaved PFC
Phase shifted ZVS-FB
200 KHz PWM (DC/DC)
100 KHz PWM (PFC)
EPWM2A
EPWM1B
EPWM2B
APWM2
Diode
clamp
Diode
clamp
IphA
•
•
•
•
•
•
EPWM1A
VOUT(P)
A
IphB
Primary Side Controller
A
D
C
F280x
Digital
Controller
I
O
P
W
M
C
O
M
M
S
I2C
CAN
SCI
SPI
TEXAS INSTRUMENTS
Example: DC/DC Control
Duty Cycle
2 pole
2 zero
CNTL
D1
2 pole
2 zero
CNTL
D2
2 pole
2 zero
CNTL
D3
EPWM1
1
1
EPWM2
2
2
EPWM3
3
3
2
4
Vout4
Vout3
Vin
1
Vout2
Vout1
GATE
DRV
2
3
4
Vout
Vin
2 pole
2 zero
CNTL
D4
2 pole
2 zero
CNTL
D
EPWM4
4
4
APWM1
1
1
GATE
DRV
2
2 pole
2 zero
CNTL
3
3
Vout
Vin
D
APWM2
2
1
APWM3
GATE
DRV
3
TEXAS INSTRUMENTS
A closer look ....
0110101100
1011011101
0010100111
• Resolution
• Topology support
Digital
Controller
DAC
ADC
• MIPS “engine”
• “C” Efficiency
• Data size (e.g. 32 bits)
“Plant”
• Resolution
• Linearity / Accuracy
• Speed (sampling rate)
TEXAS INSTRUMENTS
Processor consideration
Digital
Controller
TPWM
# Inst. vs Algorithm
PWM
S/W algorithm
CPU
Control Code spare Control Code spare
Control
# Instructions vs PWM
PWM freq.
(KHz)
50
100
200
250
300
500
750
1000
PWM per.
(uS)
20.0
10.0
5.0
4.0
3.3
2.0
1.3
1.0
Processor MIPS
40
100
150
800
2000
3000
400
1000
1500
200
500
750
160
400
600
133
333
500
80
200
300
53
133
200
40
100
150
clks
Controller
(2 pole / 2 zero)
25
Controller (3P/3Z)
29
PFC Current loop
48
IIR filter
23
PSFB (ZVS) PWM
driver
14
Multi-phase (N) IL
PWM driver.
7+2N
PFC2PHIL PWM
driver
26
MIPS = Million Instruction Per Second
TEXAS INSTRUMENTS
CPU Performance requirements
(1/2)
 ISR Bandwidth utilization = TISR / TSAMPLE * 100%
y(n)
TSAMPLE
TISR
x(n)
Interrupt
CPU
ISR
BG
CS ADC Ack
Loop1
ISR
Loop2
controller-1
Context Save +
Int latency
ADC service +
Int Ack
Operation
BG
ISR
Loop3
PWM
controller-3
DPWM
access
controller-2
CR
Context Restore +
Int Return
Context Save + Int. latency
ADC servicing + Ack
2P/2Z controller
DPWM access
Context Restore + Int. Return
# Clock Cycles
(1 loop)
16
4
25
4
16
# Clock Cycles
(2 loops)
16
5
47
8
16
# Clock Cycles
(3 loops)
16
6
69
12
16
Total
65
92
119
TEXAS INSTRUMENTS
CPU Performance requirements
(2/2)
ISR Utilization for PWM frequency vs # Control loops
CPU clk = 100 MHz
10 nS
PWM
# LOOPS & # Cycles
(KHz)
(uS)
200
300
400
500
600
700
800
900
1000
1100
5.00
3.33
2.50
2.00
1.67
1.43
1.25
1.11
1.00
0.91
1
65
13%
20%
26%
33%
39%
46%
52%
59%
65%
72%
2
92
18%
28%
37%
46%
55%
64%
74%
83%
92%
101%
3
119
24%
36%
48%
60%
71%
83%
95%
107%
119%
131%
4
146
29%
44%
58%
73%
88%
102%
117%
131%
146%
161%
5
173
35%
52%
69%
87%
104%
121%
138%
156%
173%
190%
Note: Entries in red require more than 100% and are not possible.
TEXAS INSTRUMENTS
ADC
ADC consideration
ADC utilization - # Channels (“Loops”) vs PWM freq.
MSPS = 3
PWM
# Channels
(KHz)
125
24
250
12
500
6
750
4
1000
3
MSPS = 6.25
PWM
# Channels
(KHz)
125
50
250
25
500
13
750
8
1000
6
MSPS = 12.5
PWM
# Channels
(KHz)
125
100
250
50
500
25
750
16.7
1000
12.5
( Note: 12.5 MSPS = 80 nS conversion )
TEXAS INSTRUMENTS
Example: ADC capability of F280x
ChA1
ChA2
ChA3
M
U
X
S/H
“A”
ChA7
ChB1
ChB2
ChB3
Result
registers
ADC
M
U
X
Result 0
Result 1
Result 2
Sequencer
S/H
“B”
Result 7
Result 8
ChB7
Result 14
Result 15
F280x – on chip ADC
A D C
• 12 bit resolution / Pipeline architecture / Dual S/H
• up to 12.5 MSPS / 80 nS conversion
• 16 Analog channels
• Programmable S/H apperture window
• Start of Conversion (SOC) trigger via PWM timer
• SNR = 67dB / THD = -74dB
• DNL = +/- 1LSB, INL = +/- 1.5LSB, Offset = +/- 4LSB
TEXAS INSTRUMENTS
PWM consideration
DAC
V
TPWM
PWM
TSysclk
VSTEP
t
t
PWM resolution = Log2 ( TPWM / TSysClk )
280x PWM
PWM Freq
(KHz)
200
250
300
500
750
1000
1500
2000
Regular resolution
(bits)
(%)
9.0
0.2
8.6
0.3
8.4
0.3
7.6
0.5
7.1
0.8
6.6
1.0
6.1
1.5
5.6
2.0
High resolution
(bits)
(%)
15.0
0.003
14.7
0.004
14.4
0.005
13.7
0.008
13.1
0.011
12.7
0.015
12.1
0.023
11.7
0.030
TEXAS INSTRUMENTS
Example: Regular vs High Res PWM
280x System Clock = 100 MHz
PWM freq = 10 MHz
Period = 10 clocks
(i.e. 10 step resolution)
Hi-Resolution
PWM
300 mV
Voltage resolution = 3.3V/10
= ~300mV
Conventional
PWM
Voltage output shown as ramp function
TEXAS INSTRUMENTS
Limit Cycle Oscillation in Digital Power Converter
Vo levels (DPWM duty
ADC levels
ratio steps)
Volt
ΔVc
Vref
ΔVs
ΔVs
ΔVc
steady state output,
limit cycle
Volt
Vref
Vo levels (DPWM duty ADC levels
ratio steps)
ΔVc
ΔVs
ΔVs
error bins
+0010
+0001
0000
-0001
time
error bins
+0010
+0001
0000
-0001
steady state output,
no limit cycle
time
TEXAS INSTRUMENTS
Example: Closed loop HiRes PWM
Watch Window
Vref
HR
BUCK
DRV
Voltage
Controller
Vref
CNTL
2P2Z
Ref
FB
Uout
DutyCmd
H
W
Duty
Single Power Stage
E
P
W
M
Vin1
EPWMnA
DRV
Vout1
Buck
1 MHz
DutyCmd
1 MHz
ADC
1CH
DRV
Vout
A
D
C
H
W
rslt0
Ch0
1 MHz
HiRes (150pS) PWM
Regular (10nS) PWM
TEXAS INSTRUMENTS
Example: HiRes PWM – a closer look
Non-HiRes
HiRes
TEXAS INSTRUMENTS
Resolution loss - low duty utilization
TPWM
Max Duty
PWM
Not Utilized
t
TSYSCL (10 nS)
Vout
0.8
Vin
14
12
10
9
8
7
6
1
1.2
1.8
2.5
3.3
5
3.0
2.7
2.5
2.3
2.2
2.0
1.7
2.5
2.3
2.0
1.8
1.7
1.5
1.3
2.1
1.9
1.6
1.4
1.3
1.1
0.9
1.5
1.3
1.0
0.8
0.7
0.5
0.3
Resolution Loss in bits
4.1
3.9
3.6
3.5
3.3
3.1
2.9
3.8
3.6
3.3
3.2
3.0
2.8
2.6
3.5
3.3
3.1
2.9
2.7
2.5
2.3
TEXAS INSTRUMENTS
Hardware ...
TEXAS INSTRUMENTS
AC/DC - Rectifier
VAC
IPRI
VRECT
VBOOST
VOUT
CT
F
I
L
T
E
R
APWM1
IPFC
1000W
F280x DSP based
2 phase interleaved PFC
Phase shifted ZVS-FB
200 KHz PWM (DC/DC)
100 KHz PWM (PFC)
EPWM2A
EPWM1B
EPWM2B
APWM2
Diode
clamp
Diode
clamp
IphA
•
•
•
•
•
•
EPWM1A
VOUT(P)
A
IphB
Primary Side Controller
A
D
C
F280x
Digital
Controller
I
O
P
W
M
C
O
M
M
S
I2C
CAN
SCI
SPI
TEXAS INSTRUMENTS
Common & Diff. mode filter
1
P FC_IN
1
4
2
3
2
3
P FC_RE T
4
1
3
5
2
1
2
2
A C-N
1
RELAY -C NTL
( GPIO )
3
+12V
P RI
In-Rush Relay
TEXAS INSTRUMENTS
1
2
1
+
+
P RI
P RI
+3V 3 +3V 3
P FC_IN
IPFC
1
P FC_RE T
1
V -B OOST
1
2
2
2
1
Interleaved Boost Converter
2
I-PHA -SENSE
( ADC-INA? )
1
P FC_IS E NS E
2
+3V 3 +3V 3
2
2
P FC_IS E NS E _GND
1
3
P RI
PWM
PFC
P RI
+12V
2
PFC- A ( APWM1 )
3
PFC- B ( APWM2 )
5
I-LIM- FLAG ( GPIO )
6
I-PFC- SET
( EPWM3A )
7
1
14
3V 3-out
V DD
P V DD
IN1
OUT1
IN2
OUT2
13
12
1
P RI
11
P RI
10
P RI
CLF
I-LIM
N/C
N/C
I-S E NS E
P GND
A GND
3
U7
I-PHB- SENSE
( ADC-INA? )
1
2
2
P FC_IS E NS E
8
P RI
IPHA & B
9
4
UCD7201
P RI
P RI
TEXAS INSTRUMENTS
Phase Shifted Full Bridge
+3V 3
IDCDC
I-D C D C - SEN SE
( ADC-INA? )
2
8
5
1
P RI
4
1
V B OOS T
V OUT
1
OUT-LS
2
1
2
1
P RI
P RI
R-HS
SEC
R-LS
HCNR200
EN
1
( GPIO )
OUT-HS
IN-LS
5
HCNR200
+
-
3
2
1
3
V - OU T- SEN SE
( ADC-INA? )
2
P RI
2
2
2
VOUT
3
1
PWM
PSFB
+
FB -E N
IN-HS
3
FB- R LS (EPWM2B)
4
1
3
1
FB- R HS (EPWM2A)
8
2
2
EN
FB gate dri ve2_2
1
1
1
L-LS
2
OUT-LS
L-HS
1
OUT-HS
IN-LS
2
IN-HS
3
( EPWM1B )
-
FB- LLS
3
FB- LH S ( EPWM1A )
2
2
FB gate dri ve1_2
HCNR200
SEC
TEXAS INSTRUMENTS
Signal Conditioning / DSP Interface
F280x
V- AC- SENSE
P FC_IN
UCD9501 / 2801 - P artial view
V- AC- SENSE
+3V 3
V- PFC- SENSE
+
3
I-DCDC
-
2
I-PFC- SENSE
+2V 5_Ref
A C-N
3
2
I-PHA -SENSE
+
I-PHB- SENSE
-
Comparator
I-D CDC- SENSE
I-DCDC-S E T
+5V
V- OUT- SENSE
( EPWM3B )
+2V 5_Ref
P RI
A DCIN-A 1
E P WM1B
A DCIN-A 2
E P WM2A
A DCIN-A 3
E P WM2B
A DCIN-A 5
E P WM3A
A DCIN-A 6
E P WM3B
A P WM1
P RI
A P WM2
P RI
FB- LH S
FB- LLS
FB- RHS
FB- RLS
A DCIN-A 4
A DCIN-B 0
+
3
E P WM1A
A DCIN-A 7
-
2
A DCIN-A 0
I-PFC- SET
I-D CDC- SET
PFC- A
PFC- B
A DCIN-B 1
P RI
+3V 3
A DCIN-B 2
GP IO
A DCIN-B 3
GP IO
RELAY -C NTL
I-LIM- FLG
A DCIN-B 4
V -B OOS T
A DCIN-B 5
V- PFC- SENSE
A DCIN-B 7
3
+
+
3
3
I-D CDC- TRIP
-
2
2
I-P FC-GND
A DCIN-B 6
I-PFC- SENSE
I-P FC
2
+2V 5_Ref
+
-
V- PFC- TRIP
Comparator
TZ1 (trip zone)
TZ2
TZ3
TZ4
P RI
P RI
<V alue>
V -P FC-S E T
(partial view)
P RI
P RI
P RI
TEXAS INSTRUMENTS
F280x “Life support”
A DCIN-A 0
A DCIN-A 1
A DCIN-A 2
A DCIN-A 3
A DCIN-A 4
A DCIN-A 5
A DCIN-A 6
A DCIN-A 7
A D0
3V 3
U12
23
22
21
20
19
18
17
16
27
28
29
30
31
32
33
34
3V 3
5
2
5
2
V CC
GND
V CC
GND
CLMP1
CLMP2
CLMP3
CLMP4
CLMP1
CLMP2
CLMP3
CLMP4
NUP 420MR6
4
6
3
1
4
6
3
1
A D0
2u2
2u2
22K 1, 1%
37
36
38
24
35
100n
E P WM1A
E P WM1B
E P WM2A
E P WM2B
E P WM3A
E P WM3B
E P WM4A
E P WM4B
E P WM5A
E P WM5B
E P WM6A
E P WM6B
TZ1
TZ2
TZ3
TZ4
47
44
45
48
51
53
56
58
60
61
64
70
1
95
8
9
S P I-SIMO
S P I-SOMI
S P I-CLK
GP IO-19
GP IO-20
GP IO-21
GP IO-22
GP IO-23
A P WM1
A P WM2
A P WM3
A P WM4
S CI-RX
S CI-TX
CA N-RX
CA N-TX
50
52
54
57
63
67
71
72
83
91
99
79
92
4
6
7
S DA
S CL
GP IO-34
10 x 0.1uF ceramic
3V 3
100
5
43
A DCIN-A 0
A DCIN-A 1
A DCIN-A 2
A DCIN-A 3
A DCIN-A 4
A DCIN-A 5
A DCIN-A 6
A DCIN-A 7
A DCIN-B 0
A DCIN-B 1
A DCIN-B 2
A DCIN-B 3
A DCIN-B 4
A DCIN-B 5
A DCIN-B 6
A DCIN-B 7
Flash V DD3V FL
3V3
I/O
1V8
Core
A DC-RE FP
A DC-RE FM
A DC-RE S E X T
A DC-LO
A DC-RE FIN
GP IO-00
GP IO-01
GP IO-02
GP IO-03
GP IO-04
GP IO-05
GP IO-06
GP IO-07
GP IO-08
GP IO-09
GP IO-10
GP IO-11
GP IO-12
GP IO-13
GP IO-14
GP IO-15
GP IO-16
GP IO-17
GP IO-18
GP IO-19
GP IO-20
GP IO-21
GP IO-22
GP IO-23
GP IO-24
GP IO-25
GP IO-26
GP IO-27
GP IO-28
GP IO-29
GP IO-30
GP IO-31
GP IO-32
GP IO-33
GP IO-34
TMS 320F2808P Z
V DDIO1
V DDIO2
V DDIO3
V DDIO4
V DD2
V DD3
V DD4
V DD5
V DD6
V DD7
X RS n
X1
X2
X CLKIN
X CLKOUT
TE S T1
TE S T2
TRS Tn
TCK
TMS
TDI
TDO
E MU0
E MU1
V DDA IO
V S S A IO
V DD1A 18
V DD2A 18
V S S 1A GND
V S S 2A GND
V DDA 2
VSSA2
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
V S S 10
V S S 11
V S S 12
96
3
46
65
82
50uH
50uH
50uH
50uH
10
42
59
68
85
93
50uH
50uH
50uH
50uH
50uH
50uH
78
1V 8
RE S E T
88
86
90
66
1M
97
98
30MHz
33p
84
75
74
73
76
80
81
33p
3V 3
26
25
12
40
13
39
15
14
1V 8A
50uH
50uH
50uH
+
+
4u7
2
11
41
49
55
62
69
77
87
89
94
4u7
1V 8
U8
V in(5V )
1
8
10
6
0.1u
5
0.01u
V in
E n2
E n1
NR
GND
2.2u
V out1
V out2
Reset
FB 2
NC
TP S 71319
1V 8A
50uH
3
4
3V 3
2
7
9
2.2u
0.01u
RE S E T
TEXAS INSTRUMENTS
BH2808 Contoller board
F2808 DSP controller board
• “battle hardened” design for harsh electrical environments
• DIMM 100 pin format
• Isolated SCI Interface
• JTAG port for real-time debug
• Dimensions – 1.4” x 3.5” (35 x 89 mm)
TEXAS INSTRUMENTS
Actual System hardware
Bridge
Rect.
Con.
Inductor 1
PFC
Phase 2
PFC
Phase 1
FET+Diode
Inductor 2
In-rush
relay
Full Bridge
Left-leg
Full Bridge
Right-leg
Res.
Ind.
Common / Diff mode
chokes
Output
diodes
Isolation
transformer
DC bus
Caps
(900uF)
Output
diodes
Output Ind.
DSP
controller
Voltage
Feedback
opto
Output
Caps
TEXAS INSTRUMENTS
Multi-phase / Output DC/DC
Duty Cycle
2 pole
2 zero
CNTL
D1
2 pole
2 zero
CNTL
D2
2 pole
2 zero
CNTL
D3
EPWM1
1
1
EPWM2
2
2
EPWM3
3
3
2
4
Vout4
Vout3
Vin
1
Vout2
Vout1
GATE
DRV
2
3
4
Vout
Vin
2 pole
2 zero
CNTL
D4
2 pole
2 zero
CNTL
D
EPWM4
4
4
APWM1
1
1
GATE
DRV
2
2 pole
2 zero
CNTL
3
3
Vout
Vin
D
APWM2
2
1
APWM3
GATE
DRV
3
TEXAS INSTRUMENTS
DC/DC ...more details
F2808
ILim_set-1
ILim_set-2
10 bit
DAC
8-Ch
SPI-DO
SPI-DI
SPI-CLK
EPWM1A
EPWM2A
Bot. FET
Bias Gen.
EPWM6A
PWM6
ADCIN-A0
ADCIN-A1
VOUT-1
VOUT-2
ADCIN-A5
VOUT-6
ADCIN-B0
ADCIN-B1
IPHS-1
IPHS-2
ADCIN-B5
Analog
MUX
ADCIN-B6
GPIO
GPIO
VTEMP-1
VTEMP-2
IPHS-6
Enable-1
Enable-2
GPIO
Enable-6
GPIO
GPIO
Fault-1
Fault-2
GPIO
Fault-6
Vin2
(5~12v)
ILim_set-6
Top FET
Bias Gen.
PWM1
PWM2
Vin1
(5~12v)
PWM1
VOUT-1
IPHS-1
VTEMP-1
Fault-1
Enable-1
ILim_set-1
PWM2
VOUT-2
IPHS-2
VTEMP-2
Fault-2
Enable-2
ILim_set-2
Top Bot.
Bias Bias
8A Sync Buck Stage
1
8A Sync Buck Stage
2
VOUT1
VOUT2
VTEMP-6
Vin1
Vin2
PWM3
VOUT-6
IPHS-6
VTEMP-6
Fault-6
Enable-6
ILim_set-6
8A Sync Buck Stage
6
VOUT6
TEXAS INSTRUMENTS
The Power stage
8A Synchronous Buck power stage
Vin
(5~12v)
Fault
Top Bias
Bot. Bias
Circuit
Breaker
Logic
PWM
Enable
UCD7230
Digital Control
Gate Driver
VOUT
8A
max
ILim_set
Ret
IPHS
VTEMP
Vout
Temp
sensor
Diff Amp
TEXAS INSTRUMENTS
UCD7230 gate driver
TEXAS INSTRUMENTS
6 ch power EVM + 2808 ezDSP
TEXAS INSTRUMENTS
Software ...
TEXAS INSTRUMENTS
Software Framework for a Digital Controller
“infrastructure which supports the application”
Considerations
 How many ISRs (Interrupt Service Routines)
 Are ISRs Synchronous or Asynchronous ?
 CPU % utilization balance between ISRs and Background (BG)
 High level language (HLL), e.g. “C/C++”, Assembly ?, or both ?
 Need to employ an Operating system ?
 Interrupt driven Communications ?
TEXAS INSTRUMENTS
The simple “ISR / BG” Framework
(1/2)
“keep it simple”
BG loop
ISR
Context Save
 2 Loops only
 ISR code has highest priority
 ISR Synchronous to PWM switching
 ISR incurs entry/exit overhead
 BG runs only during ISR “idle time”
ISR body
Context
Restore
TEXAS INSTRUMENTS
The simple “ISR / BG” Framework
(2/2)
PWM
t
Interrupt
ISR
base
TS1
Back
Ground
idle
time
BG
base
TS2
idle
time
base
TS3
BG
base
BG
TS4
base
BG
Time-slice
Tsample
 Can Time slice the ISR for simple synchronous multi-task scheduling
 In a practical system BG needs approx 15~20% of CPU bandwidth
 If CPU timing is “tight” may consider using a H/W accelerated controller
TEXAS INSTRUMENTS
Single ISR / BG loop example
Main
ISR
400 KHz
Initialisation
Execute every ISR call
fast Vloop or ILoop
Device level (CPU, PLL,..)
Peripheral level (ADC, PWM...)
System level (GPIO, Comms)
Time Slice
manager
Framework (BG / ISR)
Interrupts
100 KHz
Background loop
Startup / Shutdown / sequencing
TS1
loop1
100 KHz
100 KHz
TS2
loop2
TS3
filtering
100 KHz
TS4
OVP mgr
Margining
Diagnostics / Reporting / Comms
Fault management
Slow control loops
Return
TEXAS INSTRUMENTS
Time Sliced ISR – Practical example
Interrupt
TS1
TS2
I V I V
(200KHz) 1 1 2 2
I V
1 1
ISR
Back
Ground
B
G
I
Pfc
TS3
I V I V
1 1 2 2
I
bal
TS4
I V
1 1
1/
x2
B
G
I
cmd
(1/2)
TS1
I V I
1 1 2
RA
B
G
t
B
G
5000 nS
Code Function
PWM rate
(KHz)
Code execution
rate (KHz)
Identifier
DC/DC-1 V Loop
200
200
V1
DC/DC-1 I Loop
200
200
I1
DC/DC-2 V Loop
200
100
V2
DC/DC-2 I Loop
200
100
I2
PFC I loop
100
50
IPfc
PFC V loop (done in BG)
50
VPfc
PFC 1/X2 (X=Vac Rect &
Avg)
50
1/X2
PFC I-cmd (V1*V2*V3)
50
Icmd
PFC Vac Rect. and Average
50
RA
PFC I-balance
50
Ibal
TEXAS INSTRUMENTS
Time Sliced ISR – Practical example
TS1
Interrupt
ISR
(600KHz)
B1
B2
TS2
B3
Back
Ground
B1
B
G
B2
TS3
B4
B1
B2
B
G
TS4
B5
B1
B2
(2/2)
TS1
B1
spare
B
G
B2
t
B3
B
G
1667 nS
Code Function
PWM rate (KHz)
Code execution rate
(KHz)
Identifier
Buck 1 - single phase V Loop
600
600
B1
Buck 2 - single phase V Loop
600
600
B2
Buck 3 - 4-phase IL V Loop
300 / phase (90o apart)
150
B3
Buck 4 - 3-phase IL V Loop
300 / phase (120o apart)
150
B4
Buck 5 - 3-phase IL V Loop
300 / phase (120o apart)
150
B5
TEXAS INSTRUMENTS
Hardware Accelerated Controllers
F280x
DSP
32 bit core
50~100
MHz
(1/2)
UCD9110
Ch1
ADC
Ch1
Ch2
12 bit
(80nS)
MCU
ADC
16 bit core
4 MHz
12 bit
(5 uS)
Ch2
Ch16
DPWM1
DPWM2
DPWM3
PWM1A
PWM1B
Ch8
EA+
EA-
EADC
CLA
DPWM1
PWM2A
PWM2B
PWM3A
Error ADC
5 bit
(~300 nS)
DPWM2
PWM1A
PWM1B
PWM2A
PWM2B
PWM3B
Accelerated Controller
DPWM8
Non-Accelerated Controller
PWM8A
PWM8B
Note: CLA = Control Law Accelerator
TEXAS INSTRUMENTS
Hardware Accelerated Controllers
Interrupt
CLA1
t
TC1
C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1
ISR
C2
(2/2)
C3
C2
Background
C3
BG
C2
BG
UCD9110 example
with CLA
Note: a 3 execution
thread system.
Tsample
t
Interrupt
ISR
C1
C2
Background
C1
BG
C1
BG
C3
C1
BG
C1
F2801 example #1
Time-sliced ISR for
slow loops C2, C3
C2
BG
TC1
t
Interrupt
ISR
Background
C1
C1
C2 / C3 / BG
TC1
C1
C2 / C3 / BG
C1
C2 / C3 / BG
C1
C2 / C3 / BG
C2, C3 rate
scheduled
by BG code
F2801 example #2
BG managed slow
loops C2, C3
TEXAS INSTRUMENTS
Code development strategy
 Modularity - blocks with well defined inputs / outputs
(“cause and effect”)
 Multiple Instancing - use of same function (module) many times
 Peripheral (h/w) drivers - separate core code from peripheral code
 Re-useable / Re-targetable - maximize return on investment
 Efficiency & high performance - code execution in minimal time
TEXAS INSTRUMENTS
Software Library approach
CNTL
2P2Z
CNTL
3P3Z
Ref
Ref
Uout
FB
IIR-FILT
2P2Z
FB
E
P
W
M
Duty
H
W
Uout
IIR-FILT
3P3Z
f
BUCK
DRV
MPIL
DRV
f
E
P
W
M
HR
BUCK
DRV
E
P
W
M
Duty
H
W
EPWMnA
EPWMnB
EPWM1A
EPWM1B
EPWM2A
MPIL
BAL
DRV
E
P
W
M
EPWM2B
In
Out
In
Out
Duty
SinGen1
Freq
Out
Offset
Gain
Out
Duty
SLEW
LIMIT
In
In
HHB
DRV
Offset
INV
SQR
Out
ZVS
FB
DRV
Out
Incr
SSartSEQ
Llegdb
Rlegdb
H
W
E
P
W
M
H
W
Freq
Gain
Offset
Out
BalAdj
Delay
Slope
Out
ADC
DRV
Target
Rslt
PFC
2PHIL
DRV
E
P
W
M
Phase
RampGen
EPWM1B
EPWM2A
H
W
SGenHP1
Freq
Gain
EPWM1A
EPWM2B
Duty
H
W
EPWMnA
A
D
C
EPWMnA
Duty
EPWMnB
Adj
EPWMnA
PWM
DAC
DRV
EPWMnB
EPWM(n+1)A
EPWM(n+1)B
In1
In2
E
P
W
M
H
W
EPWMnA
EPWMnB
E
P
W
M
H
W
EPWMnA
EPWMnB
Ch0
Ch1
Ch3
Ch4
H
W
TEXAS INSTRUMENTS
Modular s/w architecture
“Signal Net” based module connectivity
Net1
Net2
In1A
f1
Out1
In1B
Net6
f2
Net3
Net5
In2A
Net7
Out2
f3
Net4
In3A
In4A
In4B
f4
Out4
Net8
In4C
f5
In5A
Out5
Net9
Out3
Initialization time (“C”)
Run time (ASM macros)
// pointer & Net declarations
Int *In1A, *In1B, *Out1, *In2A,...
Int Net1, Net2, Net3, Net4,...
; Execute the code
// “connect” the modules
In1A=&Net1; In1B=&Net2; Out1=&Net5;
In2A=&Net3; Out2=&Net6;
In3A=&Net4; Out3=&Net7;
In4A=&Net5; In4B=&Net6; In4C=&Net7; Out4=&Net8;
In5A=&Net7; Out5=&Net9;
f1
f2
f3
f4
f5
TEXAS INSTRUMENTS
PFC (2PHIL) Software control flow
VpfcSetSlewed
1 KHz
VpfcSet
VpfcSlewRate
In
Out
Incr
VpfcOvp
100 KHz
1 KHz
SLEW
LIMIT
385 V
VpfcCntl
CNTL
2P2Z
Ref
PFC
ICMD
PFC
OVP
Out
In
CNTL
2P2Z
Out
Ref
PfcIcmd
V2
Voltage
Controller
PFC
2PHIL
DRV
100 KHz
V1
Out
Fdbk
Vmon
2
100 KHz
100 KHz
Out
PfcDuty
E
V
H
W
Duty
Fdbk
T2PWM
T4PWM
Adj
Vac
Current
Controller
Vboost
Vboost
PfcShareAdj
VpfcSet
InvVavgSqr
Ipfc
385 V
50 KHz
160 V
50 KHz
200 KHz
200 KHz
AC
LINE
RECT
FILT
2P2Z
FILT
BIQUAD
INV
SQR
50mS
Out
In
Out
In
Out
In
Out
200 KHz
Ipfc
Vboost
In
VacLine
rslt0
rslt1
rslt2
rslt3
Vavg
VacLineAvg
VacLineRect
IN0
ADC
SEQ1
DRV
VacLineFilt
rslt4
BOX
CAR
AVG
IphA
100 Hz
IpfcAvgA
PFC
ISHARE
PfcShareAdj
Out
In
BOX
CAR
AVG
Ia
Ib
Out
IpfcAvgB
Out
50 KHz
In
rslt5
A
D
C
H
W
IN1
IN2
IN3
IN4
IN5
IpfcPhaseA
HalfVref
50 KHz
IpfcPhaseB
IphB
TEXAS INSTRUMENTS
DC-DC (PSFB) Software control flow
“ON”
200 KHz
200 KHz
SLEW
LIMIT
48 V
2
VoutSet
In
VoutSlewRate
Incr
200 KHz
VoutSetSlewed
CNTL
2P2Z
Ref
Out
Out
Voltage
Controller
VdcCntl
Fdbk
Vout
ZVS
FB
DRV
200 KHz
I_FOLD
BACK
V
Out
phase
ZvsPhaseCntl
I
50KHz
Rv
VoutSet
Fv
48 V
Ri
ZVS
DB
DRV
Fi
CNTL
2P2Z
0V
100mS
12 A
IoutSet
Ipri
Ref
Fdbk
Out
GPIO
DCDC_Enable
200 nS
ZvsDbAdjL
llegdb
180 nS
ZvsDbAdjR
rlegdb
PWM1
PWM2
PWM7
E
V
PWM8
G
P
I
O
C
N
T
L
PWM1
PWM2
PWM7
PWM8
H
W
IdcCntl
200 KHz
200 KHz
Current Controller
Ipri
Ipri
rslt0
Vout
Vout
rslt1
ADC
SEQ2
DRV
A
D
C
IN0
H
W
IN1
TEXAS INSTRUMENTS
Multi-output DC s/w management
Start / Stop trigger
Voltage
Controller
S-start / SEQ
Vref1
BUCK
DRV
CNTL
2P2Z
Ref
Uout
DutyCmd1
FB
Duty
Single Power Stage
E
P
W
M
H
W
Vin
EPWM1A
Vout1
DRV
Buck
400 KHz
1 MHz
ADC
DRV
Vout1
rslt0
A
D
C
H
W
Ch0
400 KHz
Voltage
Controller
S-start / SEQ
Vref2
BUCK
DRV
CNTL
2P2Z
Ref
Uout
DutyCmd2
FB
Duty
Single Power Stage
E
P
W
M
H
W
Vin
EPWM1A
Vout2
DRV
Buck
400 KHz
1 MHz
ADC
DRV
Vout2
rslt0
A
D
C
H
W
Ch1
400 KHz
TEXAS INSTRUMENTS
Soft-start & Sequencing multi Vout
TEXAS INSTRUMENTS
Multi-Phase IL s/w management
+/+/+/+/-
Start / Stop trigger
Adj
Adj
Adj
Adj
1
2
3
4
MPIL
DRV
400 KHz
S-start / SEQ
CNTL
2P2Z
Vref
Ref
DutyAdj
Uout
E
P
W
M
2
3
Vout
4
Vin
H
W
1
EPWM1A
Duty
FB
EPWM4A
EPWM3A
EPWM2A
GATE
DRV
400 KHz
Voltage
Controller
ADC
DRV
Vout
rslt0
A
D
C
I1
Ch4
Ch3
Ch2
Ch1
Ch0
H
W
I2
I3
I4
400 KHz
0
1
D
2
3
0
1
2
3
0
+ % Adj
Ph1
D
- % Adj
Ph2
D
+ % Adj
Ph3
D
Zero Adj
Ph4
F
TEXAS INSTRUMENTS
Multi-output control s/w module
C / C++
Assembly
N-BuckLoop control module
Coef[1]
Coefficient B2
Coef[1]
Vref[1]
2 pole /
2 Zero
Ref
Uout[1]
DPWM
module
Duty PWM
PWM-1
Coefficient A2
ADC
module
ADC-1
Coefficient A1
In
Coefficient B1
Uout
FB
Coefficient B0
Controller 1
Out
Dmax
Coef[2]
Dmin
Coef [1-N]
Coefficient set 1A
N
Vref[2]
2 pole /
2 Zero
Ref
Uout
Uout[2]
Duty PWM
PWM-2
ADC
module
ADC-2
FB
Controller 2
Coefficient B2
DPWM
module
Coef[1]
Coefficient B1
Vref [1-N]
N
Out
In
Coefficient B0
Uout [1-N]
Coefficient A2
N
Coefficient A1
Dmax
Coef[N]
Dmin
Vref[N]
2 pole /
2 Zero
Ref
Coefficient set 1B
Uout
Uout[N]
DPWM
module
Duty PWM
PWM-N
ADC
module
ADC-N
FB
Controller N
S-start / SEQ
Vref[1]
Out
In
TEXAS INSTRUMENTS
How many Vreg outputs ?
CPU speed (MHz)
Context save (cyc)
Context restore (cyc)
100
12
12
# DC/DC loops
1 laws
Overhead
Control
28
27
BG spare (MIPs)
BG loop spd (KHz)
2 laws
Overhead
Control
28
54
BG spare (MIPs)
BG loop spd (KHz)
3 laws
Overhead
Control
28
81
BG spare (MIPs)
BG loop spd (KHz)
4 laws
Overhead
Control
28
108
BG spare (MIPs)
BG loop spd (KHz)
5 laws
Overhead
Control
28
135
BG spare (MIPs)
BG loop spd (KHz)
6 laws
Overhead
Control
28
162
BG spare (MIPs)
BG loop spd (KHz)
7 laws
Overhead
Control
28
189
BG spare (MIPs)
BG loop spd (KHz)
8 laws
Overhead
Control
BG spare (MIPs)
BG loop spd (KHz)
28
216
Control loop (cyc)
Misc Mgmt
Background code (cyc)
27
4
300
CPU prd (nS)
10.0
200
5.0
300
3.3
400
2.5
500
2.0
700
1.4
1000
1.0
11.0%
5.6%
5.4%
16.5%
8.4%
8.1%
22.0%
11.2%
10.8%
27.5%
14.0%
13.5%
38.5%
19.6%
18.9%
55.0%
28.0%
27.0%
89.0
296.7
83.5
278.3
78.0
260.0
72.5
241.7
61.5
205.0
45.0
150.0
16.4%
5.6%
10.8%
24.6%
8.4%
16.2%
32.8%
11.2%
21.6%
41.0%
14.0%
27.0%
57.4%
19.6%
37.8%
82.0%
28.0%
54.0%
83.6
278.7
75.4
251.3
67.2
224.0
59.0
196.7
42.6
142.0
18.0
60.0
21.8%
5.6%
16.2%
32.7%
8.4%
24.3%
43.6%
11.2%
32.4%
54.5%
14.0%
40.5%
76.3%
19.6%
56.7%
109.0%
28.0%
81.0%
78.2
260.7
67.3
224.3
56.4
188.0
45.5
151.7
23.7
79.0
-9.0
-30.0
27.2%
5.6%
21.6%
40.8%
8.4%
32.4%
54.4%
11.2%
43.2%
68.0%
14.0%
54.0%
95.2%
19.6%
75.6%
136.0%
28.0%
108.0%
72.8
242.7
59.2
197.3
45.6
152.0
32.0
106.7
4.8
16.0
-36.0
-120.0
32.6%
5.6%
27.0%
48.9%
8.4%
40.5%
65.2%
11.2%
54.0%
81.5%
14.0%
67.5%
114.1%
19.6%
94.5%
163.0%
28.0%
135.0%
67.4
224.7
51.1
170.3
34.8
116.0
18.5
61.7
-14.1
-47.0
-63.0
-210.0
38.0%
5.6%
32.4%
57.0%
8.4%
48.6%
76.0%
11.2%
64.8%
95.0%
14.0%
81.0%
133.0%
19.6%
113.4%
190.0%
28.0%
162.0%
62.0
206.7
43.0
143.3
24.0
80.0
5.0
16.7
-33.0
-110.0
-90.0
-300.0
43.4%
5.6%
37.8%
65.1%
8.4%
56.7%
86.8%
11.2%
75.6%
108.5%
14.0%
94.5%
151.9%
19.6%
132.3%
217.0%
28.0%
189.0%
56.6
188.7
34.9
116.3
13.2
44.0
-8.5
-28.3
-51.9
-173.0
-117.0
-390.0
48.8%
5.6%
43.2%
73.2%
8.4%
64.8%
97.6%
11.2%
86.4%
122.0%
14.0%
108.0%
170.8%
19.6%
151.2%
244.0%
28.0%
216.0%
51.2
170.7
26.8
89.3
2.4
8.0
-22.0
-73.3
-70.8
-236.0
-144.0
-480.0
KHz
uS
TEXAS INSTRUMENTS
Power Supply
Control Loop...
TEXAS INSTRUMENTS
Introduction
•
•
•
•
•
Analog control of Power Supply
Digital control of Power Supply
Design by Emulation (DBE)
Direct Digital Design (DDD)
Design Example
TEXAS INSTRUMENTS
Analog Control of Power Supply
r +
(reference)
“analog computation”
s-domain equations

e
-
Ky
EA
(volt/current
error amp
compensation)
u
PWM
d
P
(power
converter)
y
(volt/
current)
K
(feedback)
C2
C
y
C1
R
R2
R
Ky
R3
Q
RL
R1
R4
EA gain or
analog controller
U R  1  R1C1s 

C ( s)   2 
E R1  s(1  R2C2 s) 
Need to find :
R1, R2, C1, C2
Switching &
output
filter stage
L
Y
P( s) 
d
Power stage ss model
TEXAS INSTRUMENTS
Digital Control of Power Supply
r[n]
+

e[n]
u[n]
Cd
(controller)
-Ky[n]
Difference equation
DPWM
A-D
d
P
y
(plant)
K
S+ZOH+Quantizer
C
U (n)  a2  U (n  2)  a1  U (n  1) 
b2  E (n  2)  b1  E (n  1)  b0  E (n)
where E(n)  R(n)  KY(n)
Need to find:
a1, a2, b0, b1, b2
Q
R
Switching &
Output filter
stage
L
Power stage ss model P(s)
Z Transform
TEXAS INSTRUMENTS
Design by Emulation (DBE)
r
+

e
-
Cd
u
(controller)
PWM d
A-D
1
P
(plant)
y
K
Ignore S/H effect, choose controller type (PID, lag, lead, 2p-2z)
Derive Plant model  P(s)
Cd ( s) P( s)
Y ( s)

R( s) 1  KCd ( s) P( s)
2
Closed loop gain
3
Use Bode plot and system criteria (BW, PM, GM) to design analog controller Cd(s).
H ( s) 
4
Transform Cd(s) to Cd(z)  use: Tustin bilinear transform:
5
Transform Cd(z) to difference equation  use:
2  1  z 1 

s   
1 
T 1 z 
x(n-1) ↔ z -1. X(z)
TEXAS INSTRUMENTS
Direct Digital Design (DDD)
R
+

E
-
U
Cd
(controller)
Hc
Comp
delay
DPWM
A-D
S+ZOH
P
W
(plant)
K
“Digital Plant”
1
Choose controller type, e.g. 2p-2z, 2p-1z
2
Digitize Plant model P(s)  P(z) use: P(z) = Z{ P(s) . ZOH(s) . Hc }
this exactly accounts for ZOH + Computation delay.
Cd ( z ) P ( z )
W ( z)

R( z ) 1  KCd ( z ) P( z )
3
Closed loop gain
4
Design Cd(z) to meet system criteria.  use: Z-Domain Root locus, Bode plot,
5
Transform Cd(z) to difference equation  use:
H ( z) 
x(n-1) ↔ z -1. X(z)
TEXAS INSTRUMENTS
Design Example
•
•
•
•
Digital control - DC/DC conv.
Sampling scheme
Design by Emulation (DBE)
Direct Digital Design (DDD)
TEXAS INSTRUMENTS
Digital Control of DC/DC Converter
Iin
Io
Vo
L
Vin
C
RL
 Vin
= 4V ~ 6V,
 Vo = 1.6V, Io = 16A
 L = 1uH, C = 1620uF, ESR = 0.004 ohm
 PWM Freq = 250kHz,
 Digital Control Loop Sampling Freq, fs = 250kHz,
 Voltage Control Loop Bandwidth = 20kHz,
 Phase Margin = 45 deg
 Settling Time < 75uSec
TEXAS INSTRUMENTS
Design by Emulation (DBE)
Iin
L
Vin

Vo
G P (s) 

d
Kd
Vo
d
C
RL
Vos
A/D
PWM
Vo(n)
U(n)
UCD9508
Gc(z)
E(n)
+
Vref
TEXAS INSTRUMENTS
Calculating Gp(s) – continuous plant
Ignore Sample & Hold (S&H) Effect,
PWM Modulator Gain Fm = 1,
Continuous Plant Gp1(s) = Kd.Fm.Gp(s)
Vin=5.0, RL=0.1, Kd=0.5,
L=1uH, C=1620uF, Rc=0.004 ohm,
1.62x10-5 s + 2.5
Gp1(s) = --------------------------------------1.685x10-9 s2 + 1.648x10-5 s + 1
G1p(s)
d
Gp(s)
Vo
Fm
Kd
Vo(n)
U(n)
Gc(z)
Need to find:
Gc(s) = ? - use Root locus, Bode, ... other
Gc(z) = ?
E(n)
+
Vref
TEXAS INSTRUMENTS
Equivalent Discrete controller Gc(z)
1. Discrete Equivalents via Numerical Integration
a) Forward rule, s= (z-1)/Ts
b) Backward rule, s = (z-1)/zTs
c) Trapezoidal/Tustin/Bilinear, s = 2(z-1)/Ts(z+1)
2. Pole-Zero Matching Equivalents, z = esTs
3. Hold Equivalents : zero-order-hold (ZOH), first-order-hold (FOH)
E.g. 1) In Matlab, Gc_z = c2d(Gc_s, Ts, 'matched')
12.34 z^2 - 22.53 z + 10.28
[pole-zero matched,
Gc1(z) = ------------------------------------------Ts = 4uSec, i.e. 250KHz]
z^2 - 1.605 z + 0.6051
E.g. 2) In Matlab, Gc_z = c2d(Gc_s, Ts, ‘tustin')
12.49 z^2 - 22.81 z + 10.41
Gc1(z) = -----------------------------------z^2 - 1.598 z + 0.5985
[Tustin, Ts = 4uSec]
TEXAS INSTRUMENTS
Transient response result
(Fpwm = 250KHz), pole-Zero Matched
Controller
Gp1(z)*Gc1(z)
TEXAS INSTRUMENTS
Direct Digital Design (DDD)
Iin
Vo
L
Vin
C
RL
Kd
Ts
d
ZOH
DPWM

Vo
G P (s) 

d
UCD9508
Comp Delay Model
Hc = e-sTd ,
Td = Computational Time Delay
Hc U(n) Gc(z)
Vo(n)
E(n)
+
Vref
TEXAS INSTRUMENTS
Sampling Scheme
(1 of 4)
Sample to PWM Update Delay Td = 2Ts (Computation Delay)
N
N+1
Ts
CTR
N+2
(Sample period)
CTR = Zero
t
PWM
PWM
update
INT
CPU
ISR
ADC
SW
SOC
BG
ISR
BG
ISR
BG
ISR
Td
(computation delay)
TEXAS INSTRUMENTS
Sampling Scheme
(2 of 4)
Computation Delay: Td ~ 0.75Ts i.e. 0.5Ts ≤ Td ≤ 1Ts
N
N+1
Ts
N+2
(Sample period)
CTR = duty/2
CTR
t
PWM
update
PWM
HW SOC
ADC
INT
CPU
ISR
BG
TC
ISR
Td
BG
ISR
TC
Td
BG
ISR
TC
BG
Td
(computation delay)
TEXAS INSTRUMENTS
Sampling Scheme
(3 of 4)
Computation Delay: Td = 0.5Ts
N
N+1
Ts
N+2
(Sample period)
CTR=PRD
CTR
t
PWM
update
PWM
HW SOC
ADC
INT
CPU
ISR
BG
TC
ISR
BG
TC
ISR
BG
TC
ISR
Td
(computation delay)
TEXAS INSTRUMENTS
Sampling Scheme
(4 of 4)
Computation Delay: Td ≤ 0.5Ts
N
N+1
Ts
CTR = fixed value
N+2
(Sample period)
CTR
t
PWM
update
PWM
HW SOC
ADC
INT
CPU
ISR
BG
TC
ISR
BG
TC
ISR
BG
TC
ISR
Td
(computation delay)
TEXAS INSTRUMENTS
Effect of Sample and Hold
Time Delay Ts/2
Ts
PM = 33.18 deg
ZOH = -ωTs/2
= -180f/fs
fs = 250kHz,
f = 7.25kHz,
additional
phase lag of 5.2°
PM = 28 deg
f = 125kHz,
additional
phase lag of 90°
TEXAS INSTRUMENTS
Calculating Gp(z) – discrete plant
Gp1(z)
Vin=5.0, RL=0.1, Kd=0.5
L=1uH, C=1620uF,
Rc=0.004 ohm
d
1.62x10-5 s + 2.5
Kd.Gp(s) = ------------------------------------1.685x10-9 s2 + 1.648x10-5 s + 1
ZOH(s) = (1 – e-sTs )/s
Hc = e-sTd
Gp(s)
Vo
Kd
PWM
Ts
Hc
ZOH
accounts for sample & hold
+ comp. delay
Discrete Plant Model,
Gp(z) = Z{ZOH(s).Kd.Gp(s).Hc}
U(n)
Gc(z)
Vo(n)
E(n)
+
Vref
Gp1(z) = (0.0494z - 0.0261)/(z2 - 1.952 z + 0.962), [Td=0, Hc = 1]
Note: for now use Td = 0, as a base line comparison
TEXAS INSTRUMENTS
Calculating Gc(z) – using Matlab
Use Matlab SISOTOOL for Gp1(z), and design Gc2(z)
Discrete System Bode Plot,
2 Pole 2 Zero Type Controller,
Gp1(z)*Gc2(z)
(Td=0)
BW = 27.9kHz, PM = 61.6 deg, GM = 9dB
14.87 z^2 - 26.91 z + 12.16
Gc2(z) = ------------------------------------z^2 - 1.473 z + 0.4731
Vo(n)
Gp(z)
U(n)
Gc(z)
E(n)
+
Vref
TEXAS INSTRUMENTS
Effect of Computational delay - [Td = 0.5Ts]
Plant: with computation delay [Td = 0.5Ts],
Gp2(z) = (0.022z^2+0.017z - 0.158)/z(z^2 - 1.952 z + 0.962),
Controller with no delay compensation,
Gc2(z)=(14.87 z^2 - 26.91 z + 12.16)/(z^2 - 1.473 z + 0.4731 )
Gp2(z)*Gc2(z)
Phase Lag,
Hc = -ωTd
=360fTd
Loss of PM from
(Gp1*Gc2) to (Gp2*Gc2)
= 61.6-41
= 20.6 deg
BW = 26.9kHz, PM = 41 deg, GM = 7.46dB
Hc = 360(26900)(2uS)
= 19.37 deg
TEXAS INSTRUMENTS
Transient response result (FPWM=250KHz)
Gp2(z)*Gc2(z)
TEXAS INSTRUMENTS
Control Law realization
1 of 2
14.9 z2 – 26.9 z + 12.2
14.9 – 26.9 z -1 + 12.2 z -2
Gc(z) = U / E = ------------------------------------ = ----------------------------------z2 - 1.47 z + 0.47
1 – 1.47 z -1 + 0.47 z -2
14.9 E(z) – 26.9 z-1 E(z) + 12.2 z-2 E(z) = U(z) – 1.47 z-1 U(z) + 0.47 z-2 U(z)
U(z) = – z-2{0.47 U(z)} + z-1{1.47 U(z)} + z-2{12.2 E(z)} – z-1{26.9 E(z)} + z-0{14.9 E(z)}
Use: x(n-a) <==> z-a X(z)
u(n) = – 0.47 u(n-2) + 1.47 u(n-1) + 12.2 e(n-2) – 26.9 e(n-1) + 14.9 e(n)
u(n) = a2*u(n-2) + a1*u(n-1) + b2*e(n-2) – b1*e(n-1) + b0*e(n)
Where, a2 = – 0.47, a1 = 1.47, b2 = 12.2, b1 = – 26.9, b0 = 14.9
TEXAS INSTRUMENTS
Control Law realization
2 of 2
u(n) = a2*u(n-2) + a1*u(n-1) + b2*e(n-2) – b1*e(n-1) + b0*e(n)
e(n)
Z-1
Z-1
e(n)
IIR (Infinite Impulse Response) Filter
e(n-1)
e(n-2)
b0
b1
b2
+
+
+
a2
a1
y(n-2)
b0 – b1*z -1 + b2*z -2
U / E = ----------------------------1 – a1*z -1 + a2*z -2
u(n)
Roots of denominator = Poles
Roots of numerator = Zeros
y(n-1)
Z-1
Z-1
2nd order biquad IIR filter section
can be used to realize a 2 pole / 2 zero controller
TEXAS INSTRUMENTS
Sampling frequency (fs) selection
Design by
Emulation (DBE)
Direct digital
Design (DDD)
Neglect ZOH & Computational delay
“poor sampling strategy”, i.e. Td = 2Ts
fs ≈ 30 x fc
Neglect ZOH & Computational delay
“good sampling strategy”, i.e. Td = 0.5Ts
fs ≈ 20 x fc
Account for ZOH & Computational delay
“poor sampling strategy”, i.e. Td = 2Ts
fs ≈ 15 x fc
Account for ZOH & Computational delay
“good sampling strategy”, i.e. Td < 0.5Ts
fs ≈ 10 x fc
fs = 12.5*fc
fs = 20*fc
TEXAS INSTRUMENTS
TEXAS INSTRUMENTS
Spare....
TEXAS INSTRUMENTS
Module Sync’ing and Phase Control
Single EPWM module
Ext Sync In
(optional)
Master
Time-Base (TB)
TBPRD Shadow (16)
TBPRD Active (16)
Phase Reg
Sync
In/Out
Select
Mux
CTR=ZERO
CTR=CMPB
Disabled
EPWMxSYNCO
EPWM1A
CNT=Zero
CTR=PRD
TBCTL[SYNCOSEL]
CNT=CMPB
EPWMxSYNCI
TBCNT
Active (16)
SyncIn
S0 S1
16
Counter
UP / DWN
(16 bit)
En
F
TBCTL[SWFSYNC]
(software forced sync)
TBCTL[CNTLDE]
X
1
EPWM1B
SyncOut
CTR=ZERO
CTR_Dir
16
TBPHS Active (16)
Phase
Control
CTR=PRD
EPWMxINTn
CTR=ZERO
CTR=CMPA
Counter Compare (CC)
CTR=CMPB
Event
Trigger &
Interrupt
(ET)
EPWMxSOCA
EPWMxSOCB
CTR_Dir
16
CTR=CMPA
CMPA Shadow (16)
En
SyncIn
F
Dead
Band
(DB)
PWM
Chopper
(PC)
EPWM2B
CNT=CMPB
Trip
Zone
(TZ)
2
CTR=CMPB
EPWMxBO
EPWMB
EPWM2A
CNT=Zero
EPWMxAO
EPWMA
CMPA Active (16)
16
Phase Reg
Action
Qualifier
(AQ)
16
Slave
X
SyncOut
16
CMPB Active (16)
CMPB Shadow (16)
EPWMxTZINTn
TZ1n to TZ6n
CTR=ZERO
TEXAS INSTRUMENTS
Phase control with EPWM module
TBCTR
FFFFh
Master Module
600
TBPRD
600
0000
CTR=Zero
(SycnOut)
time
TBCTR
F
FFFFh
Phase = 120o
Slave Module
600
TBPRD
600
200
TBPHS
200
0000
SyncIn
time
TEXAS INSTRUMENTS
Multi-Phase Interleaved (MPI)
1/2
4B
Master
Phase Reg
En
F
2B
EPWM1A
CNT=Zero
X
1
Vin
EPWM1B
CNT=CMPB
SyncO
1B
Slave
Phase Reg
En
F
Vout
3B
SyncI
GATE
DRV
SyncI
EPWM2A
CNT=Zero
EPWM2B
CNT=CMPB
X
2
SyncO
EPWM1B
Slave
Phase Reg
En

F
SyncI
F
EPWM3A
CNT=Zero
EPWM3B
CNT=CMPB
X
3
EPWM2B
SyncO
F
Slave
Phase Reg
En

SyncI
F
EPWM3B
EPWM4A
F
CNT=Zero
EPWM4B
CNT=CMPB
4
X
SyncO
EPWM4B
TEXAS INSTRUMENTS
Multi-Phase Interleaved (MPI)
Master
Phase Reg
En

SyncI
F
2/2
Z
Z
Z
Z
I
I
I
I
EPWM1A
CNT=Zero
CA
CNT=CMPB
EPWM1B
X
1
SyncO
P CA
EPWM1A
Phase Reg
En
F
P CA
CA
A
RED
FED
P CA
A
RED
EPWM1B
Slave
CA
A
RED
FED
FED
SyncI
F
EPWM2A
CNT=Zero
EPWM2B
CNT=CMPB
X
2
EPWM2A
SyncO
EPWM2B
Slave
Phase Reg
En

F
SyncI
F
EPWM3A
CNT=Zero
CNT=CMPB
EPWM3B
X
3
EPWM3A
EPWM3B
SyncO
F
Slave
Phase Reg
En
F
SyncI
EPWM4A
EPWM4A
EPWM4B
EPWM4B
CNT=Zero
CNT=CMPB
4
X
SyncO
TEXAS INSTRUMENTS
Multi Channel independent freq.
Master
Phase Reg
En
1B
SyncIn
Vout1B
Vin
FX
1/2
EPWM1A
Vout1A
CNT=Zero
CNT=CMPB
EPWM1B
X
1
GATE
DRV
SyncO
Master
Phase Reg
1A
En
2B
SyncIn
FX
Vout2B
Vin
EPWM2A
Vout2A
CNT=Zero
EPWM2B
CNT=CMPB
X
2
GATE
DRV
SyncO
Master
Phase Reg
2A
En
3B
SyncIn
FX
Vout3B
Vin
EPWM3A
Vout3A
CNT=Zero
CNT=CMPB
3
X
EPWM3B
SyncO
3A
GATE
DRV
TEXAS INSTRUMENTS
Multi Channel “synchronized” freq.
f1
Master
Phase Reg
En
4
SyncIn
F
2
CNT=Zero
EPWM1B
CNT=CMPB
X
1
Vout4
3
EPWM1A
Vout3
Vout2
Vin
SyncO
Vout1
2*f1
Slave
Phase Reg
En
1
SyncIn
F*
GATE
DRV
EPWM2A
CNT=Zero
EPWM2B
CNT=CMPB
X
2
SyncO
Master Module
f1 = 1 / Period
4*f1
Slave
Phase Reg
En
SyncIn
F*
EPWM3A
SyncO
CNT=Zero
EPWM3B
CNT=CMPB
X
3
SyncO
f2 = 2 * f1
5*f1
Slave
Phase Reg
En
f3 = 4 * f1
SyncIn
F*
EPWM4A
CNT=Zero
EPWM4B
CNT=CMPB
4
Slave Module
Phase = 0o
X
f4 = 5 * f1
SyncO
* could be constant
offset
TEXAS INSTRUMENTS
Configuration example #1
VIN 1

VOUT 1
Triple output
o
o

4-phase interleaved
Two single phase
Single Vin
VOUT 2
VOUT 3
TEXAS INSTRUMENTS
Configuration example #2
VIN 1

VOUT 1
Dual output
o

2 x 3-phase interleaved
Single Vin
VOUT 2
TEXAS INSTRUMENTS
Configuration example #4
VIN 2
VIN 1

VOUT 1
Six output voltages
o
VOUT 2
o
o
VOUT 3

Independent control
loops
Individual monitoring
Adjustable interleaving
Single or dual Vin
capable
VOUT 4
VOUT 5
VOUT 6
TEXAS INSTRUMENTS
System Framework
5uS
Time-slice
(200KHz)
ISR
base
Back
Ground
TS1
base
BG
TS2
base
BG
TS3
base
TS4
BG
Interrupt





base
BG
t
Can address the control of most power system (even complex ones)
Simple to use and understand
Efficient (incurs only 1 ISR context save/restore)
Deterministic (all events synchronous and submultiples of ISR freq.)
High degree of visibility during debug and development
Back-ground loop (BG)
• C / C++, code can be large and complex
• Feature rich e.g. diagnostics, fault management, communications, ….etc
• System intelligence / application’s personality defined here
Interrupt Service Routine (ISR) – Main control loop
• Low cycle count “in-line” assembly (ASM), this results in a very small footprint.
• Control and “Math function” type code only. “if then else” branches or loops are avoided
• Once developed, should change very little. Low maintenance burden.
TEXAS INSTRUMENTS
Sampling Considerations
1 of 2
Sample to PWM Update Delay Td = 2Ts (Computation Delay)
N
N+1
Ts
CTR
N+2
(Sample period)
CTR = Zero
t
PWM
PWM
update
INT
CPU
ISR
ADC
SW
SOC
BG
ISR
BG
ISR
BG
ISR
Td
(computation delay)
TEXAS INSTRUMENTS
Sampling Considerations
2 of 2
Computation Delay: Td = 0.5Ts
N
N+1
Ts
N+2
(Sample period)
CTR=PRD
CTR
t
PWM
update
PWM
HW SOC
ADC
INT
CPU
ISR
BG
TC
ISR
BG
TC
ISR
BG
TC
ISR
Td
(computation delay)
TEXAS INSTRUMENTS
Digital Power Modules – some examples
Symbol
CNTL
2P2Z
Ref
Out
Fdbk
Descr.
Controller,
2 pole / 2 zero
# Cycles
25
Symbol
PFC
2PHIL
DRV
Duty
FILT
BIQUAD
In
Out
INV
SQR
In
Out
PFC
ICMD
V1
Out
V2
Vac
IIR
digital
filter
Inverse
square
function
PFC
Current
Command
function
E
V
Descr.
T2PWM
H
W
T4PWM
Adj
# Cycles
PFC 2-phase
Interleaved
PWM
s/w driver
26
Zero Voltage
Switched
Full Bridge
PWM
s/w driver
14
Analog /
Digital conv.
Sequencer
s/w driver
32
Multi-phase3
Interleaved
PWM
s/w driver
15
23
ZVS
FB
DRV
phase
78
llegdb
PWM1
E
V
PWM2
H
W
PWM7
PWM8
rlegdb
ADC_A0
30
ADC
SEQ1
DRV
A
D
C
H
W
ADC_A1
ADC_A2
ADC_A3
ADC_A4
Rslt[0:5]
SLEW
LIMIT
In
Out
Incr
PFC
OVP
In
Out
Vmon
Slew rate
Limiter
function
PFC overvoltage
monitor
ADC_A5
17
MPH3
IL
DRV
25
Duty
EPWM1A
E
P
W
M
H
W
EPWM1B
EPWM2A
EPWM2B
EPWM3A
EPWM3B
TEXAS INSTRUMENTS
CPU Bandwidth utilization
MIPS = 100
# TS = 4
S. rate = 200
ISR
All
TS1
TS2
TS3
TS4
Rate
# inst / uS = 100
# inst / time slice = 500
Sampling period = 5.0
Function / Activity
# Cyc
200KHz Context Save / Restore
32
200KHz ISR Call / Return / Ack
24
200KHz Time slice Mgmt
12
200KHz ADCSEQ2_DRV
14
200KHz CNTL_2P2Z 1 (V loop)
200KHz CNTL_2P2Z 2 ( I loop)
36
36
200KHz
200KHz
200KHz
200KHz
200KHz
25
14
57
35
7
I_FOLD_BACK
ZVSFB_DRV
ADCSEQ1_DRV
FILT_2P2Z
AC_LINE_RECT
PWM(KHz) = 200
PWM(bits) = 9.0
Tot. Cyc.
292
FW_Isr
200 KHz
Stats
% Util
Every ISR call
58%
Context Save
ADCSEQ2_DRV
CNTL_2P2Z(1)
CNTL_2P2Z(2)
ZVSFB_DRV
ADCSEQ1_DRV
FILT_2P2Z
AC_LINE_RECT
117
100KHz PFC_OVP
25
100KHz PFC_ICMD
100KHz CNTL_2P2Z 4 (I loop)
100KHz PFC2PHIL_DRV
30
36
26
50KHz
BOXCAR_AVG 1
42
50KHz
100 Hz
50KHz
1KHz
BOXCAR_AVG 2
PFC_ISHARE
Execution Pre-scaler(1:50)
CNTL_2P2Z 3 (V loop)
42
15
10
36
100KHz
100KHz
100KHz
100KHz
PFC_OVP
PFC_ICMD
CNTL_2P2Z 4 (I loop)
PFC2PHIL_DRV
25
30
36
26
117
50KHz
50KHz
FILT_BIQUAD
INV_SQR
46
78
124
% Util
82%
Time Slice mgr
#Cyc. Rem.
91
145
% Util
87%
#Cyc. Rem.
63
50 KHz
#Cyc. Rem.
91
% Util
50 KHz
50 KHz
TS1
TS2
TS3
TS4
PFC_OVP
PFC_ICMD
CNTL_2P2Z(4)
PFC2PHIL_DRV
BOXCAR_AVG(1)
BOXCAR_AVG(2)
PFC_ISHARE
ExecPS(1:50)
CNTL_2P2Z(3)
PFC_OVP
PFC_ICMD
CNTL_2P2Z(4)
PFC2PHIL_DRV
FILT_BIQUAD
INV_SQR
% Util
82%
50 KHz
83%
#Cyc. Rem.
84
BG
Function / Activity
Comms + Supervisory
+ Soft-Start + Other ?
SLEW_LIMIT 1
SLEW_LIMIT 2
# inst.
400
Tot.Cyc.
434
Stats
Int Ack
Context restore
17
17
% ISR utilization =
Spare ISR MIPS =
BG loop rate (KHz) / (uS) =
87%
12.6
29.0
34.4
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TEXAS INSTRUMENTS
The end…...
TEXAS INSTRUMENTS