Transcript Dr. Andrei Grebennikov

LECTURE 3. POWER AMPLIFIER DESIGN FUNDAMENTALS
3.1. Main characteristics (two-port networks, gain,
delivered power )
3.2. Gain and stability
3.3. Stabilization circuit technique
3.4. Class-A,-B,-C operation modes
3.5. Linearity
3.6. DC biasing
3.7. Push-pull amplifiers
3.8. Practical aspect of RF and microwave
power amplifiers
1
3.1. Main characteristics
Generalized single-stage power amplifier circuit
Input
matching
circuit
Source
WS
I2
I1
1
[W]
V1
2
3
Output
matching
circuit
V2
Load
WL
4
Two-port active device is characterized by immitance W-parameters which
means system of impedance Z-parameters or admittance Y-parameters
Matching circuits are necessary to transform source WS and load WL
immitances into definite values between points 1-2 and 3-4, respectively
If source of input signal is presented by current source with internal admittance YS
1
IS
I1
V1
YS
I2
[Y]
 device is characterized by Y-parameters
3
YL
V2
2
4
 I1  Y11V1  Y12V2

 I 2  Y21V1  Y22V2
If source of input signal is presented by voltage source with internal impedance ZS
ZS
I2
I1
V1
VS
2
[Z]
 device is characterized by Z-parameters
3
1
ZL
V2
4
 V1  Z11 I1  Z12 I 2

V2  Z 21 I1  Z 22 I 2
2
3.1. Main characteristics
Power amplifier gain
(in terms of Y-parameters)
• Operating power gain GP = PL /Pin - ratio of power dissipated in active
load GL to power delivered to input port of active device with
admittance Yin : this gain is independent of GS but is strongly
dependent on GL
• Available power gain GA = Pout /PS - ratio of power available at output
port of active device with admittance Yout to power available from
source GS : this gain depends on GS but is independent of GL
• Transducer power gain GT = PL /PS - ratio of power dissipated in
active load GL to power available from source GS : this gain
strongly depends on both GS and GL
• Maximum available gain MAG - theoretical power gain of active
device when its reverse transfer function Y12 is set equal to zero :
represents theoretical gain limit that can be achieved with given
device under assumption of conjugate input and output impedance
matching
3
3.1. Main characteristics
Operating power gain
Two types of power gain are widely used: operating
power gain GP and transducer power gain GT
IS
1
I1
V1
YS
I2
[Y]
3
• operating power gain to characterize device
2
amplifying capability and multistage power amplifier
• transducer power gain to evaluate input matching and stability
Power flowing from input port
From
 I1  Y11V1  Y12V2

 I 2  Y21V1  Y22V2
input admittance
Output power dissipated in load
4
Pin  0.5 V12 Re Yin
in view of
I 2   YL V2
I1
Y12 Y21
Yin 
 Y11 
V1
Y22  YL
PL  0.5 V22 Re YL
2
operating power gain
YL
V2
Y21 ReYL
PL
GP 

2
Pin
Y22  YL ReYin
4
3.1. Main characteristics
Transducer power gain
Transducer power gain GT includes
assumption of conjugate matching
both load and source
From
 I1  Y11V1  Y12V2

 I 2  Y21V1  Y22V2
source current
in view of
IS 
Output power dissipated in load
transducer power gain
Maximum available gain
(Y12 = 0, YS = Y11*, YL = Y22*)
IS
I S2
PS 
8ReYS
Power flowing from input port
I1
1
V1
YS
I2
[Y]
3
YL
V2
2
4
I S  YSV1  I1
Y11  YS Y22  YL   Y12Y21
Y22  YL
V1
PL  0.5 V22 Re YL
P
GT  L 
PS
2
4 Y21 ReYS ReYL
Y11  YS Y22  YL   Y12Y21 2
MAG 
Y21
2
4 ReY11ReY22
5
3.1. Main characteristics
Small-signal FET power amplifier
Lin
RS
g
d
Rgs
VS
Rds
Yin
Cgs
V
Cds
Y11  j Cgs / 1  j RgsCgs 
Y12  0
Y21  gm / 1  j RgsCgs 
Y22  1 / Rds   j Cds
f 
GT  f   GT  f T  T 
 f 
2
- gain estimation at
any frequency vs
gain at transition
frequency
Lout
RL
gmV
s
Equivalent circuit with Cgd = 0
Yout
s
Input and output conjugate matching
RS  Rgs
RL  Rds
Lin  1/  2Cgs
Lout  1/  2Cds
2
 f  Rds
GT Cgd  0  MAG   T 
 f  4 Rgs
f T  gm / 2 Cgs - transition frequency
f max 
fT
2
Rds
Rgs
- maximum frequency
where MAG = 1
6
3.2. Gain and stability
Principle of power amplifier design - to provide maximum power gain and
efficiency for given output power with predictable degree of stability
Main reasons of instability:
• positive feedback from output to input through intrinsic feedback capacitance
or inductance of common-grounded terminal
• oscillation conditions due to external elements forming positive feedback loop
In terms of immitance approach, circuit will be unconditionally stable if
for both hypothetical conditions of open-circuited input and output ports:
Re WS    Win    0

 Im WS    Win    0
Re WL    Wout    0

Im WL    Wout    0
In case of opposite signs, active two-port network can be treated as
unstable or potentially unstable (having negative input or output immitance)
When
Re WS    0
Requirements of power amplifier
stability can be simplified to
Re WL    0
Re Win    0
Re Wout    0
7
3.2. Gain and stability
Device stability
In common case, value of ReWout depends on WS 
within definite values of WS, ReWout < 0 and two-port
network will be potentially unstable
To provide unconditional stability
 ReWout /  ImWS  0
Minimum positive value
when ReWS = 0 :
Wout  W22 
W12 W21
W11  WS
Re Wout   min  0
ReWout  ReW22 
ReWout  ReW22 
W12 W21  ReW12 W21 
2Re W11  WS 
W12 W21  ReW12 W21 
2Re W11 
2ReW11 ReW22  W12 W21  ReW12 W21   0
K 
2 ReW11 ReW22  Re W12 W21 
W12 W21
- device stability factor
Unconditional stability: K > 1
Potential instability: -1 < K < 1
8
3.2. Gain and stability
Circuit stability
When active device is potentially unstable, power amplifier stability can be
improved with proper choice of source and load immitances, WS and WL:
KT 
2 Re W11  WS  Re W22  WL   Re W12 W21 
1
W12 W21
Maximum gain with unconditionally stable device
When K > 1, it is necessary to choose
load immitance WL to maximize finite
value of operating power gain GP :
 GP
 0
 ReWL

W21
/ K 
W12
GP 
ReW 
o
L
 GP
 0
 ImWL
GPmax 
2
K2  1

W21 ReWL
PL

2
Pin
W22  WL ReWin
W12 W21
K2  1
2ReW11
ImW12 W21 
ImWLo 
 ImW22
2ReW11
- maximum gain (maximum achievable
value at K = 1)
9
3.3. Stabilization circuit technique
Frequency domains of BJT potential instability
Stability factor through
Z-parameters:
K 
2 R11 R22  Re Z12 Z 21 
Z12 Z 21
BJT equivalent circuit
Z-parameters:
1 
 

Z11  rb 
/ 1  j
gm 
T 
1 
 

Z12 
/ 1  j
gm 
T 
 1
1  

Z 21 

/ 1 
g

j C   
 m
 1
1  

Z 22 

/ 1 
g

 T C  
 m
C
rb
C
Zin
c
XL
V
gmV
e
e
BJT stability factor
1
K  2rb g m
 

j
T 
j
b
 

T 
gm
 T C
 gm
1 
 C






2
Maximum value at higher frequencies:

gm
K  2rb g m 1 

 TC





10
3.3. Stabilization circuit technique
Frequency domains of BJT potential instability
At low frequencies if to take into account
dynamic base-emitter resistance r and
Early collector-emitter resistance r0  K >
1
For K = 1
f p2
gm

/
2 C
Only one unstable frequency
domain with low fp1 and high
fp2 boundary frequencies

2rb gm 2 1  gm
 TC

2

 1


or
f p2 
1
4 rbC
In common case, at higher frequencies with parasitic emitter lead inductance Le :
Expression for low fp3 and high fp4
boundary frequencies of second
domain of BJT potential instability
b
C
rb
C
f p3,4  f T
1  4 T rbC
8 T rbC
where
   T Le / rb
V
gmV
2
 1  4 T rbC 
  1
 
 8 r C   r C  2
T b 
T b 


c
Zin
XL
e
Le
11
3.3. Stabilization circuit technique
Frequency domains of BJT potential instability
Appearance of second frequency domain of BJT potential instability is result of
simultaneous effect of feedback capacitance C and emitter lead inductance Le
• first case for Le = 0 and reactive load XL:
one frequency domain of potential instability
1
Z in  rb 
Hartley oscillator
gm
 C
1
1



gm
gm 1  j

1
1   C X L   jg m X L
T
 T C
LL
LS
Boundary condition of first potential instability domain:
LL
1

LS
 T rbC
to prevent oscillations  reduce value
of collector choke inductance and
increase value of base choke inductance
12
3.3. Stabilization circuit technique
Frequency domains of BJT potential instability
Appearance of second frequency domain of BJT potential instability is result of
simultaneous effect of feedback capacitance C and emitter lead inductance Le
• second case for Le  0 and reactive load XL:
two frequency domains of potential instability
second frequency
domain
first frequency domain
LL
CS
- parasitic
oscillator with
inductive
source and
load
reactances
Le
LL
LS
Le
- parasitic oscillator with
capacitive source and
inductive load reactances
13
3.3. Stabilization circuit technique
Frequency domains of MOSFET potential instability
Stability factor through Yparameters:
2 G11 G22  Re G12 G21 
K 
Y12 Y21
MOSFET equivalent
circuit Y-parameters:
Y11 
j Cgs
1  j RgsCgs
 j Cgd
Y12   j Cgd
gm
Y21 
 j Cgd
1  j Rgs Cgs
1
Y22 
 j Cds  Cgd 
Rds
Cgd
g
d
Rgs
Yin
Rds
Cgs
V
XL
Cds
gmV
s
s
MOSFET stability factor:

Cgs 
 RgsCgs
2 

K  1 
1



2
g
R
C

m ds 
gd 
 1   Rgs Cgs 
Maximum value at higher frequencies:

2
K  1 
g m Rds


C 
1  gs 

Cgd 

14
3.3. Stabilization circuit technique
Frequency domains of MOSFET potential instability
Only one unstable frequency
domain with low fp1 and high
fp2 boundary frequencies
At low frequencies if to take into account
gate leakage resistance  K > 1
For K = 1
f p2 
1

4 Rgs C gs
g m Rds
1

C
C
1  gs
1  gs  g m Rds
Cgd
Cgd
or
f p2 
1
4 Rgs Cgs
In common case, parasitic emitter lead inductance Le creates second
frequency domain of potential instability at higher frequencies
K
=0
3
4
1.0
Cgd
g
   T Ls / Rgs
Rd
Rgs
Rds
6
Cgs
0.5
d
V
Cds
gmV
YL
Yin
s
0
0.5
1.0
RgsCgs
When  = 3.5  second frequency
domain disappears
Ls
15
3.3. Stabilization circuit technique
Frequency domains of MOSFET potential instability
Appearance of second frequency domain of MOSFET potential
instability is result of simultaneous effect of feedback
capacitance Cgd and source lead inductance Ls
• first case for LS = 0 and reactive load XL:
one frequency domain of potential instability




1 j
1  j Rgs Cgs 


j Cgs

T
1  g R

Yin 
m ds
Cgd
1  j Rgs Cgs 

BL  
 
1  j Rds Cds 1 


Cds
 Cds  


LL
LS
Hartley
oscillator
16
3.3. Stabilization circuit technique
Frequency domains of MOSFET potential instability
Appearance of second frequency domain of MOSFET potential
instability is result of simultaneous effect of feedback
capacitance Cgd and source lead inductance Ls
• second case for LS  0 and reactive load XL: two
frequency domain of potential instability
second frequency
domain
first frequency domain
LL
- parasitic
oscillator with
inductive
source and
load
reactances
CS
Ls
LL
LS
Ls
- parasitic oscillator with
capacitive source and
inductive load reactances
17
3.3. Stabilization circuit technique
General requirements to provide stable
operation of power amplifier:
• use active device with stability factor K > 1
• if it is impossible to choose active device with K > 1, provide circuit
stability factor KT > 1 on operating frequency by appropriate choice
of real parts of source and load immitances
• disrupt equivalent circuit of possible parasitic oscillators
• choose such reactive parameters of matching circuits adjacent
to input and output of active device which are necessary to avoid
self-oscillation conditions
In common case, it is difficult to propose unified approach to
provide stable operation of different power amplifiers
especially for multistage power amplifier
18
3.3. Stabilization circuit technique
Stability analysis must be done in different frequencies ranges:
• at lower frequencies when frequency of parasitic oscillations fp
is significantly smaller operating frequency f0 (fp << f0)
L1
L1
R1
L1
L2
C1
R1
C1
Vcc
Vcc
- using stabilizing
resistor R1 in
parallel to RF choke
C1
- using stabilizing
resistor R1 with
series bypass
capacitance C2 in
parallel to power
supply
- using stabilizing
resistor R1 in parallel to
additional RF choke to
avoid degradation of RF
performance
- using additional RF choke if impedance of
series R1C2 circuit is too high
R1
C2
Vcc
L1
C1
L2
R1
Vcc
C2
19
3.3. Stabilization circuit technique
Stability analysis must be done in different frequencies ranges:
• at higher frequencies when frequency of parasitic oscillations fp
is significantly higher operating frequency f0 (fp >> f0)
Vb
Vcc
- reduce value of collector
choke inductance
- increase value of base
choke inductance
C1
L2
L1
C2
- inductive impedance at
device input
C3
C4
C5
- capacitive
impedance at
device output
20
3.3. Stabilization circuit technique
Stability analysis must be done in different frequencies ranges:
• near operating frequency frequency when frequency of parasitic
oscillations fp is close to operating frequency f0 (fp  f0)
series L1C1 circuit is tuned on
operating frequency
series connection of
stabilizing RLC circuit
connected in series
between active device
and output matching
circuit
R1
Zout
L2
C1
L1
C2
C3
Zstab
L2
R1
L1
Yout
Ystab
C1
C2
C3
parallel connection of
stabilizing RLC circuit
between active device
and output matching
circuit
21
3.4. Class-A,-B,-C operation modes
Class A
i
- input cosinusoidal voltage
2Vcc
i  I q  I cos t - output cosinusoidal
V
v
R
vin
vin  Vb  Vin cos t
v Output voltage
Vcc
current
Vcc
v  Vcc  V cos t
Vcc

0
Transfer characteristic
i
2
t
i
- output cosinusoidal current
P0  I qVcc - DC output power
P  0.5 I V - fundamental output
power
I
 
Iq
Vb
0 Vp
Vin
vin
0
t
- collector efficiency
  V / Vcc - voltage peak factor
Output current
For ideal condition of zero
saturation voltage when
t
Input voltage
2

P
1 I V
1 I



P0
2 I q Vcc
2 Iq
  0.5
I / Iq  1
 1
- maximum collector efficiency in Class A
22
3.4. Class-A,-B,-C operation modes
Class B
vin  Vb  Vin cos t
Output voltage
v
i1
i
- input cosinusoidal voltage
2Vcc
   t  
 I q  I cos t ,
i  
0,
   t  2  

V
R
vin
Vcc
Vcc
Transfer characteristic

0
2
t
For moment with zero current
i  0  I q  I cos
i
i
cos  
I
vin
0
Vin

0
2
 = 90
Output current
t
Input voltage
-output current
conduction angle 2
indicates its duty cycle
t
Iq
I
i  I cos t  cos 
For moment with maximum current
i  I max  I  1  cos 
23
3.4. Class-A,-B,-C operation modes
I q   I cos
- quiescent current as function of half-conduction angle 
• when  > 90  cos  < 0  Iq > 0 - Class AB operation mode
• when  = 90  cos  = 0  Iq = 0 - Class B operation mode
• when  < 90  cos  > 0  Iq < 0 - Class C operation mode
i  I 0  I1cos t  I 2cos 2 t  I 3cos 3 t  
where
I1 
1

where

1
I0 
2
 I cos t

 I cos t
 cos  d  t   I  0
- Fourier series
- DC component

 cos  cos t d  t   I  1 - fundamental component

0 
1
sin   cos  ,
1 
1


 sin cos  

P
1 I1
1 1
  1 
 
 - collector efficiency
P0
2 I0
2 0
When  = 90 and   1
 

4
- current
coefficients
 0.785 - maximum collector
efficiency in Class B24
3.4. Class-A,-B,-C operation modes
i
I
i
Transfer characteristic
Output current
K
Imax

0
P
M
Vcc
N

v
N'
2Vcc
M'
0
M''
t
N''
Iq
Vsat
V
L
Input voltage Vcos
 = 90
t

Vcc 
v


i   Iq 


 1R   1R

tan  
I
V 1  cos 

- dynamic characteristic of power
amplifier or load line function within
   t  
1
 1R
- slope of load line
25
3.4. Class-A,-B,-C operation modes
Class B
i
Transfer characteristic
i
Output current
K
I
L
I

0
M
Vcc
P
2Vcc
v

0
t
 = 90
For increased input voltage
amplitude:
Input voltage
t
• operation in saturation, active and
pinch-off regions
• load line represents broken line with three sections:
KL- saturation region (depression in collector current waveform)
KM – active region
MP – pinch-off region
26
3.4. Class-A,-B,-C operation modes
t2
i
t2
t1
0
t1
i
v
t0
a).
• collector current becomes
asymmetrical for complex
load impedance
0
v
t0
b).
asymmetrical load line
• for inductive load impedance, depression in collector current
waveform is shifted to the left (a)
• for capacitive load impedance, depression in collector current
waveform is shifted to the right (b)
Reason: different phase conditions for higher-order harmonics
27
3.5. Linearity
To evaluate nonlinear properties of power amplifier,
consider transfer function of active device in common form of i = f(v)
where i - output current, v - input voltage
f v   f V0 
1  n  f v 
n


 
v

V
0
n
n!

v
n 1
v V

where V0 - DC
bias voltage
o
Usual method to determine nonlinear properties is to to apply twotone excitation test signal
For two signals with equal
amplitudes V1 = V2 = V :
v
Peak envelope power PEP corresponds
to maximum amplitude of 2V:
2V
PPEP  2V  / 2R
2
v  V1cos 1t  V2cos 2t
 2V cos t cos t
Total power due to each tone:
t
where
Ptotal  P1  P 2  V 2 / R
   1   2  / 2
   1   2  / 2
PPEP  2Pout  4P
T/2
where
P  P1  P 2
28
3.5. Linearity
For two-tone excitation test signal
Taylor’s expansion of output current
for first three derivatives results in
v  V0  V1cos 1t  V2cos 2t
i  f v   f V0 
1  2 f v 

V12  V22
2
4 v v V


o



1  3 f v   1 2
1  3 f v 
1 2 
 2
2
  f V0  
V1  V2  V2 cos 2t
 V1  V2  V1 cos 1t   f V0  
3
3
4

v
2 
4

v
2



v V 
v Vo 

o
1  2 f v 
2
2

V
cos2

t

V
cos2 2t
1
1
2
2
4 v v V

o

1  3 f v 
3
3

V
cos3

t

V
cos3 2t
1
1
2
24 v 3 v V

o
1  2 f v 

V1 V2 cos  1   2  t
2
2 v v V
o
1  3 f v 
2
2



V
V
cos
2



t

V
V
1
2
1
2
1 2 cos  1  2 2  t 
8 v 3 v V


o
29

3.5. Linearity
Main conclusions:
• variation of DC bias point is directly proportional to second
derivative (in common case - even derivatives) of transfer function
• device transfer function will be linear only if third derivative
(in common case - odd derivatives) is equal to zero
• even harmonic components are result of even derivatives of
transfer function; odd harmonic components are result of odd
derivatives of transfer function
• first-order mixing products (total and differential) depend on even
derivatives of transfer function
• mixing products of third and higher order are mainly determined by
odd derivatives of transfer function
Distortions which are determined by second derivatives of device
transfer function are called second-order intermodulation distortions;
distortion which are determined by third-order derivatives are called
third-order intermodulation distortions
30
3.5. Linearity
Output current amplitude of
fundamental, second and third
harmonic or intermodulation
components depends on first,
second and third degree of input
voltage, respectively
Consequently, output
powers of linear, second- or
third-order component show
straight-line behavior and
vary by 1 dB, 2 dB and 3 dB,
respectively, with 1-dB
variation of input power
Pout, dBm
These straight lines intersect at some
points which are called intercept points IPn
IP3
IP2
PIMn  nP1  n  1 IPn dBm
P1dB
P1
Second harmonic component
P21
P212
P21  2P1  IP2 dBm
Third-order intermodulation component
Pin, dBm
P21 2  3P1  2IP3 dBm
P1dB  IP3  9 dBm - 1-dB gain compression point
31
3.5. Linearity
For MOSFET device, there is optimum bias point with drain quiescent
current Idg in limits of 0.1…0.15 Idss when IM3 can be minimized
providing high-power and high-efficiency operation because of
quadratic transfer function in this region
IM3
Idq1
Idq2
Output spectrum containing n-order
intermodulation components
Idq1 > Idq2 > Idq3
V1
V2
V3
Idq3
V5
V7
V9
0
Pout




31  22
21  2
1
2
22  1
32  21
IM3  10 log10 P21 2 / P  P21 2  P dBc - third-order intermodulation
IM5  10 log10 P31 22 / P  P31 22  P dBc
where
P  P1  P2
product
- fifth-order intermodulation
product
32
3.6. DC biasing
DC biasing of active device provides required operation condition
which should be stable over input power, temperature or technology
process variations
For MOSFETs as voltage
controlled devices, at
normal conditions it is
enough to use resistive
divider to set gate bias
voltage
Vdd
Vdd
Vdd
L1
R1
L1
R1
VT1
VT1
R2
R2
VD1
L1
R1
VD1
When device
threshold
voltage is too
high, it is best
to connect
several silicon
diodes in
series
VD2
VT1
R2
R3
However, in wide temperature
range when device threshold
voltage varies with
temperature (2 mV/C), to
reduce quiescent current
variation, it is possible to use
silicon diode in series to
variable resistor
Such simple bias circuit
configurations for MOSFETs
become possible in view of
extremely small gate DC
current equal to its leakage
current only
33
3.6. DC biasing
Current mirror bias circuits
For bipolar transistor as current-controlled device, to stabilize quiescent current it
is best to use current-mirror type of bias circuits where reference diode is formed
using same diode-connected transistor with substantially smaller area
Vref
Vcc
Vcc
Vref
R2
Q3
Q1
R1
Q1
R0
Q2
RFout
RFin
R0
Q0
RFout
RFin
To minimize quiescent current variations over
temperature, ratio of ballast resistors R1/R0
must be equal to device area ratio Q0 /Q1
However,to fix current flowing from
reference source through resistor R2, its
value should be much higher than base
current of RF device Q0
Q0
To reduce current from reference
source and to increase current
driving capability for high power RF
device, driving transistor Q3 is used
to feed DC base current for RF
34
device Q0
3.6. DC biasing
Vcc
Vref
Current mirror bias circuits
R2
Popular configuration of temperature
compensated bias circuit contains one
reference transistor and one driving device
Q2
Q1
R1
Vcc
R0
RFout
Vref
Q2
Q0
RFin
R2
Q1
It is very important to provide ratio of
ballast resistors R1/R0 equal to ratio of
device areas Q0/Q1 which minimizes
variations over temperature as well as
stabilizes DC bias point over input power
R1
R0
RFout
RFin
Q0
Vbe0, V
1.4
1 - required
value of ballast
resistor R1
1.3
1
1.2
2
1.1
2 - R1 = 0
1.0
-10
-5
0
5
10
15
Pin, dBm
To minimize current from
reference voltage source, emitter
follower configuration can be used
where this current is equal to
extremely small base current of
emitter follower device Q35
2
3.7. Push-pull amplifiers
Push-pull operation helps to increase values of input and output
impedances and to additionally suppress even harmonics
For 50% duty cycle of each device (ideal
Class B) with driving sinusoidal voltage:
ic1
T2
T1
  I sin , 0    
ic1   c
0,
    2

n1
icc
Vcc
Vb
first transistor collector current
iL
RL
n2
second transistor collector current
n1
0,
0  

ic2  
  I c sin ,     2
ic2
ic1
Being transformed through output
transformer T2, total collector current:
Ic
icc
icL

2

ic2
iL    ic1   ic2    I c sin 
Ic
Ic
2
Ic0

Ic

2
2
Current flowing in center tap of
primary winding of transformer T2:
icc    ic1   ic2    Ic sin 
36
3.7. Push-pull amplifiers
Ideally, even-order harmonics are canceled
as they are in-phase and combined in center
tap of primary winding of output transformer
ic1
T2
T1
icc
To eliminate losses, it is necessary to
connect bypass capacitance to this
center point
n1
Vcc
Vb
iL
n2
RL
n1
As for 50% duty cycle, third- and higherorder odd harmonics do not exist, ideally
sinusoidal signal will appear in load
ic2
Total DC collector current
1
I co 
2
2
 icc   d 
0
2

Ic
For zero saturation resistance when
collector voltage amplitude Vc = Vcc and
equal turns of winding when VL = Vc, DC
and fundamental output powers
P0 
2

I cVcc
Pout 
1
I cVcc
2
vL    I c RL sin   VL sin 
Maximum theoretical collector
efficiency that can be achieved
in Class B operation
 
Pout


 78.5%
P0
4
37
3.7. Push-pull amplifiers
In balanced circuit, identical sides carry
180° out-of phase signals of equal amplitude
If perfect balance is maintained, there are
midpoints where signal amplitudes are zero
virtual
ground
Such a condition is called virtual grounding
Being inside device package with two balanced
transistors, virtual ground reduces commonmode inductance and simplify matching circuit
Matching conditions for
single-ended transistor
Simplification for balanced transistors
where matching parallel capacitances
are combined and DC blocking
capacitances are not required
38
3.7. Push-pull amplifiers
For push-pull operation, unbalance-to-balance transformation is required
Pin
Pout
T2
l5
l3
C6
C1
Pin
C3
T1
l4
Pout
C5
C4
C2
l1
• for 50-ohm source and
load, its characteristic
impedance = 50 Ohm
and each balanced part
sees 25 Ohm
l8
l2
• most suitable
approach is to
use 1:1 coaxial
transformer
C7
T8
l7
T7
l6
• as shortened stubs produce inductive impedances,
series capacitors C1 and C2 are used forming high-pass
matching sections
• to minimize
transformer size and
provide broadband
operation with minimum
return loss, coaxial
transformers are
mounted and soldered
along shortened
microstrip lines and
additional shortened
stubs are added for
symmetry 39
3.8. Practical aspect of RF and microwave power amplifiers
Typical microwave power amplifier topology
Vbias

Vsupply



l1
l3
Input
Output
C1
l2
C2
l4
• matching circuits in form of L-transformers:
parallel microstrip open stubs represent capacitive reactances,
series microstrip lines represent inductive reactances
• bias circuits contain quarterwave loaded and opened
microstrip lines for RF signal isolation
40
3.8. Practical aspect of RF and microwave power amplifiers
Microwave 2.5-2.7 GHz 5 W GaAs MESFET power amplifier topology
7V
330 
3.3 k
50 

1 k
50 
10 V


25 
25 
82 

Pin
50 
29 
10 pF
100 pF
0.68 F

82 


50 
50 
1-5 pF

30 pF
29 
Pout
50 
1-5 pF
• matching circuits are combinations of L-transformers (parallel
capacitors and series microstrip lines) and quarterwave lines with
different characteristic impedances
• drain bias circuit contains additional RC-circuit to prevent high-frequency
oscillations and large capacitance to prevent low-frequency oscillations
41
3.8. Practical aspect of RF and microwave power amplifiers
Microwave balanced power
amplifier
/4
50 
/4
PA1
• to combine output powers from
two or more transistors at
microwaves, 90-degree branch-line
hybrids are widely used where
active devices are isolated from
each other
Pin
/4
/4
• at equal reflection coefficients from
loads connected to output terminals,
reflection wave is absent at input
terminal and flowing to 50-ohm
ballast resistor
Pout
PA2
50 
Vg
Vdd
RFC
0.25 
Pin
50 
1 pF
RFC
lout
lin
1 pF
Z2
Z1
Z2
Z3
0.25 
0.25 
Z2
Z3
Z1
Z2
1 pF
50 
50 
0.25 
lin
lout
Pout
50 
RFC
RFC
Vg
1 pF
• branch-line hybrid
also can work as
impedance transformer
with characteristic
impedances of its
microstrip branches as
Vdd
Z 1  Z in
Z 3  Zout
Z2 
Z in Z out
2
42
3.8. Practical aspect of RF and microwave power amplifiers
Microwave 5.5 GHz 2.5 W GaAs MESFET power amplifier topology
10 V
Vg
• for monolithic microwave
20 pF
2 k
40 ,
33
5 pF
87 ,
5
5 pF 40 , 89
Pin
50 Ohm
5 pF
3.8 pF
49 , 14
50 , 62
3.8 pF
49 , 14
50 , 62
5 pF 40 , 89
40 ,
33
5 pF
2 k
Vg
50 Ohm
5 pF
87 ,
5
10 V
20 pF
applications, when output
resistance of transistor is
slightly less or higher than 50ohm, it is convenient to realize
parallel connection of active
devices (easy to provide circuit
symmetry for packaged
Pout
devices)
• to combine power from two
transistors, it is necessary
simply to transform
impedance from each device
to 100 Ohm and then parallel
connection results in
required 50-ohm load
• input matching circuits represent quarterwave microstrip line transformer
and L-transformer with series microstrip line and parallel capacitance each
43