Transcript Chap. 3 Logic Gates and Boolean Algebra

3-1
Chap. 3 Logic Gates and Boolean Algebra


Logic Gates : the basic elements of logic circuits(AND, OR, NOT,...)
Boolean Algebra
 A tool for the analysis and design of digital systems
 Describes relationship between logic circuit’s inputs and outputs
 Used to help simplify a logic circuit

3-1 Boolean constants and
variables
 Only two possible values(Many
different terms used synonymously)
 Logic level


0 and 1 do not present actual
numbers but instead represent the
state of a voltage variable
3-2 Truth tables
 Describing how a logic circuit’s
output depends on the logic level of
circuit’s input(2N possible inputs)
 Fig. 3-1 Truth Table(2, 3, 4 inputs)
Digital Systems
Tab. 3-1
Logic 0
FALSE
Off
Low
No
Open
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Fig. 3-1
Logic 1
TRUE
On
High
Yes
Close
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
(c)
Chap. 3 Logic Gates/Boolean Algebra
B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
B
x
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
?
A
0
0
1
1
x
B
0
1
0
1
x
1
0
1
0
(a)
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
x
0
1
1
0
0
0
0
1
(b)
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Dept. of Info. & Comm.
3-2

3-3 OR Operation with OR gates
A
0
0
0
0
1
1
1
1
 Output x is a logic 1 if one or more inputs are 1(Fig. 3-2(a))
 Boolean expression : x = A + B
 x= 1 + 1 = 1,
 x = 1 + 1 + 1 = 1,
 x = 1 + 1 + …+ 1 = 1
A
0
0
1
1
x= A+B
0
1
1
1
X= A+B
A
B
 OR Gate : Fig. 3-2(b)
 Multiple input OR Gate : Fig. 3-3
B
0
1
0
1
B
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
X= A+B+C
A
B
C
Fig. 3-2 Truth Table and Symbol
x= A+B+C
0
1
1
1
1
1
1
1
Fig. 3-3 Three-input OR
 Exam. 3-1 : Alarm is activated if temperature or pressure exceed a reference
 Exam. 3-2 : Determine the OR gate output in Fig. 3-5
 Exam. 3-3 : Same time transition in A and B input, Glitch or Spike

3-4 AND Operation with AND gates
A
0
0
1
1
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

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Output x is 1 only when all inputs are 1
Boolean expression : x = AB = A•B
OR Gate : Fig. 3-7(b)
Multiple input OR Gate : Fig. 3-8
 Exam. 3-4, 3-5A, 3-5B
Fig. 3-7
Digital Systems
B
0
1
0
1
x= AB
0
0
0
1
X= AB
A
B
Truth Table and Symbol
Chap. 3 Logic Gates/Boolean Algebra
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
x= ABC
0
0
0
0
0
0
0
1
X= ABC
A
B
C
Fig. 3-8 Three-input AND
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3-3

3-5 NOT Operation
A
0
1
 Single input operation, Complement of input
 NOT operation : x= A
X= A
A
x
A
 NOT circuit : Inverter(Fig. 3-11(b))

x= A'
1
0
3-6 Describing Logic Circuits Algebraically
1
0
1
0
Fig. 3-11 Truth Table, Symbol, waveform
 Boolean logic can describe any logic circuit by Boolean expression.
 Order of precedence : Parentheses, NOT, AND, OR
 Fig. 3-12, 13, 14, 15

3-7 Evaluating Logic Circuit Output
 Given a Boolean expression
 Evaluate output for given inputs
 Exam. : Fig. 3-15(a)
» A=0, B=1, C=1, D=1

Exam. : Fig. 3-15(b)
» A=0, B=0, C=1, D=1, E=1
Digital Systems
x  ABC( A  D )
x  [ D  ( A  B)  C ]  E
 0  1  1  (0  1)
 [1  (0  0)  1]  1
 1  1  1  (0  1)
 [1  0  1]  1
 1  1  1  (1)
 111 0
0
 [1  0]  1
 [1  1]  1
 11
1
Chap. 3 Logic Gates/Boolean Algebra
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Dept. of Info. & Comm.
3-4
 Evaluation rule for Boolean expression
1) Perform all inversions of single terms
2) Perform all operations within parentheses
3) Perform an AND operation before an OR operation
4) If an expression has a bar over it, perform the expression first and then
invert the result
 Determining output level from a diagram
 The output can be determined directly from the circuit diagram without using
1
A 0
Boolean expression.

3-8 Implementing circuits from Boolean
expression
B 1
C 1
 Circuit can be implemented from expression
 y  AC BC  ABC
AC
BC
ABC
D 1
1
0
x 0
Fig. 3-16 Determining the output from a diagram
A
y  AC BC  ABC
1
0
AC
BC
B
C
y  AC BC  ABC
ABC
Fig. 3-17 Constructing a logic circuit from a Boolean expression
Digital Systems
Chap. 3 Logic Gates/Boolean Algebra
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
3-9 NOR gates and NAND gates
 NOR gate : x  A  B
 Exam. 3-8, 3-9
x  A B
 NAND gate : x  A  B
 Exam. 3-10, 3-11, 3-12

A
0
0
1
1
B
0
1
0
1
A+B
0
1
1
1
A+B
1
0
0
0
Fig. 3-19 NOR Gate
x  A B
A
0
0
1
1
B
0
1
0
1
AB
0
0
0
1
AB
1
1
1
0
Fig. 3-22 NAND Gate
3-10 Boolean Theorems
 Single variable theorems(Fig. 3-25)
 x • 0 = 0, x • 1 = x, x • x = x, x • x = 0
 x + 0 = x, x + 1 = 1, x + x = x, x + x = 1
 Multivariable theorems
Commutative laws
 x + y = y + x, x.y = y.x
 x + (y + z) = (x + y)+ z = x + y + z, x (yz) = (xy)z = xyz,
 x (y + z) = xy + xz, (w + x)(y + z) = wy + xy + wz + xz
 x + xy = x : P.81 case 1,2,3,4 or x + xy = x(1+y) = x•1= x
 x + x y= x = y : (x + x)•(x + y) = 1 •(x + y) = x + y
Associative laws
Distributive laws
 Exam. 3-13, 3-14, 3-15
Digital Systems
Chap. 3 Logic Gates/Boolean Algebra
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
3-11 DeMorgan’s Theorems
 DeMorgan’s Theorems
 ( x  y)  x  y
 ( x  y)  x  y
x y

x y  x y
x  y  x y
( x  y  z)  x  y  z
( x  y  z)  x  y  z

xy  x y
x  y  xy
x y
x  y  xy
xy  x y
Fig. 3-26, 27 Equivalent circuits implied by DeMorgans Theorems
 Exam.
x  ( AB  C )
 Exam.
 Exam.
 Exam.
w  ( A  BC)  ( D  EF )
z  A B C
 ( AB )  C
 A  (B  C)
 ( A  BC)  ( D  EF )
 (A  B )C
 A  (B  C )
 ( A  BC)  ( D  EF )
 A  (B  C )
 [ A  ( B  C )]  [ D  ( E  F )]
 ( A  B)  C
 A  C  BC
x  AB  CD  EF
 AB  CD  EF
 AB  CD  EF
 Exam. 3-16
z  ( A  C)  (B  D )
 ( A  C)  (B  D )
 ( A  C )  (B  D )
 AC  B  D
 AB  AC  DE  DF
 Exam. 3-17 : Determine the output expression and simplify it
using DeMorgan Theorems
z  A B C
 A  B C
 A  B C
Digital Systems
Chap. 3 Logic Gates/Boolean Algebra
© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.
3-7

3-12 Universality of NAND and NOR gates
 Implement any logic expression using only NAND or NOR gates
x  A A  A
A B
A
x  AB

x  A A  A
A B

x  A  B  A B
A

B

x  A B

x  A  B  A B

B
Fig. 3-29, 30 NAND/NOR gates can be used to implement any Boolean operation
 Exam. 3-18 : A conveyer belt will shut down whenever specific conditions
occur(x = AB + CD)

74LS00 NAND, 74LS08 AND, 74LS32 OR gate 사용(Fig. 3-31)
Fig. 3-32 Possible implementation
Digital Systems
Chap. 3 Logic Gates/Boolean Algebra
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
3-13 Alternate Logic-Gate Representations
 Standard Logic Symbols : AND, OR, Inverter, NAND, NOR
 Alternate Logic Symbols : Fig. 3-33
1) Add bubbles on input and output lines that do not have bubbles, and Remove
bubbles that are already there
2) Change the operation symbol from AND to OR, or from OR to AND(Inverter is
not changed)
A  B  A B
 Note:
A B

» The equivalence can be extended to gates with any
number of inputs
A  B  A B
A B
» None of the standard symbols have bubbles on their
inputs, but all the alternate symbols have bubbles on
their inputs
A  B  A B
A B
» The standard and alternate symbols for each gate
represent the same physical circuit(No differences)
A  B  A B
A B
» NAND and NOR gates are inverting gates(both the
standard and the alternate symbols have a bubble
A
A
on either the input or the output)
» AND and OR gates are non-inverting gates(the
alternate symbols have bubbles on both inputs and
outputs)
Fig. 3-33 Standard and alternate symbols




Digital Systems
Chap. 3 Logic Gates/Boolean Algebra
© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.
3-9
 Logic Symbol Interpretation
 Active-HIGH : An input or output line has no bubbles
 Active-LOW : An input or output line does have bubbles
Active-HIGH
Active-LOW
A B
Active-HIGH
Active-LOW
Output goes LOW only
when all inputs are HIGH
Output goes HIGH only
when any inputs are LOW
A  B  A B
Fig. 3-34 Interpretation of the two NAND gates
 Exam. 3-19 : Give the interpretation of the two OR gate symbols
A B
Output goes HIGH only
when any inputs are HIGH
Output goes LOW only
when all inputs are LOW
A  B  A B
Fig. 3-35 Interpretation of the two OR gates

3-14 Which Gate Representation to Use
 Proper use of the alternate gate can make the circuit operation much clear
Active-HIGH
Output goes HIGH
whenever either
A=B=1 or C=D=1
Original Circuit
Digital Systems
Active-LOW
Output goes LOW only
when A or B=0 and
C or D=0
Fig. 3-36 Alternate Representation
Chap. 3 Logic Gates/Boolean Algebra
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Dept. of Info. & Comm.
3-10
 Which Circuit Diagram Should be Used?
 The answer to this question depends on the particular function being
performed by the circuit output
» If the circuit is used to turn on/off an LED, Relay, or Motor


Active-HIGH : On when output goes to 1
Active-LOW : On when output goes to 0
 Bubble Placement
 Whenever possible, choose gate symbols
» Bubble outputs connected to bubble inputs(Fig. 3-36 (b))
» Non-bubble outputs connected to non-bubble inputs(Fig. 3-36 (c))
 Exam. 3-20, 21, 22, 23
 Asserted Levels
 Asserted = Active
 Unasserted = Inactive
Address Decode 회로
 Labeling Active-LOW Logic Signals
 Over-bar = Active Low Signal
 Labeling Bi-state Signals
 Output signals have two active states
Digital Systems
RD, ROM  A, ROM  B, RAM, MEM
RD / WR , CONT / DATA
Chap. 3 Logic Gates/Boolean Algebra
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