Silicon strips readout using Deep Sub

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Transcript Silicon strips readout using Deep Sub

130nm Digital Sampler chip New results

Jean François Genat

on behalf of D. Fougeron, 1 R. Hermel 1 , H. Lebbolo 2 , T.H. Pham 2 , R. Sefri, 2 and A. Savoy-Navarro 2

1 LAPP Annecy, 2 LPNHE Paris

5th SiLC Meeting, April 25-27 th 2007, Prague

Outline

• • • • • Goals Last results New results Further tests Next chip

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Goals

Full readout chain integration in a single chip - Preamp-shaper - Trigger decision (analog sums) - Pulse Sampling: Analog pipe-lines - On-chip digitization: ADC - Buffering and pre-processing: Centroids, Least square fits, - Lossless compression and error codes - Calibration and calibration management - Power switching (ILC timing) • CMOS 130nm 2006 • CMOS 90nm 2007 • 512-1024 channels envisaged This chip yes yes yes yes yes no no no no yes no 4 channels

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Front-end in 130nm

130nm CMOS: Smaller Faster More radiation tolerant Lower power Will be (is) dominant in industry Drawbacks: - Reduced voltage swing (Electric field constant) - Leaks (gate/subthreshold channel) - Models more complex, not always up to date - Crosstalk (digital-analog)

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Under tests

2006 Chips Summary

130nm Chip #1 (4 channels) Chip #2 Preamp-shapers + Sparsifier Pipeline 1 ADC Digital (One channel) Preamp-shapers + Sparsifier DC servo Pipeline 2 DAC Test structures : MOSFETS, passive

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

4-channel chip

Strip Channel n+1 Sparsifier

S a

i V i > th Time tag Channel n-1 reset reset Analog samplers, (slow) Preamp + Shapers

UMC CMOS 130nm

Wilkinson ADC Can be used for a “trigger” Counter Ch # Waveforms Clock 3-96 MHz

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Targeted

Amplifier: Shaper: Sparsifier: Sampler: ADC: 20 mV/MIP gain threshold on analog sum 16-deep 10-bit Noise: Measured with 180nm CMOS: 375 + 10.5 e-/pF @ 3 m s shaping, 90 m W power

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Outline

• • • • • 130 nm chip goals February results Present results Further tests Next chip

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Silicon

180nm 130nm Picture

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

130nm chip noise results (2/’07)

Gain OK: 30 mV/MIP Dynamics: 30 MIPs @ 5% OK OK Peaking time: .8 – 2

s .7 - 3

Power (Preamp+ Shaper) = 290 m W Noise: 130nm @ 0.8 m s : 850 + 14 e-/pF 130nm @ 2 m s : 625 + 9 e-/pF 625*sqrt(2/3 m

)=510

e-/pF

180nm @ 3 m s : 375 + 10.5 e-/pF

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Outline

• • • • • 130 nm chip goals Last results Present results Further tests Next chip

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Analog pipeline output

Simulation of the analog pipeline Measured output of the ADC

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

ADC

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Sampler + ADC

Waveform biased by the output pad parasitic capacitance (~ 1pF) Chip130-2 under tests: buffer between sampler and ADC

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Outline

• • • • • 130 nm chip goals Last results Present results Further tests Next chip

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

130-1 next tests

Measure ADC extensively Linearities integral, differential Noise fixed pattern, random Speed maximum clock rate

Effective number of bits (ENOB) J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

DC Servo Channel n-1 Channel n+1

130nm Chip 2

Sparsifier

S a

i V i > th Analog Pipe-line Preamp and Shapers ADC

ramp

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

130-2 tests (LAPP Annecy)

Measure improved pipeline extensively Denis Fougeron’s (LAPP) design Linearities integral, differential Noise fixed pattern, random Speed maximum clock rate Droop Hold data for 1ms at ILC

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Outline

• • • • • 130 nm chip goals Last results Present results Further tests Next chip

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Next chip

Equip a detector: Lab test bench and 2007 beam-tests 130nm chips 1 + 2 128 channels Preamp-shapers + sparsifier Pipeline ADC Digital Calibration Power cycling

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Power cycling Switch the current sources between zero and a small fraction (10 -2 to 10 -3 ) This option switches the current source feeding both the preamplifier & shaper between 2 values to be determined by simulation. Zero or a small fraction (0.1% - 1%) of biasing current is held during « power off ».

Zero-power option tested on 180nm chip with 2 ms recover time constant

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Planned Digital Front-End

Chip control Buffer memory Processing for - Calibrations - Amplitude and time least squares estimation, centroids - Raw data lossless compression Tools - Digital libraries in 130nm CMOS available - Synthesis from VHDL/Verilog - SRAM - Some IPs: PLLs - Need for a mixed-mode simulator

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

Some issues with 130nm design Noise likely not model pessimistic, but measured acceptable Design rules more constraining Some (via densities) not available under Cadence Calibre (Mentor) required Lower power supplies voltages Low Vt transistors leaky (Low leakage option available)

J-F Genat, 5 th SiLC meeting, Prague, April 25-27th 2007

The End

…

Backup

Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

Possible issues: noise: 130nm vs 180nm (simulation)

PMOS:

130nm W/L = 2mm/0.5u

Ids = 38.79u,Vgs=-190mV,Vds=-600mV gm=815.245u,gms=354.118u

1MHz



7.16nV/sqrt(Hz)

Thermal noise hand calculation = 3.68nV/sqrt(Hz) 180nm gm=944.4uS,gms=203.1uS

1MHz



3.508nV/sqrt(Hz)

Thermal noise hand calculation = 3.42nV/sqrt(Hz) Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

Noise: 130nm vs 180nm (simulation)

NMOS :

130nm W/L = 50u/0.5u

Ids=48.0505u,Vgs=260mV,Vds=1.2V

gm=772.031uS,gms=245.341uS,gds=6.3575uS

1MHz --> 24.65nV/sqrt(Hz)

100MHz --> 5nV/sqrt(Hz) Thermal noise hand calculation = 3.78nV/sqrt(Hz) 180nm W/L=50u/0.5u

Ids=47uA,Vgs=300mV,Vds=1.2V

gm=842.8uS,gms=141.2uS,gds=16.05uS

1MHz --> 4nV/sqrt(Hz)

10MHz --> 3.49nV/sqrt(Hz) Thermal noise hand calculation = 3.62nV/sqrt(Hz) Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

Preamp CR RC Shaper Follower Comparator

130-90nm noise evaluation (STM process)

L. Ratti et al FE2006 Perugia

100 m A 1 MHz 1mA

J-F Genat 4th SiLC Workshop Dec 18 th – 20 th 2006 Barcelone

Noise origin

Thermal noise white 4 kT/g 1/f noise due to: m Excess noise: not so white… due to process features (?) - Traps at the gate dielectrics interfaces - Mobility fluctuations in the channel UMC models and measurements: - The gate dielectric in 130nm induces more traps compared to 180nm degrading 1/f noise. No more S i O 2 in 90nm next generation CMOS -> hi k dielectrics (Hf, Zr …) - Some thermal excess noise shows up Ratti et al. (Pavia, Bergamo), CERN: - Both ST90nm and IBM 130nm show better 1/f noise performance To be looked at : UMC 90nm simulations

J-F Genat 4th SiLC Workshop Dec 18 th – 20 th 2006 Barcelone

Backup

Silicon strips readout using CMOS Deep Sub-Micron Technologies Jean-Francois Genat Leuven, Feb 26 th 2007 2 J. David, H. Lebbolo 2 2 M. Dellhot, D. Fougeron, 1 R. Hermel 1 , , T.H. Pham 2 , F. Rossel 2 , A. Savoy-Navarro 2 , R. Sefri 2 , S. Vilalte 1

1 LAPP Annecy, 2 LPNHE Paris Help from IMEC-Leuven (Europractice)

C. Das, E. Deumens, P Malisse

Outline • • • • • • Detector data Technologies Front-End Electronics 180nm chip 130nm chips Future plans

Silicon strips parameters 4-5 10 6 Silicon strips 10 - 60 cm long Thickness Inner : 150 -200 m m Outer : -400 m m Strip pitch 50 m m Inner : Double Outer : Single sided AC sided DC coupled coupled

Silicon strips data at the ILC Pulse height: Cluster centroid to get a few µm position resolution

Detector pulse analog sampling to get accurate charge estimation

Time: Two scales: Coarse : 150-300 ns for BC identification, 80ns sampling

Shaping time of the order of the microsecond

Fine: nanosecond timing for the coordinate along the strip 10ns sampling Not to replace another layer or double sided Position estimation to a few cm using pulse reconstruction from samples

Shaping time: 20-50 ns

Coordinate along the strip L =28nH R =5 W C i =500 fF SPICE

15 ns 90cm V = 6 10 7 m/s= c/5

C s = 100 fF

 1 /

1 ns time resolution is 6 cm

Measured Pulse Velocity

Measured velocity: 5.5cm/ns Measured moving a laser diode along 24 cm

Outline • • • • • • Detector data Technologies Front-End Electronics 180nm chip 130nm chips Future plans

Technologies Front-end chips: Thinner CMOS processes 250, 180, 130, 90 nm now available from UMC, TSMC SiGe, less 1/f noise, faster Chip thinning down to 50 m m ?

More channels on a chip, more functionalities, less power

Connectivity: 3D ? On detector bump-bonding ? Stud bonding ?

Stud bonding sufficient if pitch more than 50

m Smaller pitch detectors, better position and time resolution.

Less material

Outline • • • • • • Detector data Technologies Front-End Electronics 180nm chip 130nm chips Future plans

Integrated functionalities Full readout chain integration in a single chip - Preamp-shaper - Trigger decision (analog sums) : compact data - Sampling: Analog pipe-lines - On-chip digitization - Buffering - Digital Processing: Centroids and Least Squares time/amplitude estimation - Calibration and calibration management - Power switching Presently 128 channels (APV, SVX) chips, 256-1024 envisaged

Front-End Chip

Integrate 512-1024 channels in 90nm CMOS:  Charge Amplifiers: 20-30 mV/MIP over 30 MIP   Shapers: - slow 500 ns – 1 m s - fast 20-50 ns Zero-suppression: threshold the sum of adjacent channels  2D analog memory: - 8-16 samples 80 ns and 10 ns sampling clocks Event buffer 16-deep     ADC: 10 bits Buffering Calibration Power switching saves a factor 100-200

ILC timing:

1 ms: ~ 3-6000 trains @150-300ns / BC 200ms in between

Foreseen Front-end architecture

Channel n+1 Channel n-1 reset Strip Sparsifier

S a

i V i > th Time tag reset Analog samplers, slow, fast Wilkinson ADC ‘trigger’ Calibration Control Preamp + Shapers Counter Ch # Waveforms Storage Charge 1-40 MIP, Time resolution: BC tagging 150-300ns, fine: ~ 1ns

Technologies: Deep Sub-Micron CMOS 180-130nm Future: SiGe &/or deeper DSM

Outline • • • • • • Detector data Technologies Front-End Electronics 180nm chip 130nm chips Future plans

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

Silicon 2005 - Preamp - Shaper - Sample & Hold - Comparator 3mm 16 + 1 channel UMC 180nm chip (layout and picture)

Process spreads

Process spreads: 3.3 % (same wafer)

Preamp gains statistics (same wafer)

Shaper output noise 375 e- RMS 375 e- +10.4 e-/pF input noise with chip-on-board wiring 275 + 8.9/pFsimulated

Linearities 180nm chip +/-1.5% +/-0.5% expected +/-6% +/-1.5% expected

Tests conclusions on UMC 180 nm chips 12 chips tested (end 2005) The UMC CMOS 180nm process is mature and reliable: - Models mainly OK - Only one transistor failure over 12 chips - Process spreads of a few % 90 Sr Source tests with 180nm chip connected to a Si detector and compared with VA1 chip from Ideas (see test bench section) S/N ~ 10 still system noise dominating

Outline • • • • • • Detector data Technologies Front-End Electronics 180nm chip 130nm chips Future plans

Front-end in CMOS 130nm 2006-2007 130nm CMOS motivations: Benefits - Smaller - Faster - More radiation tolerant - Less power - Presently dominant in the IC industry Issues: - Design more constraining (Design rules) - Reduced voltage swing (Electric field constant) - Leaks (gate/subthreshold channel) - Models more complex, sometimes still not accurate

UMC Technology parameters 180 nm 130nm • 3.3V transistors yes • Logic supply 1.8V • Metals layers 6 Al • MIM capacitors • Transistors 1fF/mm² yes 1.2V

8 Cu 1.5 fF/mm

Three Vt options Low leakage option Useful for analog storage during < 1 ms

130nm 4-channel test chip

Channel n+1 Zero-suppression

S a

i V i > th Time tag Strip Channel n-1 reset reset Analog samplers, (slow) Preamp + Shaper DC servo implemented for DC coupled detectors

UMC CMOS 130nm Received in 2006 Being tested: Analog OK, Digital under tests

Ramp ADC Counter Can be used for a “trigger” Ch # Waveforms Clock 3-96 MHz

Analog pipeline simulation

Silicon

180nm 130nm Picture

Noise 130nm vs 180nm (simulation)

PMOS:

180nm gm=944.4uS

Id = 30 uA Weak inversion

1MHz



3.508nV/sqrt(Hz)

Thermal noise hand calculation = 3.42nV/sqrt(Hz) 130nm gm=815.245uS

Id =60 uA Moderate inversion

1MHz



7.16nV/sqrt(Hz)

Thermal noise hand calculation = 3.68nV/sqrt(Hz) Measurements on 130nm show 2 x better results !

130nm-1 design Noise models pessimistic ? 130nm CMOS Silicon actually 2x better !

Design rules more constraining Post layout simulations at Leuven (Mentor) Some design rules (via densities) not available under Cadence Calibre (Mentor) required

Go to 90 nm ?

130nm-1 conclusions Good matching wrt simulation Except noise which is… much better ! - Still lot to test: pipe-line and digital - Statistics available from two wafers (70 chips) Very encouraging results

130nm-2 design

One channel version with - Servo DC - Improved pipe-line - Calibration DAC

Layout Picture One channel 1.5 x 1.5 mm 2

130nm-2 architecture DC servo to accommodate DC coupled DAC + calibration, Improved pipe-line detectors,

Preamp Shaper Analog sampler DC reference

Received January 5 th 2007 Test card under wiring Test stand under work

Planned on-chip digital Chip control Buffer memory Processing for - Calibrations - Amplitude and time least squares estimation, centroids Tools - Digital libraries in 130nm CMOS available (VST) - Place & Route tools: Cadence + design kits from Europractice (Leuven, Belgium) Mixed mode needed - Synthesis from VHDL/Verilog - Some IPs: PLLs, SRAM

Wiring Detector to FE Chips Wire bonding Flip Chip Technology

Courtesy: Marty Breidenbach (Cal SiD) OR (later)

Wiring Detector to FE Chips

Courtesy: Ray Yarema, FEE 2006, Perugia

3D Wiring

Courtesy: Ray Yarema, FEE 2006, Perugia

Manuel Lozano (CNM Barcelona)

Chip connection

• Wire bonding – Only periphery of chip available for IO connections – Mechanical bonding of one pin at a time (sequential) – Cooling from back of chip – High inductance (~1nH) – Mechanical breakage risk (i.e. CMS, CDF) • Flip-chip – Whole chip area available for IO connections – Automatic alignment – One step process (parallel) – Cooling via balls (front) and back if required – Thermal matching between chip and substrate required – Low inductance (~0.1nH)

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

Manuel Lozano (CNM Barcelona)

Bump bonding flip chip technology

• Electrical connection of chip to substrate or chip to chip face to face flip chip • Use of small metal bumps bump bonding •

CNM

Process steps: – Pad metal conditioning: Under Bump Metallisation (UBM) – Bump growing in one or two of the elements – Flip chip and alignment – Reflow – Optionally underfilling

Manuel Lozano (CNM Barcelona)

Bump bonding flip chip technology

• Expensive technology – Especially for small quantities (as in HEP) – Big overhead of NRE costs • Minimal pitch reported: 18 µm but ...

• Few commercial companies for fine pitch applications (< 75 µm) • Bumping technologies – Evaporation through metallic mask – Evaporation with thick photoresist – Screen printing – Stud bumping (SBB) – Electroplating – Electroless plating – Conductive Polymer Bumps – Indium evaporation

The End

…

The SiTR-130_1 chip

180nm 130nm Picture

Possible issues: noise: 130nm vs 180nm (simulation)

PMOS:

180nm gm=944.4uS

1MHz



3.508nV/sqrt(Hz)

Thermal noise hand calculation = 3.42nV/sqrt(Hz) 130nm gm=815.245uS

1MHz



7.16nV/sqrt(Hz)

Thermal noise hand calculation = 3.68nV/sqrt(Hz)

Measurements show 2 times better results

SiTR-130_1 tests results

Gain OK: 30 mV/MIP Dynamics: 30 MIPs @ 5% OK OK Peaking time: 0.8 – 2 m s 0.7 - 3 m s Noise comparative Power (Preamp+ Shaper) = 300 m W 130nm @ 0.8 m s : 850 + 14e-/pF 130nm @ 2 m s : 625 + 9e-/pF 180nm @ 3 m s : 360 + 10.5 e-/pF

Some issues with 130nm design Noise models pessimistic, Silicon actually much better !

Design rules more constraining Some design kits are not fully developed and thus additional effort needed

Power dissipation budget

(measured) 180nm/ch Preamp 90 Shaper Zero suppr.

Pipe line 180 Total Analog 270 ADC Logic Total Digital 130nm/ch Common 148 148 198 10 100 575 66 5 96 101

Final goal: ≤ 1 mWatt/channel all included (looks achievable)

Next developments Implement the fast (20-50ns shaping) version in Silicon-Germanium including: - Preamp + Shaper (20-100ns) - Fast sampling Submit a full 128 channel version in 130nm CMOS including slow and fast analog processing, power cycling, digital

Planned on-chip digital Chip control Buffer memory Processing for - Calibrations - Amplitude and time least squares estimation, centroids Tools - Digital libraries in 130nm CMOS available (VST) - Place & Route tools: Cadence + design kits from Europractice (Leuven, Belgium) - Synthesis from VHDL/Verilog - Some IPs: PLLs, SRAM

Chip connection on µstrips • Wire bonding – Only periphery of chip available for IO connections – Mechanical bonding of one pin at a time (sequential) – Cooling from back of chip – High inductance (~1nH) – Mechanical breakage risk • Flip-chip – Whole chip area available for IO connections – Automatic alignment – One step process (parallel) – Cooling via balls (front) and back if required – Thermal matching between chip and substrate required – Low inductance (~0.1nH)

Planned on-chip digital Chip control Buffer memory Processing for - Calibrations - Amplitude and time least squares estimation, centroids Tools - Digital libraries in 130nm CMOS available (VST) - Place & Route tools: Cadence + design kits from Europractice (Leuven, Belgium) - Synthesis from VHDL/Verilog - Some IPs: PLLs, SRAM

1st step: bump bonding FE on detector Studying flip-chip FEE chips on strips IMB-CNM, VTT, HIP, LPNHE, Liverpool (firms) • Design of the fan-in fan-out on the µstrip sensor 1st case: 128 ch 2nd case: 1024 channel The design is starting have a foundry or a firm ready to implement it on the sensor • Bump bonding of the FEE chip crucial issue here: have a working chip with the required nb of channels (by end 2007)

2nd step: cabling => use: Tape Automated Bonding (TAB) or????????

Don’t forget auxiliary electronics that degrade any fancy solution on paper ex: decoupling capacitors

A few words about cabling and connection to the overall DAQ system: preliminary thoughts • A preparer…

2nd step: cabling => use: Tape Automated Bonding (TAB) or????????

Don’t forget auxiliary electronics that degrade any fancy solution on paper ex: decoupling capacitors

Planned on-chip digital Chip control Buffer memory Processing for - Calibrations - Amplitude and time least squares estimation, centroids Tools - Digital libraries in 130nm CMOS available (VST) - Place & Route tools: Cadence + design kits from Europractice (Leuven, Belgium) - Synthesis from VHDL/Verilog - Some IPs: PLLs, SRAM

2nd step: cabling => use: Tape Automated Bonding (TAB) or????????

Don’t forget auxiliary electronics that degrade any fancy solution on paper ex: decoupling capacitors

backup

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

Beam-tests at DESY

October 2006

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

Wiring Detector to FE Chips Wire bonding Flip Chip Technology

Courtesy: Marty Breidenbach (Cal SiD) OR (later)

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

Wiring Detector to FE Chips

Courtesy: Ray Yarema, FEE 2006, Perugia

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

3D Wiring

Courtesy: Ray Yarema, FEE 2006, Perugia

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

Manuel Lozano (CNM Barcelona)

Chip connection

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

Manuel Lozano (CNM Barcelona)

Bump bonding flip chip technology

• Electrical connection of chip to substrate or chip to chip face to face flip chip • Use of small metal bumps bump bonding

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

•

CNM

Process steps: – Pad metal conditioning: Under Bump Metallisation (UBM) – Bump growing in one or two of the elements – Flip chip and alignment – Reflow – Optionally underfilling

Manuel Lozano (CNM Barcelona)

Bump bonding flip chip technology

• Expensive technology – Especially for small quantities (as in HEP) – Big overhead of NRE costs • Minimal pitch reported: 18 µm but ...

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

Noise: 130nm vs 180nm (simulation)

NMOS :

130nm W/L = 50u/0.5u

Ids=48.0505u,Vgs=260mV,Vds=1.2V

gm=772.031uS,gms=245.341uS,gds=6.3575uS

1MHz --> 24.65nV/sqrt(Hz)

100MHz --> 5nV/sqrt(Hz) Thermal noise hand calculation = 3.78nV/sqrt(Hz) 180nm W/L=50u/0.5u

Ids=47uA,Vgs=300mV,Vds=1.2V

gm=842.8uS,gms=141.2uS,gds=16.05uS

1MHz --> 4nV/sqrt(Hz)

10MHz --> 3.49nV/sqrt(Hz) Thermal noise hand calculation = 3.62nV/sqrt(Hz)

J-F Genat, LECC06, Valencia, Sept 25-29th 2006

Noise: 130nm vs 180nm (UMC) Models

1/f NMOS 130/180: factor 6 worse Thermal 130/180: factor 1.4 worse 130nm

W/L = 50/0.5 Ids=48 uA gm=770uS

1MHz --> 24 nV/sqrt(Hz)

100MHz --> 5nV/sqrt(Hz) Calculation = 3.8nV/sqrt(Hz)

180nm

W/L=50/0.5 Ids=47uA gm=840uS

1MHz --> 4 nV/sqrt(Hz)

10MHz --> 3.5nV/sqrt(Hz) Calcualtion= 3.6nV/sqrt(Hz) Measurements give an overall factor of 1.5 between 130 and 180nm at 800 ns and 3 m s shaping time (look at 130nm at 2 m s)

J-F Genat 4th SiLC Workshop Dec 18 th – 20 th 2006 Barcelone

Manuel Lozano (CNM Barcelona)

Chip connection

Manuel Lozano (CNM Barcelona)

Bump bonding flip chip technology

• Electrical connection of chip to substrate or chip to chip face to face flip chip • Use of small metal bumps bump bonding •

CNM

Process steps: – Pad metal conditioning: Under Bump Metallisation (UBM) – Bump growing in one or two of the elements – Flip chip and alignment – Reflow – Optionally underfilling

Manuel Lozano (CNM Barcelona)

Bump bonding flip chip technology

• Expensive technology – Especially for small quantities (as in HEP) – Big overhead of NRE costs • Minimal pitch reported: 18 µm but ...

0.18 m chip

PREAMPLIFIER

Reset FET Gain: 8mV/MIP 3.3V input trans 2000/0.5

gm = 0.69 mS 40 m A (Weak inversion IC ~= 0.01

)

Tests results :

Gain

Linearity Noise 3

: +/-1.5% +/-0.5% expected m

s-20

s rise-fall, 40

: 498 + 16.5 e-/pF OK

Dynamic range

: 60 MIPs OK Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

0.18 m chip

SHAPER

RC-CR Peaking time ajustable :1 m s -> 5 m s

Tests:

1.5 - 6 m s rise/fall Linearity: +/- 6%

Noise @ 3

+/- 1% expected m

s 140

W power

: 375 + 10.4 e-/pF 274 + 8.9 e-/pF expected Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

Circuit en 0.13

m

PREAMPLIFIER Gain

: 28.5mV/MIP

3.3V transistor d’entrée gm

= 1.5 mS/ ~70 m A

Capacité de charge

1.5m/0.5

= 133 fF m m

Plage de dynamique

: 17MIPs (linearit é = 1% a 17MIPs)

Bruit@70

= 1000e + 25e-/pF

SHAPER Filtre RC-CR Temps adjust é

:0.7

m s -> 3 m s

bruit@700ns bruit@3

= 335+22e /pF = 305+16 e-/pF

Plage de dynamique

: 17MIPS Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

0.13 m Chip Sparsifier

SPARSIFICATION

+ Sum of3 adjacent channels + R ésolution ~ 0.1mV

+ Response time = 186ns Sommateur Offset cancel Ref Comparateur Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

0.13 m Chip Simulations

SIMULATIONS :

Preamps linearity Shaper linearity Sparsifier response

Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

Possible issues: Transistors leaks

Two situations: - Gate-channel due to tunnel effect (can affect noise performances)

- Through channel when transistor switched-off (only affects large digital

designs) Sub-threshold current

Nano-CMOS Circuit and Physical design B.P Wong, A. Mittal, Y. Cao, G. Starr, 2005, Wiley 130 nm 180 nm 90 nm Gate leakage - 180nm chip OK - 130nm, no gate leakage expected, but sub-threshold - 90nm, important gate leakage Scale: 1 nA/ m m = 8000 e- noise in FE Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

Possible issues: noise: 130nm vs 180nm (simulation)

PMOS:

130nm W/L = 2mm/0.5u

Ids = 38.79u,Vgs=-190mV,Vds=-600mV gm=815.245u,gms=354.118u

1MHz



7.16nV/sqrt(Hz)

Thermal noise hand calculation = 3.68nV/sqrt(Hz) 180nm gm=944.4uS,gms=203.1uS

1MHz



3.508nV/sqrt(Hz)

Thermal noise hand calculation = 3.42nV/sqrt(Hz) Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool

Noise: 130nm vs 180nm (simulation)

NMOS :

130nm W/L = 50u/0.5u

Ids=48.0505u,Vgs=260mV,Vds=1.2V

gm=772.031uS,gms=245.341uS,gds=6.3575uS

1MHz --> 24.65nV/sqrt(Hz)

100MHz --> 5nV/sqrt(Hz) Thermal noise hand calculation = 3.78nV/sqrt(Hz) 180nm W/L=50u/0.5u

Ids=47uA,Vgs=300mV,Vds=1.2V

gm=842.8uS,gms=141.2uS,gds=16.05uS

1MHz --> 4nV/sqrt(Hz)

10MHz --> 3.49nV/sqrt(Hz) Thermal noise hand calculation = 3.62nV/sqrt(Hz) Jean-Fran çois Genat 3d SiLC Workshop, June 13-14th 2006, Liverpool